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www.renesas.com rev.3.00 sep 2010 user?s manual all information contained in these materials, including products and pr oduct specifications, represents information on the pr oduct at the time of publicati on and is subject to change by renesas electronics corp. without notice. please review the la test information published by renesas electronics corp. through various m eans, including the renesas electronics corp. website (http://www.renesas.com). v850es/jg3 user?s manual: hardware renesas mcu v850es/jg3 microcontrollers pd70f3739 pd70f3740 pd70f3741 pd70f3742 32
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1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
how to use this manual readers this manual is intended for users who wish to understand the functions of the v850es/jg3 and design application systems using the v850es/jg3. purpose this manual is intended to give users an understanding of the hardwar e functions of the v850es/jg3 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? data types ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to understand the overall func tions of the v850es/jg3 read this manual according to the contents . to find the details of a regi ster where the name is known use appendix c register index . register format the name of the bit whose number is in angle br ackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. to understand the details of an instruction function refer to the v850es architecture user?s manual available separately. to know the electrical spec ifications of the v850es/jg3 see chapter 29 electrical specifications the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that if ?xxx.yyy? is described as is in a program, however, the compiler/assembler cannot recognize it correctly.
conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3
related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/jg3 document name document no. v850es architecture user?s manual u15943e v850es/jg3 hardware user?s manual this manual documents related to development tools document name document no. qb-v850essx2 in-circuit emulator u17091e qb-v850mini on-chip debug emulator u17638e qb-mini2 on-chip debug emulator with programming function u18371e operation u17293e c language u17291e assembly language u17292e ca850 ver. 3.00 c compiler package link directives u17294e pm+ ver. 6.20 project manager u17990e id850qb ver. 3.20 integrated debugger operation u17964e sm850 ver. 2.50 system simulator operation u16218e sm850 ver. 2.00 or later system si mulator external part user open interface specification u14873e operation u17246e sm+ system simulator user open interface u17247e basics u13430e installation u17419e technical u13431e rx850 ver. 3.20 real-time os task debugger u17420e basics u13773e installation u17421e technical u13772e rx850 pro ver. 3.20 real-time os task debugger u17422e az850 ver. 3.30 system performance analyzer u17423e pg-fp4 flash memory programmer u15260e
caution: this product uses superflash ? technology licensed from silicon storage technology, inc. iecube is a registered trademark of renesas electronics corporation in japan and germany. minicube is a registered trademark of renesas electronics corporation in japan and germany or a trademark in the united states of america. eeprom is a trademark of re nesas electronics corporation. applilet is a registered trademark of renesas electronics in japan, germany , hong kong, china, the republic of korea, the united kingdom, and th e united states of america. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. superflash is a registered trademark of silicon st orage technology, inc. in several countries including the united states and japan. pc/at is a trademark of internati onal business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. tron is an abbreviation of the r ealtime operating system nucleus. itron is an abbreviati on of industrial tron.
contents chapter 1 introduction ...................................................................................................... ..............1 1.1 general ........................................................................................................................ ...............1 1.2 features....................................................................................................................... ...............3 1.3 application fields............................................................................................................. .........4 1.4 ordering information........................................................................................................... ......4 1.5 pin configuration (top view) ................................................................................................... 5 1.6 function block configuration ...................................... ............................................................7 1.6.1 internal bl ock di agram ......................................................................................................... .........7 1.6.2 internal units ................................................................................................................. ...............8 chapter 2 pin functio ns .................................................................................................... ........... 11 2.1 list of pin functions .......................................................................................................... .... 11 2.2 pin states ..................................................................................................................... ........... 19 2.3 pin i/o circuit types, i/o buffer power suppl ies, and connection of unused pins ....... 20 2.4 cautions ....................................................................................................................... ........... 24 chapter 3 cpu functio n ..................................................................................................... ........... 25 3.1 features....................................................................................................................... ............ 25 3.2 cpu register set ............................................................................................................... ..... 26 3.2.1 program regi ster set ........................................................................................................... .......27 3.2.2 system regi ster set ............................................................................................................ ........28 3.3 operation modes ................................................................................................................ .... 34 3.3.1 specifying oper ation mode...................................................................................................... ...34 3.4 address space.................................................................................................................. ...... 35 3.4.1 cpu address space .............................................................................................................. .....35 3.4.2 wraparound of cpu addr ess spac e ..........................................................................................36 3.4.3 memory map ..................................................................................................................... .........37 3.4.4 areas .......................................................................................................................... ...............39 3.4.5 recommended use of address s pace........................................................................................44 3.4.6 peripheral i/o regist ers ....................................................................................................... .......47 3.4.7 special r egister s .............................................................................................................. ..........57 3.4.8 cauti ons....................................................................................................................... ..............61 chapter 4 port functio ns ................................................................................................... ........ 64 4.1 features....................................................................................................................... ............ 64 4.2 basic port configuration ....................................................................................................... 64 4.3 port configuration ............................................................ ................................................. ..... 65 4.3.1 port 0 ......................................................................................................................... ................70 4.3.2 port 1 ......................................................................................................................... ................73 4.3.3 port 3 ......................................................................................................................... ................74 4.3.4 port 4 ......................................................................................................................... ................80 4.3.5 port 5 ......................................................................................................................... ................83 4.3.6 port 7 ......................................................................................................................... ................87 4.3.7 port 9 ......................................................................................................................... ................89 4.3.8 port cm........................................................................................................................ ..............97 4.3.9 port ct ........................................................................................................................ ..............99
4.3.10 port dh ........................................................................................................................ ............101 4.3.11 port dl........................................................................................................................ .............103 4.4 block diagrams................................................................................................................. .... 106 4.5 port register settings when alternate function is used ................................................ 136 chapter 5 bus control function ............................ .............................................................. 14 9 5.1 features....................................................................................................................... .......... 149 5.2 bus control pins............................................................................................................... .... 150 5.2.1 pin status when internal rom, internal ra m, or on-chip peripher al i/o is a ccessed ...............150 5.2.2 pin status in eac h operation mode ...........................................................................................150 5.3 memory block function....................................................................................................... 151 5.4 external bus interface mode control function ....... .......................................................... 152 5.5 bus access ..................................................................................................................... ...... 153 5.5.1 number of clo cks for a ccess .................................................................................................... 153 5.5.2 bus size setti ng func tion ...................................................................................................... ....153 5.5.3 access by bus si ze ............................................................................................................. .....154 5.6 wait function .................................................................................................................. ...... 161 5.6.1 programmable wa it func tion..................................................................................................... 161 5.6.2 external wait func tion......................................................................................................... ......162 5.6.3 relationship between programmabl e wait and exte rnal wa it ................................................... 163 5.6.4 programmable address wait func tion .......................................................................................164 5.7 idle state insertion function ............................................................................................... 165 5.8 bus hold function.............................................................................................................. .. 166 5.8.1 functional outlin e............................................................................................................. ........166 5.8.2 bus hold pr ocedur e............................................................................................................. .....167 5.8.3 operation in power save mode ................................................................................................167 5.9 bus priority ................................................................................................................... ........ 168 5.10 bus timing ..................................................................................................................... ....... 169 chapter 6 clock generation function ................ .............................................................. 175 6.1 overview....................................................................................................................... ......... 175 6.2 configuration .................................................................................................................. ...... 176 6.3 registers ...................................................................................................................... ......... 178 6.4 operation...................................................................................................................... ......... 183 6.4.1 operation of each cl ock ........................................................................................................ ...183 6.4.2 clock output functi on .......................................................................................................... .....183 6.5 pll function................................................................................................................... ...... 184 6.5.1 overvi ew....................................................................................................................... ...........184 6.5.2 regist ers...................................................................................................................... ............184 6.5.3 usage .......................................................................................................................... ............187 chapter 7 16-bit timer/event counter p (tmp) . ............................................................... 188 7.1 overview....................................................................................................................... ......... 188 7.2 functions...................................................................................................................... ......... 188 7.3 configuration .................................................................................................................. ...... 189 7.4 registers ...................................................................................................................... ......... 191 7.5 operation...................................................................................................................... ......... 203 7.5.1 interval timer mode (tpnmd2 to tpnmd0 bi ts = 000) ............................................................. 204 7.5.2 external event count mode (tpn md2 to tpnmd0 bits = 001) ................................................. 214 7.5.3 external trigger pulse output mode (tpnmd2 to tpnmd0 bits = 010) .....................................222
7.5.4 one-shot pulse output mode (tpn md2 to tpnmd0 bits = 011)............................................... 234 7.5.5 pwm output mode (tpnmd2 to tpnmd0 bi ts = 100) .............................................................. 241 7.5.6 free-running timer mode (tpnmd2 to tpnmd0 bi ts = 101) .................................................... 250 7.5.7 pulse width measurement mode (tpn md2 to tpnmd0 bits = 110)......................................... 267 7.5.8 timer output operati ons ........................................................................................................ ...273 7.6 selector function .............................................................................................................. ... 274 7.7 cautions ....................................................................................................................... ......... 276 chapter 8 16-bit timer/event counter q (tmq). ............................................................... 277 8.1 overview....................................................................................................................... ......... 277 8.2 functions...................................................................................................................... ......... 277 8.3 configuration .................................................................................................................. ...... 278 8.4 registers ...................................................................................................................... ......... 280 8.5 operation...................................................................................................................... ......... 296 8.5.1 interval timer mode (tq0md2 to tq0md0 bi ts = 000) ............................................................ 297 8.5.2 external event count mode (tq0 md2 to tq0md0 bits = 001) ................................................ 306 8.5.3 external trigger pulse output mode (tq0md2 to tq0md0 bits = 010) ....................................315 8.5.4 one-shot pulse output mode (tq0 md2 to tq0md0 bits = 011).............................................. 328 8.5.5 pwm output mode (tq0md2 to tq0md0 bi ts = 100) ............................................................. 337 8.5.6 free-running timer mode (tq0md2 to tq0md0 bi ts = 101).................................................... 348 8.5.7 pulse width measurement mode (tq0 md2 to tq0md0 bits = 110) ........................................ 368 8.5.8 timer output operati ons ........................................................................................................ ...374 8.6 cautions ....................................................................................................................... ......... 375 chapter 9 16-bit interval timer m (tmm) .... ........................................................................ 376 9.1 overview....................................................................................................................... ......... 376 9.2 configuration .................................................................................................................. ...... 377 9.3 register ....................................................................................................................... .......... 378 9.4 operation...................................................................................................................... ......... 379 9.4.1 interval ti mer m ode ............................................................................................................ ......379 9.4.2 cauti ons....................................................................................................................... ............383 chapter 10 watch timer functions ........................ .............................................................. 384 10.1 functions...................................................................................................................... ......... 384 10.2 configuration .................................................................................................................. ...... 385 10.3 control registers.............................................................................................................. .... 387 10.4 operation...................................................................................................................... ......... 391 10.4.1 operation as watch ti mer ....................................................................................................... ..391 10.4.2 operation as in terval timer .................................................................................................... ...392 10.4.3 cauti ons....................................................................................................................... ............393 chapter 11 functions of watchdog timer 2 .. ................................................................. 394 11.1 functions...................................................................................................................... ......... 394 11.2 configuration .................................................................................................................. ...... 395 11.3 registers ...................................................................................................................... ......... 396 11.4 operation...................................................................................................................... ......... 398 chapter 12 real-time output function (rto).. ................................................................. 399 12.1 function....................................................................................................................... .......... 399 12.2 configuration .................................................................................................................. ...... 400
12.3 registers ...................................................................................................................... ......... 402 12.4 operation...................................................................................................................... ......... 404 12.5 usage .......................................................................................................................... ........... 405 12.6 cautions ....................................................................................................................... ......... 405 chapter 13 a/d converter ................................................................................................... ...... 406 13.1 overview....................................................................................................................... ......... 406 13.2 functions...................................................................................................................... ......... 406 13.3 configuration .................................................................................................................. ...... 407 13.4 registers ...................................................................................................................... ......... 410 13.5 operation...................................................................................................................... ......... 421 13.5.1 basic oper ation ................................................................................................................ ........421 13.5.2 conversion operat ion ti ming .................................................................................................... 422 13.5.3 trigger mode................................................................................................................... .........423 13.5.4 operati on m ode ................................................................................................................. ......425 13.5.5 power-fail co mpare mode ........................................................................................................ 429 13.6 cautions ....................................................................................................................... ......... 434 13.7 how to read a/d converter characteristics table. .......................................................... 438 chapter 14 d/a converter ................................................................................................... ...... 442 14.1 functions...................................................................................................................... ......... 442 14.2 configuration .................................................................................................................. ...... 442 14.3 registers ...................................................................................................................... ......... 443 14.4 operation...................................................................................................................... ......... 445 14.4.1 operation in normal mode....................................................................................................... .445 14.4.2 operation in real-t ime output mode ..........................................................................................445 14.4.3 cauti ons....................................................................................................................... ............446 chapter 15 asynchronous serial interface a (uarta) ............................................. 447 15.1 mode switching of uarta and other serial inte rfaces ................................................... 447 15.1.1 csib4 and uarta0 m ode switch ing.......................................................................................447 15.1.2 uarta2 and i 2 c00 mode swit ching .........................................................................................448 15.1.3 uarta1 and i 2 c02 mode swit ching .........................................................................................449 15.2 features....................................................................................................................... .......... 450 15.3 configuration .................................................................................................................. ...... 451 15.4 registers ...................................................................................................................... ......... 453 15.5 interrupt request signals................................................... ................................................. 45 9 15.6 operation...................................................................................................................... ......... 460 15.6.1 data fo rmat .................................................................................................................... ..........460 15.6.2 sbf transmission/rec eption fo rmat ..........................................................................................462 15.6.3 sbf trans missi on............................................................................................................... ......464 15.6.4 sbf rec eptio n .................................................................................................................. ........465 15.6.5 uart trans missi on .............................................................................................................. ....467 15.6.6 continuous transmi ssion proc edure .........................................................................................468 15.6.7 uart rec eptio n ................................................................................................................. ......470 15.6.8 reception errors ............................................................................................................... .......471 15.6.9 parity types and operat ions.................................................................................................... ..473 15.6.10 receive data noi se f ilter ...................................................................................................... .....474 15.7 dedicated baud rate generator ......................................................................................... 475 15.8 cautions ....................................................................................................................... ......... 483
chapter 16 3-wire variable-length serial i/ o (csib).................................................... 484 16.1 mode switching of csib and other serial inte rfaces ....................................................... 484 16.1.1 csib4 and uarta0 m ode switch ing.......................................................................................484 16.1.2 csib0 and i 2 c01 mode swit ching ............................................................................................485 16.2 features....................................................................................................................... .......... 485 16.3 configuration .................................................................................................................. ...... 486 16.4 registers ...................................................................................................................... ......... 488 16.5 interrupt request signals................................................... ................................................. 49 5 16.6 operation...................................................................................................................... ......... 496 16.6.1 single transfer mode (master mode, transmi ssion m ode)........................................................ 496 16.6.2 single transfer mode (master mode, recept ion m ode) ............................................................. 498 16.6.3 single transfer mode (master mode, transmission/rec eption m ode) ........................................ 500 16.6.4 single transfer mode (slave mode, transmi ssion m ode) .......................................................... 502 16.6.5 single transfer mode (slave mode, recept ion m ode)................................................................ 504 16.6.6 single transfer mode (slave mode, transmission/rec eption m ode)........................................... 506 16.6.7 continuous transfer mode (master mode, transmi ssion m ode)................................................ 508 16.6.8 continuous transfer mode (master mode, recept ion m ode) ..................................................... 510 16.6.9 continuous transfer mode (master m ode, transmission/re ception mode) ................................513 16.6.10 continuous transfer mode (slave mode, transmi ssion m ode) .................................................. 517 16.6.11 continuous transfer mode (slave mode, recept ion m ode)........................................................ 519 16.6.12 continuous transfer mode (slave m ode, transmission/re ception mode) ...................................522 16.6.13 reception error ................................................................................................................ ........526 16.6.14 clock ti ming ................................................................................................................... ..........527 16.7 output pins .................................................................................................................... ....... 529 16.8 baud rate generator............................................................................................................ 530 16.8.1 baud rate generatio n ........................................................................................................... ....531 16.9 cautions ....................................................................................................................... ......... 532 chapter 17 i 2 c bus ......................................................................................................................... . 533 17.1 mode switching of i 2 c bus and other serial interfaces ......... .......................................... 533 17.1.1 uarta2 and i 2 c00 mode swit ching .........................................................................................533 17.1.2 csib0 and i 2 c01 mode swit ching ............................................................................................534 17.1.3 uarta1 and i 2 c02 mode swit ching .........................................................................................535 17.2 features....................................................................................................................... .......... 536 17.3 configuration .................................................................................................................. ...... 537 17.4 registers ...................................................................................................................... ......... 541 17.5 i 2 c bus mode functions....................................................................................................... 557 17.5.1 pin confi guratio n .............................................................................................................. ........557 17.6 i 2 c bus definitions and control methods ................ .......................................................... 558 17.6.1 start c onditi on ................................................................................................................ ..........558 17.6.2 addre sses...................................................................................................................... ..........559 17.6.3 transfer direction specific ation ............................................................................................... .560 17.6.4 ack ............................................................................................................................ .............561 17.6.5 stop condi tion ................................................................................................................. .........562 17.6.6 wait state..................................................................................................................... ............563 17.6.7 wait state cance llation me thod ................................................................................................5 65 17.7 i 2 c interrupt request signals (intiicn) .................... .......................................................... 566 17.7.1 master devic e operat ion........................................................................................................ ...566 17.7.2 slave device operation (when receiving sl ave address data (addr ess matc h)) ........................569 17.7.3 slave device operation (when re ceiving extens ion c ode)......................................................... 573
17.7.4 operation without communica tion ............................................................................................577 17.7.5 arbitration loss operation (operation as slave after arbi tration loss) .........................................577 17.7.6 operation when arbitration loss occurs ( no communication after arbitrati on loss) ...................579 17.8 interrupt request signal (intiicn) generation timing and wait control....................... 586 17.9 address match detection method .... .................................................................................. 588 17.10 error detection................................................................................................................ ...... 588 17.11 extension code................................................................................................................. .... 588 17.12 arbitration .................................................................................................................... ......... 589 17.13 wakeup function................................................................................................................ .. 590 17.14 communication reservation............................................................................................... 591 17.14.1 when communication reservation function is enabled (iicfn.iicr svn bit = 0) .......................591 17.14.2 when communication reservation function is disabled (iicfn.ii crsvn bit = 1).......................595 17.15 cautions ....................................................................................................................... ......... 596 17.16 communication operations................................................................................................ . 597 17.16.1 master operation in si ngle master system ................................................................................598 17.16.2 master operation in multimaste r system ..................................................................................599 17.16.3 slave oper ation ................................................................................................................ ........602 17.17 timing of data communication .......................................................................................... 605 chapter 18 dma function (dma controller) ..... .............................................................. 612 18.1 features....................................................................................................................... .......... 612 18.2 configuration .................................................................................................................. ...... 613 18.3 registers ...................................................................................................................... ......... 614 18.4 transfer targets ............................................................... ................................................ .... 621 18.5 transfer modes ................................................................................................................. .... 622 18.6 transfer types ................................................................................................................. ..... 622 18.7 dma channel priorities........................................................................................................ 6 23 18.8 time related to dma transfer ............................................................................................ 623 18.9 dma transfer start f actors................................................................................................. 624 18.10 dma abort factors .............................................................................................................. . 625 18.11 end of dma transfer ............................................................................................................ 625 18.12 operation timing ............................................................................................................... ... 625 18.13 cautions ....................................................................................................................... ......... 630 chapter 19 interrupt/exception processing f unction............................................... 635 19.1 features....................................................................................................................... .......... 635 19.2 non-maskable interrupt s ..................................................................................................... 639 19.2.1 operat ion ...................................................................................................................... ...........641 19.2.2 restore ........................................................................................................................ ............642 19.2.3 np fl ag ........................................................................................................................ .............643 19.3 maskable interrupts............................................................................................................ .. 644 19.3.1 operat ion ...................................................................................................................... ...........644 19.3.2 restore ........................................................................................................................ ............646 19.3.3 priorities of ma skable inte rrupts.............................................................................................. .647 19.3.4 interrupt control r egister ( xxicn) ............................................................................................. .651 19.3.5 interrupt mask registers 0 to 3 (imr0 to imr3 ) ........................................................................653 19.3.6 in-service priority register (ispr) ............................................................................................ .655 19.3.7 id flag ........................................................................................................................ ..............656 19.3.8 watchdog timer mode regi ster 2 (w dtm2) .............................................................................656 19.4 software exception ............................................................................................................. . 657
19.4.1 operat ion ...................................................................................................................... ...........657 19.4.2 restore ........................................................................................................................ ............658 19.4.3 ep fl ag ........................................................................................................................ .............659 19.5 exception trap................................................................................................................. ..... 660 19.5.1 illegal opcode definit ion...................................................................................................... ......660 19.5.2 debug tr ap ..................................................................................................................... ..........662 19.6 external interrupt request input pins (nmi a nd intp0 to intp7) ................................... 664 19.6.1 noise elim inatio n.............................................................................................................. ........664 19.6.2 edge detec tion ................................................................................................................. ........664 19.7 interrupt acknowledge time of cpu .................................................................................. 669 19.8 periods in which interrupts are not acknowledge d by cpu .......................................... 670 19.9 cautions ....................................................................................................................... ......... 670 chapter 20 key interrupt function ....................... .............................................................. 671 20.1 function....................................................................................................................... .......... 671 20.2 register ....................................................................................................................... .......... 672 20.3 cautions ....................................................................................................................... ......... 672 chapter 21 standby functi on ................................................................................................ .. 673 21.1 overview....................................................................................................................... ......... 673 21.2 registers ...................................................................................................................... ......... 675 21.3 halt mode...................................................................................................................... ...... 678 21.3.1 setting and operat ion st atus ................................................................................................... .678 21.3.2 releasing ha lt m ode............................................................................................................ .678 21.4 idle1 mode ..................................................................................................................... ...... 680 21.4.1 setting and operat ion st atus ................................................................................................... .680 21.4.2 releasing id le1 m ode ........................................................................................................... .680 21.5 idle2 mode ..................................................................................................................... ...... 682 21.5.1 setting and operat ion st atus ................................................................................................... .682 21.5.2 releasing id le2 m ode ........................................................................................................... .682 21.5.3 securing setup time when releasing id le2 m ode ................................................................... 684 21.6 stop mode...................................................................................................................... ...... 685 21.6.1 setting and operat ion st atus ................................................................................................... .685 21.6.2 releasing st op m ode ............................................................................................................ 685 21.6.3 securing oscillation stabilization ti me when releasi ng stop mode .........................................688 21.7 subclock operation mode ................................................................................................... 689 21.7.1 setting and operat ion st atus ................................................................................................... .689 21.7.2 releasing subclock operation mode ........................................................................................689 21.8 sub-idle mode .................................................................................................................. ... 691 21.8.1 setting and operat ion st atus ................................................................................................... .691 21.8.2 releasing sub- idle m ode .......................................................................................................6 91 chapter 22 reset functions ................................................................................................. .... 693 22.1 overview....................................................................................................................... ......... 693 22.2 registers to check reset source............................. .......................................................... 694 22.3 operation...................................................................................................................... ......... 695 22.3.1 reset operation vi a reset pin ...............................................................................................695 22.3.2 reset operation by watchdog time r 2.......................................................................................697 22.3.3 reset operation by lo w-voltage det ector ..................................................................................699 22.3.4 operation after reset re lease .................................................................................................. .700
22.3.5 reset function operation flow.................................................................................................. .701 chapter 23 clock monito r ................................................................................................... ..... 702 23.1 functions...................................................................................................................... ......... 702 23.2 configuration .................................................................................................................. ...... 702 23.3 register ....................................................................................................................... .......... 703 23.4 operation...................................................................................................................... ......... 704 chapter 24 low-voltage detector (lvi) ............ ................................................................. 707 24.1 functions...................................................................................................................... ......... 707 24.2 configuration .................................................................................................................. ...... 707 24.3 registers ...................................................................................................................... ......... 708 24.4 operation...................................................................................................................... ......... 710 24.4.1 to use for inter nal rese t signal............................................................................................... ..710 24.4.2 to use for interr upt........................................................................................................... ........711 24.5 ram retention voltage detection operation ......... ........................................................... 712 24.6 emulation function ............................................................................................................. . 713 chapter 25 crc function .................................................................................................... ........ 714 25.1 functions...................................................................................................................... ......... 714 25.2 configuration .................................................................................................................. ...... 714 25.3 registers ...................................................................................................................... ......... 715 25.4 operation...................................................................................................................... ......... 716 25.5 usage method ................................................................................................................... .... 717 chapter 26 regulator ........................................................................................................ ......... 719 26.1 overview....................................................................................................................... ......... 719 26.2 operation...................................................................................................................... ......... 720 chapter 27 flash memory .................................................................................................... ...... 721 27.1 features....................................................................................................................... .......... 721 27.2 memory configuratio n ......................................................................................................... 72 2 27.3 functional outline ............................................................................................................. ... 724 27.4 rewriting by dedicated flash programmer............. .......................................................... 727 27.4.1 programming env ironment .......................................................................................................7 27 27.4.2 communicati on m ode ............................................................................................................. .728 27.4.3 flash memory cont rol ........................................................................................................... ...734 27.4.4 selection of comm unication mode ...........................................................................................735 27.4.5 communication commands ......................................................................................................736 27.4.6 pin connec tion ................................................................................................................. ........737 27.5 rewriting by self programming . ......................................................................................... 741 27.5.1 overvi ew....................................................................................................................... ...........741 27.5.2 featur es....................................................................................................................... ............742 27.5.3 standard self progr amming fl ow ..............................................................................................743 27.5.4 flash f uncti ons................................................................................................................ .........744 27.5.5 pin proc essi ng ................................................................................................................. ........744 27.5.6 internal res ources used ........................................................................................................ ...745 chapter 28 on-chip debug function ....................... .............................................................. 746 28.1 debugging with dcu ............................................................................................................ 7 47
28.1.1 connection circui t exam ple ..................................................................................................... .747 28.1.2 interface signal s.............................................................................................................. .........747 28.1.3 maskable f uncti ons ............................................................................................................. .....749 28.1.4 regist er ....................................................................................................................... ............749 28.1.5 operat ion ...................................................................................................................... ...........751 28.1.6 cauti ons....................................................................................................................... ............751 28.2 debugging without using dcu.................................... ....................................................... 752 28.2.1 circuit connecti on exam ples .................................................................................................... 752 28.2.2 maskable f uncti ons ............................................................................................................. .....753 28.2.3 securement of us er resour ces .................................................................................................75 4 28.2.4 cauti ons....................................................................................................................... ............760 28.3 rom security function........................................................................................................ 76 2 28.3.1 security id .................................................................................................................... ...........762 28.3.2 setti ng........................................................................................................................ ..............763 chapter 29 electrical specifications ................... .............................................................. 765 chapter 30 package drawing ................................................................................................. . 800 chapter 31 recommended soldering conditions. .......................................................... 801 appendix a development tools............................................................................................... 802 a.1 software package ............................................................................................................... .. 804 a.2 language processing software .......................................................................................... 804 a.3 control software............................................................................................................... .... 804 a.4 debugging tools (hardware) .............................................................................................. 805 a.4.1 when using iecu be qb-v850 essx2 .................................................................................... 805 a.4.2 when using minicu be qb-v850m ini ....................................................................................807 a.4.3 when using minicu be2 qb-mi ni2.........................................................................................808 a.5 debugging tools (software)................................................................................................ 809 a.6 embedded software ............................................................................................................. 8 10 a.7 flash memory writing tools ............................................................................................... 811 appendix b major differences between v850es/jg3 and v850es/jg2.................... 812 appendix c register index .................................................................................................. ....... 814 appendix d instruction set list ........................................................................................... .. 824 d.1 conventions .................................................................................................................... ...... 824 d.2 instruction set (in alphabetical order) ................... ........................................................... 827 appendix e list of cautions ............................................................................................... ...... 834 appendix f revision history................................................................................................ ...... 870 f.1 major revisions in this edition .......................................................................................... 870 f.2 revision history of previous editions ..................... .......................................................... 870
r01uh0015ej0300 rev.3.00 page 1 of 870 sep 30, 2010 r01uh0015ej0300 rev.3.00 sep 30, 2010 v850es/jg3 renesas mcu chapter 1 introduction the v850es/jg3 is one of the products in the renesas electronics v850 single-chip microcontrollers designed for low- power operation for real-time control applications. 1.1 general the v850es/jg3 is a 32-bit single-chip microcontroller that includes the v850es cpu core and peripheral functions such as rom/ram, a timer/counter, serial interfaces, an a/d converter, and a d/a converter. in addition to high real-time response characteristics and 1-clock-pitch basic instructions, the v850es/jg3 features multiply instructions, saturated operation instructions, bit m anipulation instructions, etc., realized by a hardware multiplier , as optimum instructions for digital se rvo control applications. mo reover, as a real-time c ontrol system, the v850es/jg3 enables an extremely high cost-performance for applications t hat require low power consumption, such as home audio, printers, and digital home electronics. table 1-1 lists the products of the v850es/jg3.
v850es/jg3 chapter 1 introduction r01uh0015ej0300 rev.3.00 page 2 of 870 sep 30, 2010 table 1-1. v850es/jg3 product list part number pd70f3739 pd70f3740 pd70f3741 pd70f3742 flash memory 384 kb 512 kb 768 kb 1024 kb internal memory ram 32 kb 40 kb 60 kb 60 kb logical space 64 mb memory space external memory area 16 mb external bus interface address bus: 22 bits data bus: 8/16 bits multiplex bus mode/separate bus mode general-purpose register 32 bits 32 registers main clock (oscillation frequency) ceramic/crystal (in pll mode: f x = 2.5 to 5 mhz (multiplied by 4) or f x = 2.5 to 4 mhz (multiplied by 8), in clock through mode: f x = 2.5 to 10 mhz) subclock (oscillation frequency) crystal (f xt = 32.768 khz) internal oscillator f r = 220 khz (typ.) minimum instruction executi on time 31.25 ns (main clock (f xx ) = 32 mhz) dsp function 32 32 = 64: 125 to 156.25 ns (at 32 mhz) 32 32 + 32 = 32: 187.5 ns (at 32 mhz) 16 16 = 32: 31.25 to 62.5 ns (at 32 mhz) 16 16 + 32 = 32: 93.75 ns (at 32 mhz) i/o port i/o: 84 (5 v tolerant/n-ch open-drain output selectable: 40) timer 16-bit timer/event counter p: 6 channels 16-bit timer/event counter q: 1 channel 16-bit interval timer m: 1 channel watch timer: 1 channel watchdog timer : 1 channel real-time output port 6 bits 1 channel a/d converter 10-bit resolution 12 channels d/a converter 8-bit resolution 2 channels serial interface uart/csi: 1 channel uart/i 2 c bus: 2 channels csi: 3 channels csi/i 2 c bus: 1 channel dma controller 4 channels (transfer target: on-chip peripheral i/o, internal ram, external memory) interrupt source external: 9 (9) note , internal: 48 power save function halt/idle1/idle2/stop/subclock/sub-idle mode reset reset pin input, watchdog timer 2 (wdt2), clock monitor (clm), low-voltage detector (lvi) dcu provided (run/break) operating power supply voltage 2.85 to 3.6 v operating ambient temperature ? 40 to +85 c package 100-pin plastic lqfp (fine pitch) (14 14 mm) note the figure in parentheses indicates the number of ex ternal interrupts that can release the stop mode.
v850es/jg3 chapter 1 introduction r01uh0015ej0300 rev.3.00 page 3 of 870 sep 30, 2010 1.2 features minimum instruction execution time: 31.25 ns (operating with main clock (f xx ) of 32 mhz) general-purpose registers: 32 bits 32 registers cpu features: signed multiplication (16 16 32): 1 to 2 clocks signed multiplication (32 32 64): 1 to 5 clocks saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format memory space: 64 mb of linear address space (for programs and data) external expansion: up to 16 mb (including 1 mb used as internal rom/ram) ? internal memory: ram: 32 kb/40 kb/60 kb (see table 1-1 ) flash memory: 384 kb/512 kb/768 kb/1024 kb (see table 1-1 ) ? external bus interface: separate bus/multiplexed bus output selectable 8-/16-bit data bus sizing function wait function ? programmable wait function ? external wait function idle state function bus hold function interrupts and exceptions: non-maskable interrupts: 2 sources maskable interrupts: 55 sources software exceptions: 32 sources exception trap: 2 sources i/o lines: i/o ports: 84 timer function: 16-bit interv al timer m (tmm): 1 channel 16-bit timer/event counter p (tmp): 6 channels 16-bit timer/event counter q (tmq): 1 channel watch timer: 1 channel watchdog timer: 1 channel real-time output port: 6 bits 1 channel serial interface: asynchronous serial interface a (uarta) 3-wire variable-length serial interface b (csib) i 2 c bus interface (i 2 c) uarta/csib: 1 channel uarta/i 2 c: 2 channels csib/i 2 c: 1 channel csib: 3 channels a/d converter: 10-bit resolution: 12 channels d/a converter: 8-bit resolution: 2 channels dma controller: 4 channels crc function: 16-bit error detection code for data in 8-bit units can be generated dcu (debug control unit): jtag interface clock generator: during main clock or subclock operation 7-level cpu clock (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable internal oscillation clock: 220 khz (typ.) power-save functions: halt/idle1/idle2/stop/subclock/sub-idle mode package: 100-pin plastic lqfp (fine pitch) (14 14)
v850es/jg3 chapter 1 introduction r01uh0015ej0300 rev.3.00 page 4 of 870 sep 30, 2010 1.3 application fields home audio, printers, digital home electronics, other consumer devices 1.4 ordering information part number package internal flash memory pd70f3739gc-ueu-ax pd70f3740gc-ueu-ax pd70f3741gc-ueu-ax pd70f3742gc-ueu-ax 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 384 kb 512 kb 768 kb 1024 kb remark the v850es/jg3 microcontro llers are lead-free products.
v850es/jg3 chapter 1 introduction r01uh0015ej0300 rev.3.00 page 5 of 870 sep 30, 2010 1.5 pin configuration (top view) 100-pin plastic lqfp (fine pitch) (14 14) pd70f3739gc-ueu-ax pd70f3740gc-ueu-ax pd70f3741gc-ueu-ax pd70f3742gc-ueu-ax 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p31/rxda0/intp7/sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01 p34/tip10/top10 p35/tip11/top11 p36 p37 ev ss ev dd p38/txda2/sda00 p39/rxda2/scl00 p50/tiq01/kr0/toq01/rtp00 p51/tiq02/kr1/toq02/rtp01 p52/tiq03/kr2/toq03/rtp02/ddi p53/sib2/kr3/tiq00/toq00/rtp03/ddo p54/sob2/kr4/rtp04/dck p55/sckb2/kr5/rtp05/dms p90/a0/kr6/txda1/sda02 p91/a1/kr7/rxda1/scl02 p92/a2/tip41/top41 p93/a3/tip40/top40 p94/a4/tip31/top31 p95/a5/tip30/top30 p96/a6/tip21/top21 p97/a7/sib1/tip20/top20 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 ev dd ev ss pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pdh3/a19 pdh2/a18 p915/a15/intp6/tip50/top50 p914/a14/intp5/tip51/top51 p913/a13/intp4 p912/a12/sckb3 p911/a11/sob3 p910/a10/sib3 p99/a9/sckb1 p98/a8/sob1 av ref0 av ss p10/ano0 p11/ano1 av ref1 pdh4/a20 pdh5/a21 flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst p06/intp3 p40/sib0/sda01 p41/sob0/scl01 p42/sckb0 p30/txda0/sob4 notes 1. connect these pins to v ss in the normal mode. 2. connect the regc pin to v ss via a 4.7 f (recommended value) capacitor.
v850es/jg3 chapter 1 introduction r01uh0015ej0300 rev.3.00 page 6 of 870 sep 30, 2010 pin names a0 to a21: ad0 to ad15: adtrg: ani0 to ani11: ano0, ano1: ascka0: astb: av ref0 , av ref1 : av ss : clkout: dck: ddi: ddo: dms: drst: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: intp0 to intp7: kr0 to kr7: nmi: p02 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p70 to p711: p90 to p915: pcm0 to pcm3: pct0, pct1, pct4, pct6: address bus address/data bus a/d trigger input analog input analog output asynchronous serial clock address strobe analog reference voltage analog v ss clock output debug clock debug data input debug data output debug mode select debug reset power supply for external pin ground for external pin flash programming mode hold acknowledge hold request external interrupt input key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 7 port 9 port cm port ct pdh0 to pdh5: pdl0 to pdl15: rd: regc: reset: rtp00 to rtp05: rxda0 to rxda2: sckb0 to sckb4: scl00 to scl02: sda00 to sda02: sib0 to sib4: sob0 to sob4: tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tiq00 to tiq03: top00, top01, top10, top11, top20, top21, top30, top31, top40, top41, top50, top51, toq00 to toq03: txda0 to txda2: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port dh port dl read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer input timer output transmit data power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock
v850es/jg3 chapter 1 introduction r01uh0015ej0300 rev.3.00 page 7 of 870 sep 30, 2010 1.6 function block configuration 1.6.1 internal block diagram nmi toq00 to toq03 tiq00 to tiq03 rtp00 to rtp05 sob0/scl01 sib0/sda01 sckb0 intp0 to intp7 intc 16-bit timer/ counter q: 1 ch top00 to top50, top01 to top51 tip00 to tip50, tip01 to tip51 16-bit timer/ counter p: 6 ch kr0 to kr7 rto csib1 dmac watchdog timer 2 watch timer key return function note 1 note 2 ram rom pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 a0 to a21 ad0 to ad15 ports cg regulator pll clm internal oscillator pcm0 to pcm3 pct0, pct1, pct4, pct6 pdh0 to pdh5 pdl0 to pdl15 p90 to p915 p70 to p711 p50 to p55 p40 to p42 p30 to p39 p10, p11 p02 to p06 av ref1 ano0, ano1 ani0 to ani11 av ss av ref0 adtrg clkout xt1 xt2 x1 x2 v dd v ss regc flmd0 flmd1 ev dd ev ss instruction queue bcu sob1 sib1 sckb1 csib2 sob2 sib2 sckb2 csib3 sob3 sib3 sckb3 txda0/sob4 rxda0/sib4 ascka0/sckb4 txda2/sda00 rxda2/scl00 csib0 i 2 c01 16-bit interval timer m: 1 ch uarta0 csib4 uarta2 i 2 c00 txda1/sda02 rxda1/scl02 uarta1 i 2 c02 dcu drst dms ddi dck ddo a/d converter d/a converter reset lvi notes 1. 384/512/768/1024 kb (flash memory) (see table 1-1 ) 2. 32/40/60 kb (see table 1-1 )
v850es/jg3 chapter 1 introduction r01uh0015ej0300 rev.3.00 page 8 of 870 sep 30, 2010 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable single-cl ock execution of address calc ulations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetc hes the instruction code. the prefetch ed instruction code is stored in an instruction queue. (3) rom this is a 1024/768/512/384 kb flash memory m apped to addresses 0000000h to 00fffffh/0000000h to 00bffffh/0000000h to 007ffffh/0000000h to 005ffffh. it can be accessed from the cpu in one clock during instruction fetch. (4) ram this is a 60/48/32 kb ram mapped to addresses 3ff0 000h to 3ffefffh/3ff5000h to 3ffefffh/3ff7000h. it can be accessed from the cpu in one clock during data access. (5) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp7) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiple servicing control can be performed. (6) clock generator (cg) a main clock oscillator that generates the main clock oscillation frequency (f x ) and a subclock oscillator that generates the subclock oscillation frequency (f xt ) are available. as the main clock frequency (f xx ), f x is used as is in the clock-through mode and is multiplied by four or eight in the pll mode. the cpu clock frequency (f cpu ) can be selected from seven types: f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt . (7) internal oscillator an internal oscillator is provided on chip. the oscill ation frequency is 220 khz (typ.). an internal oscillator supplies the clock for watchdog timer 2 and timer m. (8) timer/counter six-channel 16-bit timer/event count er p (tmp), one-channel 16-bit timer/ event counter q (tmq), and one-channel 16-bit interval timer m (tmm) are provided on chip. (9) watch timer this timer counts the reference time period (0.5 s) for counting the clock (t he 32.768 khz from the subclock or the 32.768 khz f brg from prescaler 3). the watch timer can also be used as an interval timer for the main clock.
v850es/jg3 chapter 1 introduction r01uh0015ej0300 rev.3.00 page 9 of 870 sep 30, 2010 (10) watchdog timer 2 a watchdog timer is provided on chip to detect inadv ertent program loops, system abnormalities, etc. the internal oscillation clock, the main clock, or t he subclock can be selected as the source clock. watchdog timer 2 generates a non-maskable interrupt request signal (intwdt2) or a system reset signal (wdt2res) after an overflow occurs. (11) serial interface the v850es/jg3 includes three kinds of serial interfac es: asynchronous serial interface a (uarta), 3-wire variable-length serial interface b (csib), and an i 2 c bus interface (i 2 c). in the case of uarta, data is transferred via the txda0 to txda2 pins and rxda0 to rxda2 pins. in the case of csib, data is transferred via the sob0 to sob4 pins, sib0 to sib4 pins, and sckb0 to sckb4 pins. in the case of i 2 c, data is transferred via the sda00 to sda02 and scl00 to scl02 pins. (12) a/d converter this 10-bit a/d converter includes 12 analog input pins. conversion is performed using the successive approximation method. (13) d/a converter a two-channel, 8-bit-resolution d/a converter that uses the r-2r ladder method is provided on chip. (14) dma controller a 4-channel dma controller is provided on chip. this controller transfers data between the internal ram and on- chip peripheral i/o devi ces in response to interrupt requests sent by on-chip peripheral i/o. (15) key interrupt function a key interrupt request signal (intkr) can be generated by i nputting a falling edge to key input pins (8 channels). (16) real-time output function the real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer compare register match signal. (17) crc function a crc operation circuit that generates 16-bit crc (cyclic redundancy check) codes for data in 8-bit units is provided. (18) dcu (debug control unit) an on-chip debug function that uses the jtag (joint test action group) communication s pecifications is provided. switching between the normal port function and on-chip de bugging function is done with the control pin input level and the ocdm register.
v850es/jg3 chapter 1 introduction r01uh0015ej0300 rev.3.00 page 10 of 870 sep 30, 2010 (19) ports the general-purpose port functions and cont rol pin functions are listed below. port i/o alternate function p0 5-bit i/o nmi, external interrupt, a/d converter trigger, debug reset p1 2-bit i/o d/a converter analog output p3 10-bit i/o external interrupt, serial interface, timer i/o p4 3-bit i/o serial interface p5 6-bit i/o timer i/o, real-time output, key interrupt input, serial interface, debug i/o p7 12-bit i/o a/d converter analog input p9 16-bit i/o external address bus, serial interface, key interrupt input, timer i/o, external interrupt pcm 4-bit i/o external control signal pct 4-bit i/o external control signal pdh 6-bit i/o external address bus pdl 16-bit i/o external address/data bus
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 11 of 870 sep 30, 2010 chapter 2 pin functions 2.1 list of pin functions the names and functions of the pins in the v850es/jg3 are described below. there are three types of pin i/o buffer power supplies: av ref0 , av ref1 , and ev dd . the relationship between these power supplies and the pins is described below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref0 port 7 av ref1 port 1 ev dd reset, ports 0, 3 to 5, 9, cm, ct, dh, dl (1) port pins (1/3) pin name pin no. i/o function alternate function p02 17 nmi p03 18 intp0/adtrg p04 19 intp1 p05 note 20 intp2/drst p06 21 i/o port 0 5-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. intp3 p10 3 ano0 p11 4 i/o port 1 2-bit i/o port input/output can be specified in 1-bit units. ano1 p30 25 txda0/sob4 p31 26 rxda0/intp7/sib4 p32 27 ascka0/sckb4/tip00/top00 p33 28 tip01/top01 p34 29 tip10/top10 p35 30 tip11/top11 p36 31 ? p37 32 ? p38 35 txda2/sda00 p39 36 i/o port 3 10-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. rxda2/scl00 note incorporates a pull-down resistor. it can be di sconnected by clearing the ocdm.ocdm0 bit to 0.
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 12 of 870 sep 30, 2010 (2/3) pin name pin no. i/o function alternate function p40 22 sib0/sda01 p41 23 sob0/scl01 p42 24 i/o port 4 3-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. sckb0 p50 37 tiq01/kr0/toq01/rtp00 p51 38 tiq02/kr1/toq02/rtp01 p52 39 tiq03/kr2/toq03/rtp02/ ddi p53 40 sib2/kr3/tiq00/toq00/rtp03/ddo p54 41 sob2/kr4/rtp04/dck p55 42 i/o port 5 6-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. sckb2/kr5/rtp05/dms p70 100 ani0 p71 99 ani1 p72 98 ani2 p73 97 ani3 p74 96 ani4 p75 95 ani5 p76 94 ani6 p77 93 ani7 p78 92 ani8 p79 91 ani9 p710 90 ani10 p711 89 i/o port 7 12-bit i/o port input/output can be specified in 1-bit units. ani11 p90 43 a0/kr6/txda1/sda02 p91 44 a1/kr7/rxda1/scl02 p92 45 a2/tip41/top41 p93 46 a3/tip40/top40 p94 47 a4/tip31/top31 p95 48 a5/tip30/top30 p96 49 a6/tip21/top21 p97 50 a7/sib1/tip20/top20 p98 51 a8/sob1 p99 52 a9/sckb1 p910 53 a10/sib3 p911 54 a11/sob3 p912 55 a12/sckb3 p913 56 a13/intp4 p914 57 a14/intp5/tip51/top51 p915 58 i/o port 9 16-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. a15/intp6/tip50/top50
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 13 of 870 sep 30, 2010 (3/3) pin name pin no. i/o function alternate function pcm0 61 wait pcm1 62 clkout pcm2 63 hldak pcm3 64 i/o port cm 4-bit i/o port input/output can be specified in 1-bit units. hldrq pct0 65 wr0 pct1 66 wr1 pct4 67 rd pct6 68 i/o port ct 4-bit i/o port input/output can be specified in 1-bit units. astb pdh0 87 a16 pdh1 88 a17 pdh2 59 a18 pdh3 60 a19 pdh4 6 a20 pdh5 7 i/o port dh 6-bit i/o port input/output can be specified in 1-bit units. a21 pdl0 71 ad0 pdl1 72 ad1 pdl2 73 ad2 pdl3 74 ad3 pdl4 75 ad4 pdl5 76 ad5/flmd1 pdl6 77 ad6 pdl7 78 ad7 pdl8 79 ad8 pdl9 80 ad9 pdl10 81 ad10 pdl11 82 ad11 pdl12 83 ad12 pdl13 84 ad13 pdl14 85 ad14 pdl15 86 i/o port dl 16-bit i/o port input/output can be specified in 1-bit units. ad15
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 14 of 870 sep 30, 2010 (2) non-port pins (1/5) pin name pin no. i/o function alternate function a0 43 p90/kr6/txda1/sda02 a1 44 p91/kr7/rxda1/scl02 a2 45 p92/tip41/top41 a3 46 p93/tip40/top40 a4 47 p94/tip31/top31 a5 48 p95/tip30/top30 a6 49 p96/tip21/top21 a7 50 p97/sib1/tip20/top20 a8 51 p98/sob1 a9 52 p99/sckb1 a10 53 p910/sib3 a11 54 p911/sob3 a12 55 p912/sckb3 a13 56 p913/intp4 a14 57 p914/intp5/tip51/top51 a15 58 output address bus for external memory (when using separate bus) n-ch open-drain output selectable. 5 v tolerant. p915/intp6/tip50/top50 a16 87 pdh0 a17 88 pdh1 a18 59 pdh2 a19 60 pdh3 a20 6 pdh4 a21 7 output address bus for external memory pdh5 ad0 71 pdl0 ad1 72 pdl1 ad2 73 pdl2 ad3 74 pdl3 ad4 75 pdl4 ad5 76 pdl5/flmd1 ad6 77 pdl6 ad7 78 pdl7 ad8 79 pdl8 ad9 80 pdl9 ad10 81 pdl10 ad11 82 pdl11 ad12 83 pdl12 ad13 84 pdl13 ad14 85 pdl14 ad15 86 i/o address bus/data bus for external memory pdl15
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 15 of 870 sep 30, 2010 (2/5) pin name pin no. i/o function alternate function adtrg 18 input a/d converter external trigger input. 5 v tolerant. p03/intp0 ani0 100 p70 ani1 99 p71 ani2 98 p72 ani3 97 p73 ani4 96 p74 ani5 95 p75 ani6 94 p76 ani7 93 p77 ani8 92 p78 ani9 91 p79 ani10 90 p710 ani11 89 input analog voltage input for a/d converter p711 ano0 3 p10 ano1 4 output analog voltage output for d/a converter p11 ascka0 27 input uarta0 baud rate clock input. 5 v tolerant. p32/sckb4/tip00/top00 astb 68 output address strobe signal output for external memory pct6 av ref0 1 reference voltage input for a/d converter/positive power supply for port 7 ? av ref1 5 ? reference voltage input for d/a converter/positive power supply for port 1 ? av ss 2 ? ground potential for a/d and d/a converters (same potential as v ss ) ? clkout 62 output internal system clock output pcm1 dck 41 input debug clock input. 5 v tolerant. p54/sob2/kr4/rtp04 ddi 39 input debug data input. 5 v tolerant. p52/tiq03/kr2/toq03/rtp02 ddo note 40 output debug data output. n-ch open-drain output selectable. 5 v tolerant. p53/sib2/kr3/tiq00/toq00/ rtp03 dms 42 input debug mode select input. 5 v tolerant. p55/sckb2/kr5/rtp05 drst 20 input debug reset input. 5 v tolerant. p05/intp2 ev dd 34, 70 ? positive power supply for external (same potential as v dd ) ? ev ss 33, 69 ? ground potential for external (same potential as v ss ) ? flmd0 8 ? flmd1 76 input flash memory programming mode setting pin pdl5/ad5 hldak 63 output bus hold acknowledge output pcm2 hldrq 64 input bus hold request input pcm3 note in the on-chip debug mode, high-level output is forcibly set.
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 16 of 870 sep 30, 2010 (3/5) pin name pin no. i/o function alternate function intp0 18 p03/adtrg intp1 19 p04 intp2 20 p05/drst intp3 21 p06 intp4 56 p913/a13 intp5 57 p914/a14/tip51/top51 intp6 58 p915/a15/tip50/top50 intp7 26 input external interrupt request input (maskable, analog noise elimination). analog noise elimination or digital noise elimination selectable for intp3 pin. 5 v tolerant. p31/rxda0/sib4 kr0 note 1 37 p50/tiq01/toq01/rtp00 kr1 note 1 38 p51/tiq02/toq02/rtp01 kr2 note 1 39 p52/tiq03/toq03/ rtp02/ddi kr3 note 1 40 p53/sib2/tiq00/toq00/ rtp03/ddo kr4 note 1 41 p54/sob2/rtp04/dck kr5 note 1 42 p55/sckb2/rtp05/dms kr6 note 1 43 p90/a0/txda1/sda02 kr7 note 1 44 input key interrupt input (on-chip analog noise eliminator). 5 v tolerant. p91/a1/rxda1/scl02 nmi note 2 17 input external interrupt input (non-maskable, analog noise elimination). 5 v tolerant. p02 rd 67 output read strobe signal output for external memory pct4 regc 10 ? connection of regulator output stabilization capacitance (4.7 f (recommended value)) ? reset 14 input system reset input ? rtp00 37 p50/tiq01/kr0/toq01 rtp01 38 p51/tiq02/kr1/toq02 rtp02 39 p52/tiq03/kr2/toq03/ddi rtp03 40 p53/sib2/kr3/tiq00/toq00/ ddo rtp04 41 p54/sob2/kr4/dck rtp05 42 output real-time output port. n-ch open-drain output selectable. 5 v tolerant. p55/sckb2/kr5/dms rxda0 26 p31/intp7/sib4 rxda1 44 p91/a1/kr7/scl02 rxda2 36 input serial receive data input (uarta0 to uarta2) 5 v tolerant. p39/scl00 sckb0 24 p42 sckb1 52 p99/a9 sckb2 42 p55/kr5/rtp05/dms sckb3 55 p912/a12 sckb4 27 i/o serial clock i/o (csib0 to csib4) n-ch open-drain output selectable. 5 v tolerant. p32/ascka0/tip00/top00 notes 1. pull this pin up externally. 2. the nmi pin alternately functions as the p02 pin. it functi ons as the p02 pin after reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1. the initial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge using intf0 and intr0 registers.
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 17 of 870 sep 30, 2010 (4/5) pin name pin no. i/o function alternate function scl00 36 p39/rxda2 scl01 23 p41/sob0 scl02 44 i/o serial clock i/o (i 2 c00 to i 2 c02) n-ch open-drain output selectable. 5 v tolerant. p91/a1/kr7/rxda1 sda00 35 p38/txda2 sda01 22 p40/sib0 sda02 43 i/o serial transmit/receive data i/o (i 2 c00 to i 2 c02) n-ch open-drain output selectable. 5 v tolerant. p90/a0/kr6/txda1 sib0 22 p40/sda01 sib1 50 p97/a7/tip20/top20 sib2 40 p53/kr3/tiq00/toq00/ rtp03/ddo sib3 53 p910/a10 sib4 26 input serial receive data input (csib0 to csib4) 5 v tolerant. p31/rxda0/intp7 sob0 23 p41/scl01 sob1 51 p98/a8 sob2 41 p54/kr4/rtp04/dck sob3 54 p911/a11 sob4 25 output serial transmit data output (csib0 to csib4) n-ch open-drain output selectable. 5 v tolerant. p30/txda0 tip00 27 external event count input/capture trigger input/external trigger input (tmp0). 5 v tolerant. p32/ascka0/sckb4/top00 tip01 28 capture trigger input (tmp0). 5 v tolerant. p33/top01 tip10 29 external event count input/capture trigger input/external trigger input (tmp1). 5 v tolerant. p34/top10 tip11 30 capture trigger input (tmp1). 5 v tolerant. p35/top11 tip20 50 external event count input/capture trigger input/external trigger input (tmp2). 5 v tolerant. p97/a7/sib1/top20 tip21 49 capture trigger input (tmp2). 5 v tolerant. p96/a6/top21 tip30 48 external event count input/capture trigger input/external trigger input (tmp3). 5 v tolerant. p95/a5/top30 tip31 47 capture trigger input (tmp3). 5 v tolerant. p94/a4/top31 tip40 46 external event count input/capture trigger input/external trigger input (tmp4). 5 v tolerant. p93/a3/top40 tip41 45 capture trigger input (tmp4). 5 v tolerant. p92/a2/top41 tip50 58 external event count input/capture trigger input/external trigger input (tmp5). 5 v tolerant. p915/a15/intp6/top50 tip51 57 input capture trigger input (tmp5). 5 v tolerant. p914/a14/intp5/top51 tiq00 40 external event count input/capture trigger input/external trigger input (tmq0). 5 v tolerant. p53/sib2/kr3/toq00/rtp03 /ddo tiq01 37 p50/kr0/toq01/rtp00 tiq02 38 p51/kr1/toq02/rtp01 tiq03 39 input capture trigger input (tmq0). 5 v tolerant. p52/kr2/toq03/rtp02/ddi
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 18 of 870 sep 30, 2010 (5/5) pin name pin no. i/o function alternate function top00 27 p32/ascka0/sckb4/tip00 top01 28 timer output (tmp0) n-ch open-drain output selectable. 5 v tolerant. p33/tip01 top10 29 p34/tip10 top11 30 timer output (tmp1) n-ch open-drain output selectable. 5 v tolerant. p35/tip11 top20 50 p97/a7/sib1/tip20 top21 49 timer output (tmp2) n-ch open-drain output selectable. 5 v tolerant. p96/a6/tip21 top30 48 p95/a5/tip30 top31 47 timer output (tmp3) n-ch open-drain output selectable. 5 v tolerant. p94/a4/tip31 top40 46 p93/a3/tip40 top41 45 timer output (tmp4) n-ch open-drain output selectable. 5 v tolerant. p92/a2/tip41 top50 58 p915/a15/intp6/tip50 top51 57 output timer output (tmp5) n-ch open-drain output selectable. 5 v tolerant. p914/a14/intp5/tip51 toq00 40 p53/sib2/kr3/tiq00/rtp03/ ddo toq01 37 p50/tiq01/kr0/rtp00 toq02 38 p51/tiq02/kr1/rtp01 toq03 39 output timer output (tmq0) n-ch open-drain output selectable. 5 v tolerant. p52/tiq03/kr2/rtp02/ddi txda0 25 p30/sob4 txda1 43 p90/a0/kr6/sda02 txda2 35 output serial transmit data output (uarta0 to uarta2) n-ch open-drain output selectable. 5 v tolerant. p38/sda00 v dd 9 ? positive power supply pin for internal ? v ss 11 ? ground potential for internal ? wait 61 input external wait input pcm0 wr0 65 write strobe for external memory (lower 8 bits) pct0 wr1 66 output write strove for external memory (higher 8 bits) pct1 x1 12 input ? x2 13 ? connection of resonator for main clock ? xt1 15 input ? xt2 16 ? connection of resonator for subclock ?
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 19 of 870 sep 30, 2010 2.2 pin states the operation states of pins in the various modes are described below. table 2-2. pin operation states in various modes pin name when power is turned on note 1 during reset (except when power is turned on) halt mode note 2 idle1, idle2, sub-idle mode note 2 stop mode note 2 idle state note 3 bus hold p05/drst pulled down pulled down note 4 held held held held held p10/ano0, p11/ano1 hi-z hi-z held held hi-z held held p53/ddo undefined hi-z note 5 held held held held held ad0 to ad15 notes 7, 8 a0 to a15 undefined notes 7, 9 a16 to a21 undefined note 7 hi-z hi-z held hi-z wait ? ? ? ? ? clkout operating l l operating operating wr0, wr1 rd astb h note 7 hi-z hldak h h h l hldrq hi-z note 6 hi-z note 6 operating note 7 ? ? ? operating other port pins hi-z hi-z held held held held held notes 1. duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit) when the power is turned on. 2. operates while alternat e functions are operating. 3. in separate bus mode, the state of the pins in the idle state inserted after the t2 state is shown. in multiplexed bus mode, the state of the pins in the idle state inserted after the t3 state is shown. 4. pulled down during external reset. during internal re set by the watchdog timer, clock monitor, etc., the state of this pin differs according to the ocdm.ocdm0 bit setting. 5. ddo output is specified in the on-chip debug mode. 6. the bus control pins function alternately as port pins, so they are initialized to the input mode (port mode). 7. operates even in the halt mode, during dma operation. 8. in separate bus mode: hi-z in multiplexed bus mode: undefined 9. in separate bus mode remark hi-z: high impedance held: the state during the immediately preceding external bus cycle is held. l: low-level output h: high-level output ? : input without sampling (not acknowledged)
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 20 of 870 sep 30, 2010 2.3 pin i/o circuit types, i/o buffer power supplies, and connection of unused pins (1/3) pin alternate function pin no. i/o circuit type recommended connection p02 nmi 17 p03 intp0/adtrg 18 p04 intp1 19 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p05 intp2/drst 20 10-n input: independently connect to ev ss via a resistor. fixing to v dd level is prohibited. output: leave open. internally pull-down after reset by reset pin. p06 intp3 21 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p10, p11 ano0, ano1 3, 4 12-d input: independently connect to av ref1 or av ss via a resistor. output: leave open. p30 txda0/sob4 25 10-g p31 rxda0/intp7/sib4 26 p32 ascka0/sckb4/tip00 27 p33 tip01/top01 28 p34 tip10/top10 29 p35 tip11/top11 30 10-d p36 ? 31 p37 ? 32 10-g p38 txda2/sda00 35 p39 rxda2/scl00 36 p40 sib0/sda01 22 p41 sob0/scl01 23 p42 sckb0 24 p50 tiq01/kr0/toq01/rtp00 37 p51 tiq02/kr1/toq02/rtp01 38 p52 tiq03/kr2/toq03/rtp02/ddi 39 p53 sib2/kr3/tiq00/toq00/rtp03/ ddo 40 p54 sob2/kr4/rtp04/dck 41 p55 sckb2/kr5/rtp05/dms 42 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open.
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 21 of 870 sep 30, 2010 (2/3) pin alternate function pin no. i/o circuit type recommended connection p70 to p711 ani0 to ani11 100-89 11-g input: independently connect to av ref0 or av ss via a resistor. output: leave open. p90 a0/kr6/txda1/sda02 43 p91 a1/kr7/rxda1/scl02 44 p92 a2/tip41/top41 45 p93 a3/tip40/top40 46 p94 a4/tip31/top31 47 p95 a5/tip30/top30 48 p96 a6/tip21/top21 49 p97 a7/sib1/tip20/top20 50 10-d p98 a8/sob1 51 10-g p99 a9/sckb1 52 p910 a10/sib3 53 10-d p911 a11/sob3 54 10-g p912 a12/sckb3 55 p913 a13/intp4 56 p914 a14/intp5/tip51/top51 57 p915 a15/intp6/tip50/top50 58 10-d pcm0 wait 61 pcm1 clkout 62 pcm2 hldak 63 pcm3 hldrq 64 pct0, pct1 wr0, wr1 65, 66 pct4 rd 67 pct6 astb 68 pdh0 to pdh3 a16 to a19 87, 88, 59, 60 pdh4, pdh5 a20, a21 6, 7 pdl0 to pdl4 ad0 to ad4 71-75 pdl5 ad5/flmd1 76 pdl6 to pdl15 ad6 to ad15 77-86 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open.
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 22 of 870 sep 30, 2010 (3/3) pin alternate function pin no. i/o circuit type recommended connection av ref0 ? 1 ? directly connect to v dd and always supply power. av ref1 ? 5 ? directly connect to v dd and always supply power. av ss ? 2 ? directly connect to v ss and always supply power. ev dd ? 34, 70 ? directly connect to v dd and always supply power. ev ss ? 33, 69 ? directly connect to v ss and always supply power. flmd0 ? 8 ? directly connect to v ss in a mode other than the flash memory programming mode. regc ? 10 ? connect regulator output stabilization capacitance (4.7 f (recommended value)). reset ? 14 2 ? v dd ? 9 ? ? v ss ? 11 ? ? x1 ? 12 ? ? x2 ? 13 ? ? xt1 ? 15 16 connect to v ss . xt2 ? 16 16 leave open.
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 23 of 870 sep 30, 2010 figure 2-1. pin i/o circuits in data output disable p-ch in/out ev dd ev ss n-ch input enable data output disable ev dd ev ss p-ch in/out n-ch open drain input enable data output disable av ref0 p-ch in/out n-ch p-ch n-ch av ref0 input enable + _ av ss av ss data output disable input enable av ref1 p-ch in/out n-ch p-ch n-ch av ss data output disable ev dd ev ss p-ch in/out n-ch open drain input enable n-ch p-ch feedback cut-off xt1 xt2 data output disable ev dd ev ss p-ch in/out n-ch open drain input enable type 2 schmitt-triggered input with hysteresis characteristics type 5 type 10-n type 11-g type 12-d type 10-d type 16 type 10-g analog output voltage (threshold voltage) note note ocdm0 bit note hysteresis characteristics are not available in port mode.
v850es/jg3 chapter 2 pin functions r01uh0015ej0300 rev.3.00 page 24 of 870 sep 30, 2010 2.4 cautions when the power is turned on, the following pin may output an undefined level temporarily, even during reset. ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 25 of 870 sep 30, 2010 chapter 3 cpu function the cpu of the v850es/jg3 is based on ri sc architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 features minimum instruction execution time: 31.25 ns (at 32 mhz operation) 30.5 s (with subclock (f xt ) = 32.768 khz operation) memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear general-purpose registers: 32 bits 32 registers internal 32-bit architecture 5-stage pipeline control multiplication/division instruction saturation operation instruction 32-bit shift instruction: 1 clock load/store instruction with long/short format four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 26 of 870 sep 30, 2010 3.2 cpu register set the registers of the v850es/jg3 can be classified into two types: general-purpose pr ogram registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register)
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 27 of 870 sep 30, 2010 3.2.1 program register set the program registers include general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are ava ilable. any of these registers can be used to store a data variable or an address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the sld and sst instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. when using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is some times used by the real-time os. if the real-time os does not use r2, it can be used as a register for variables. table 3-1. program registers name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as work ing register to create 32-bit immediate data r2 register for address/data variable (if real-time os does not use r2) r3 stack pointer used to create a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as register that i ndicates the beginning of a text area (area where program codes are located) r6 to r29 register for address/data variable r30 element pointer used as base pointer to access memory r31 link pointer used when t he compiler calls a function pc program counter holds the instruction address during program execution remark for furthers details on the r1, r3 to r5, and r31 that are used in the assembler and c compiler, refer to the ca850 (c compiler package) assembly language user?s manual . (2) program counter (pc) the program counter holds the instructio n address during program execution. the lower 26 bits of this register are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to 26 is ignored even if it occurs. bit 0 is fixed to 0. this means that execution cannot branch to an odd address. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 default value 00000000h
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 28 of 870 sep 30, 2010 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. these registers can be read or written by using system register load/store inst ructions (ldsr and stsr), using the system register numbers listed below. table 3-2. system register numbers operand specification system register number system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) note 1 3 nmi status saving register (fepsw) note 1 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 note 2 19 exception/debug trap status saving register (dbpsw) note 2 note 2 20 callt base pointer (ctbp) 21 to 31 reserved for future function expansion (operation is not guaranteed if these registers are accessed) notes 1. because only one set of these registers is availabl e, the contents of these registers must be saved by program if multiple interrupts are enabled. 2. these registers can be accessed only during the inte rval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. caution even if eipc or fepc, or bi t 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti in struction after interr upt servicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). remark : can be accessed : access prohibited
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 29 of 870 sep 30, 2010 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are used to save the status when an interrupt occurs. if a software exception or a maskable interrupt occurs, the contents of the program counter (pc) are saved to eipc, and the contents of the program stat us word (psw) are saved to eipsw (these contents are saved to the nmi status saving registers (fepc and fepsw) if a non-maskable interrupt occurs). the address of the instruction next to the instruction under execution, except some instructions (see 19.8 periods in which interrupts are not acknowledged by cpu ), is saved to eipc when a software exception or a maskable interrupt occurs. the current contents of the psw are saved to eipsw. because only one set of interrupt status saving registers is available, the cont ents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are rese rved for future function expansion (these bits are always fixed to 0). the value of eipc is restored to the pc and the val ue of eipsw to the psw by the reti instruction. 31 0 eipc (saved pc contents) 00 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (saved psw contents) 00 default value 000000xxh (x: undefined) 87 0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 30 of 870 sep 30, 2010 (2) nmi status saving registers (fepc and fepsw) fepc and fepsw are used to save the status when a non-maskable interrupt (nmi) occurs. if an nmi occurs, the contents of the program counter (pc) are saved to f epc, and those of the program status word (psw) are saved to fepsw. the address of the instruction next to t he one of the instruction under execution, except some instructions, is saved to fepc when an nmi occurs. the current contents of t he psw are saved to fepsw. because only one set of nmi status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served for future function expansion (these bits are always fixed to 0). the value of fepc is restored to the pc and the value of fepsw to the psw by the reti instruction. 31 0 fepc (saved pc contents) 00 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (saved psw contents) 00 default value 000000xxh (x: undefined) 87 0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0 (3) interrupt source register (ecr) the interrupt source register (ecr) holds the source of an exception or interrupt if an exception or interrupt occurs. this register holds the exception code of each interrupt source. because this register is a read-only register, data cannot be written to this register using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name meaning 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 31 of 870 sep 30, 2010 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the status of the program (result of instruction execution) and the st atus of the cpu. if the contents of a bit of this regist er are changed by using the ldsr instru ction, the new contents are validated immediately after completion of ldsr instruction execution. however if the id flag is set to 1, interrupt requests will not be acknowledged while the ldsr instruction is being executed. bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 0 psw rfu default value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupts. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is being proces sed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. th is flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether a ca rry or a borrow occurs as a result of an operation. 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note indicates whether an overflow occurs during operation. 0: overflow does not occur. 1: overflow occurs. 1 s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. remark also read note on the next page.
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 32 of 870 sep 30, 2010 (2/2) note the result of the operation that has performed satu ration processing is determined by the contents of the ov and s flags. the sat flag is set to 1 only when the ov flag is set to 1 when a saturation operation is performed. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded 1 1 0 7fffffffh maximum negative value is exceeded 1 1 1 80000000h positive (maximum value is not exceeded) 0 negative (maximum value is not exceeded) holds value before operation 0 1 operation result itself (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execut ion status saving registers. when the callt instruction is executed, the contents of the program counter (pc) are saved to ctpc, and those of the program status word (psw) are saved to ctpsw. the contents saved to ctpc are the address of the inst ruction next to callt. the current contents of t he psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (fixed to 0). 31 0 ctpc (saved pc contents) 00 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (saved psw contents) 00 default value 000000xxh (x: undefined) 87 0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 33 of 870 sep 30, 2010 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status registers. if an exception trap or debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and those of the program status word (psw) are saved to dbpsw. the contents to be saved to dbpc are the address of the instruction next to the one that is being executed when an exception trap or debug trap occurs. the current contents of t he psw are saved to dbpsw. these registers can be read or written onl y during the interval between the exec ution of the dbtrap instruction or illegal opcode and the dbret instruction. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (fixed to 0). the value of dbpc is restored to the pc and the value of dbpsw to the psw by the dbret instruction. 31 0 dbpc (saved pc contents) 00 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (saved psw contents) 00 default value 000000xxh (x: undefined) 87 0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a table address or generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 ctbp (base address) 00 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 34 of 870 sep 30, 2010 3.3 operation modes the v850es/jg3 has the following operation modes. (1) normal operation mode in this mode, each pin related to the bus interface is se t to the port mode after system reset has been released. execution branches to the reset entry address of the intern al rom, and then instruction processing is started. (2) flash memory programming mode in this mode, the internal flash memory can be programmed by using a flash programmer. (3) on-chip debug mode the v850es/jg3 is provided with an on- chip debug function that employs t he jtag (joint test action group) communication specifications. for details, see chapter 28 on-chip debug function . 3.3.1 specifying operation mode specify the operation mode by using the flmd0 and flmd1 pins. in the normal mode, input a low level to the flmd0 pin when reset is released. in the flash memory programming mode, a high level is input to the flmd0 pin from the flash programmer if a flash programmer is connected, but it must be input from an external circuit in the self-programming mode. operation when reset is released flmd0 flmd1 operation mode after reset l normal operation mode h l flash memory programming mode h h setting prohibited remark l: low-level input h: high-level input : don?t care
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 35 of 870 sep 30, 2010 3.4 address space 3.4.1 cpu address space for instruction addressing, up to a combined total of 16 mb of an external memory area and an internal rom area, plus an internal ram area, are supported in a linear addr ess space (program space) of up to 64 mb. for operand addressing (data access), up to 4 gb of a linear address s pace (data space) is supported. the 4 gb address space, however, is viewed as 64 images of a 64 mb physical addre ss space. this means that the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. image on address space program space internal ram area use-prohibited area use-prohibited area external memory area internal rom area (external memory area) data space image 63 image 1 image 0 peripheral i/o area internal ram area use-prohibited area external memory area internal rom area (external memory area) 16 mb 4 gb 64 mb 64 mb
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 36 of 870 sep 30, 2010 3.4.2 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counte r), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. the higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. therefore, the highest address of the program space, 03ffffffh, and t he lowest address, 00000000h, are contiguous addresses. that the highest address and the lo west address of the progra m space are contiguous in this way is called wraparound. caution because the 4 kb area of ad dresses 03fff000h to 03ffffffh is an on-chip peripheral i/o area, instructions cannot be fetched fr om this area. therefore, do no t execute an operation in which the result of a branch addre ss calculation affects this area. program space program space (+) direction ( ?) direction 00000001h 00000000h 03ffffffh 03fffffeh (2) data space the result of an operand address calculation oper ation that exceeds 32 bits is ignored. therefore, the highest address of the data space, ffffffffh, and t he lowest address, 00000000h, are contiguous, and wraparound occurs at the boundary of these addresses. data space data space (+) direction ( ?) direction 00000001h 00000000h ffffffffh fffffffeh
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 37 of 870 sep 30, 2010 3.4.3 memory map the areas shown below are reserved in the v850es/jg3. figure 3-2. data memory map (physical addresses) (64 kb) use prohibited external memory area (14 mb) internal rom area note (1 mb) external memory area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) (2 mb) 03ffffffh 03ff0000h 01000000h 00ffffffh 00200000h 001fffffh 00000000h 03feffffh 03ffffffh 03fff000h 03ffefffh 03ff0000h 001fffffh 00100000h 000fffffh 00000000h note fetch access and read access to addresses 00000000h to 000fffffh is made to the internal rom area. however, data write access to these addresses is made to the external memory area.
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 38 of 870 sep 30, 2010 figure 3-3. program memory map internal ram area (60 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area (14 mb) external memory area (1 mb) internal rom area (1 mb) 03ffffffh 03fff000h 03ffefffh 01000000h 00ffffffh 03ff0000h 03feffffh 00200000h 001fffffh 00100000h 000fffffh 00000000h
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 39 of 870 sep 30, 2010 3.4.4 areas (1) internal rom area up to 1 mb is reserved as an internal rom area. (a) internal rom (384 kb) 384 kb are allocated to addresses 00000000h to 0005ffffh in the pd70f3739. accessing addresses 00060000h to 000fffffh is prohibited. figure 3-4. internal rom area (384 kb) access-prohibited area internal rom (384 kb) 00060000h 0005ffffh 00000000h 000fffffh (b) internal rom (512 kb) 512 kb are allocated to addresses 00000000h to 0007ffffh in the pd70f3740. accessing addresses 00080000h to 000fffffh is prohibited. figure 3-5. internal rom area (512 kb) access-prohibited area internal rom (512 kb) 00080000h 0007ffffh 00000000h 000fffffh
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 40 of 870 sep 30, 2010 (c) internal rom (768 kb) 768 kb are allocated to addresses 00000000h to 000bffffh in the pd70f3741. accessing addresses 000c0000h to 000fffffh is prohibited. figure 3-6. internal rom area (768 kb) access-prohibited area internal rom (768 kb) 000fffffh 000c0000h 000bffffh 00000000h (d) internal rom (1024 kb) 1024 kb are allocated to addresse s 00000000h to 000fffffh in the pd70f3742. figure 3-7. internal rom area (1024 kb) internal rom (1024 kb) 000fffffh 00000000h
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 41 of 870 sep 30, 2010 (2) internal ram area up to 60 kb are reserved as the internal ram area. (a) internal ram (32 kb) 32 kb are allocated to addresses 03ff7000h to 03ffefffh in the pd70f3739. accessing addresses 03ff0000h to 03ff6fffh is prohibited. figure 3-8. internal ram area (32 kb) access-prohibited area internal ram (32 kb) 03ff7000h 03ff6fffh 03ff0000h 03ffefffh physical address space logical address space ffff7000h ffff6fffh ffff0000h ffffefffh (b) internal ram (40 kb) 40 kb are allocated to addresses 03ff5000h to 03ffefffh in the pd70f3740. accessing addresses 03ff0000h to 03ff4fffh is prohibited. figure 3-9. internal ram area (40 kb) access-prohibited area internal ram (40 kb) 03ff5000h 03ff4fffh 03ff0000h 03ffefffh ffff5000h ffff4fffh ffff0000h ffffefffh physical address space logical address space
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 42 of 870 sep 30, 2010 (c) internal ram (60 kb) 60 kb are allocated to addresses 03ff0000h to 03ffefffh in the pd70f3741 and 70f3742. figure 3-10. internal ram area (60 kb) internal ram 03ffefffh ffffefffh ffff0000h 03ff0000h physical address space logical address space
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 43 of 870 sep 30, 2010 (3) on-chip peripheral i/o area 4 kb of addresses 03fff000h to 03ffffffh are re served as the on-chip peripheral i/o area. figure 3-11. on-chip peripheral i/o area on-chip peripheral i/o area (4 kb) 03ffffffh 03fff000h ffffffffh fffff000h physical address space logical address space peripheral i/o registers that have functions to specify the operation mode for and monitor the status of the on-chip peripheral i/o are mapped to the on-ch ip peripheral i/o area. program cannot be fetched from this area. cautions 1. when a register is accessed in word unit s, a word area is accessed twice in halfword units in the order of lower area and higher area, wit h the lower 2 bits of the address ignored. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read, a nd data is written to the lower 8 bits. 3. addresses not defined as registers are reser ved for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. (4) external memory area 15 mb (00100000h to 00ffffffh) are allocated as the external memory area. for details, see chapter 5 bus control function .
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 44 of 870 sep 30, 2010 3.4.5 recommended use of address space the architecture of the v850es/jg3 r equires that a register that serves as a pointer be secured for address generation when operand data in the data space is access ed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. because t he number of general-purpose registers t hat can be used as a pointer is limited, however, by keeping the performance from dropping during addre ss calculation when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program count er), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, therefore, a 64 mb s pace of contiguous addresse s starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the program space, access addresses 03ff0000h to 03ffefffh. caution if a branch instruction is at the upper limit of the internal ram area, a prefetch operation (invalid fetch) straddling the on-chip peripheral i/o area does not occur. (2) data space with the v850es/jg3, it seems that t here are sixty-four 64 mb address spac es on the 4 gb cpu address space. therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address.
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 45 of 870 sep 30, 2010 (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st di sp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the re sources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by ha rdware, and practically eliminates the need for registers dedicated to pointers. example : pd70f3742 internal rom area on-chip peripheral i/o area internal ram area 32 kb 4 kb 28 kb (r = ) 000fffffh 00007fffh 00000000h fffff000h ffffefffh ffff8000h
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 46 of 870 sep 30, 2010 figure 3-12. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited internal ram program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh ffff0000h fffeffffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ff0000h 03feffffh 01000000h 00ffffffh 00100000h 000fffffh 00000000h ffffffffh fffff000h ffffefffh ffff0000h fffeffffh 00100000h 000fffffh 00000000h use prohibited remarks 1. indicates the recommended area. 2. this figure is the recommended memory map of the pd70f3742.
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 47 of 870 sep 30, 2010 3.4.6 peripheral i/o registers (1/10) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl register pdl 0000h note fffff004h port dl register l pdll 00h note fffff005h port dl register h pdlh 00h note fffff006h port dh register pdh 00h note fffff00ah port ct register pct 00h note fffff00ch port cm register pcm 00h note fffff024h port dl mode register pmdl ffffh fffff024h port dl mode register l pmdll ffh fffff025h port dl mode register h pmdlh ffh fffff026h port dh mode register pmdh ffh fffff02ah port ct mode register pmct ffh fffff02ch port cm mode register pmcm ffh fffff044h port dl mode control register pmcdl 0000h fffff044h port dl mode control register l pmcdll 00h fffff045h port dl mode control register h pmcdlh 00h fffff046h port dh mode control register pmcdh 00h fffff04ah port ct mode control register pmcct 00h fffff04ch port cm mode control register pmccm 00h fffff066h bus size configuration register bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source addres s register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source addres s register 1l dsa1l undefined fffff08ah dma source addres s register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source addres s register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h undefined fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h undefined fffff098h dma source addres s register 3l dsa3l undefined fffff09ah dma source addres s register 3h dsa3h undefined fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h undefined fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 undefined fffff0d0h dma addressing control register 0 dadc0 r/w 0000h note the output latch is 00h or 0000h. when these regist ers are in the input mode, the pin statuses are read.
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 48 of 870 sep 30, 2010 (2/10) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 00h fffff0e2h dma channel control register 1 dchc1 00h fffff0e4h dma channel control register 2 dchc2 00h fffff0e6h dma channel control register 3 dchc3 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff110h interrupt control register lviic 47h fffff112h interrupt control register pic0 47h fffff114h interrupt control register pic1 47h fffff116h interrupt control register pic2 47h fffff118h interrupt control register pic3 47h fffff11ah interrupt control register pic4 47h fffff11ch interrupt control register pic5 47h fffff11eh interrupt control register pic6 47h fffff120h interrupt control register pic7 47h fffff122h interrupt control register tq0ovic 47h fffff124h interrupt control register tq0ccic0 47h fffff126h interrupt control register tq0ccic1 47h fffff128h interrupt control register tq0ccic2 47h fffff12ah interrupt control register tq0ccic3 47h fffff12ch interrupt control register tp0ovic 47h fffff12eh interrupt control register tp0ccic0 47h fffff130h interrupt control register tp0ccic1 47h fffff132h interrupt control register tp1ovic 47h fffff134h interrupt control register tp1ccic0 47h fffff136h interrupt control register tp1ccic1 47h fffff138h interrupt control register tp2ovic 47h fffff13ah interrupt control register tp2ccic0 47h fffff13ch interrupt control register tp2ccic1 47h fffff13eh interrupt control register tp3ovic r/w 47h
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 49 of 870 sep 30, 2010 (3/10) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff140h interrupt control register tp3ccic0 47h fffff142h interrupt control register tp3ccic1 47h fffff144h interrupt control register tp4ovic 47h fffff146h interrupt control register tp4ccic0 47h fffff148h interrupt control register tp4ccic1 47h fffff14ah interrupt control register tp5ovic 47h fffff14ch interrupt control register tp5ccic0 47h fffff14eh interrupt control register tp5ccic1 47h fffff150h interrupt control register tm0eqic0 47h fffff1 52 h interrupt control register cb0ric/iicic1 47h fffff1 54 h interrupt control register cb0tic 47h fffff156h interrupt control register cb1ric 47h fffff158h interrupt control register cb1tic 47h fffff15ah interrupt control register cb2ric 47h fffff15ch interrupt control register cb2tic 47h fffff15eh interrupt control register cb3ric 47h fffff160h interrupt control register cb3tic 47h fffff162h interrupt control register ua0ric/cb4ric 47h fffff164h interrupt control register ua0tic/cb4tic 47h fffff166h interrupt control register ua1ric/iicic2 47h fffff168h interrupt control register ua1tic 47h fffff16ah interrupt control register ua2ric/iicic0 47h fffff16ch interrupt control register ua2tic 47h fffff16eh interrupt control register adic 47h fffff170h interrupt control register dmaic0 47h fffff172h interrupt control register dmaic1 47h fffff174h interrupt control register dmaic2 47h fffff176h interrupt control register dmaic3 47h fffff178h interrupt control register kric 47h fffff17ah interrupt control register wtiic 47h fffff17ch interrupt control register wtic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc 00h fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail compare mode register ada0pfm 00h fffff205h power-fail compare threshold value register ada0pft r/w 00h
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 50 of 870 sep 30, 2010 (4/10) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff210h a/d conversion result register 0 ada0cr0 undefined fffff211h a/d conversion result register 0h ada0cr0h undefined fffff212h a/d conversion result register 1 ada0cr1 undefined fffff213h a/d conversion result register 1h ada0cr1h undefined fffff214h a/d conversion result register 2 ada0cr2 undefined fffff215h a/d conversion result register 2h ada0cr2h undefined fffff216h a/d conversion result register 3 ada0cr3 undefined fffff217h a/d conversion result register 3h ada0cr3h undefined fffff218h a/d conversion result register 4 ada0cr4 undefined fffff219h a/d conversion result register 4h ada0cr4h undefined fffff21ah a/d conversion result register 5 ada0cr5 undefined fffff21bh a/d conversion result register 5h ada0cr5h undefined fffff21ch a/d conversion result register 6 ada0cr6 undefined fffff21dh a/d conversion result register 6h ada0cr6h undefined fffff21eh a/d conversion result register 7 ada0cr7 undefined fffff21fh a/d conversion result register 7h ada0cr7h undefined fffff220h a/d conversion result register 8 ada0cr8 undefined fffff221h a/d conversion result register 8h ada0cr8h undefined fffff222h a/d conversion result register 9 ada0cr9 undefined fffff223h a/d conversion result register 9h ada0cr9h undefined fffff224h a/d conversion result register 10 ada0cr10 undefined fffff225h a/d conversion result register 10h ada0cr10h undefined fffff226h a/d conversion result register 11 ada0cr11 undefined fffff227h a/d conversion result register 11h ada0cr11h r undefined fffff280h d/a converter conversion value setting register 0 da0cs0 00h fffff281h d/a converter conversion value setting register 1 da0cs1 00h fffff282h d/a converter mode register da0m 00h fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff310h crc input register crcin 00h fffff312h crc data register crcd 0000h fffff318h noise elimination control register nfc 00h fffff320h brg1 prescaler mode register prsm1 00h fffff321h brg1 prescaler compare register prscm1 00h fffff324h brg2 prescaler mode register prsm2 00h fffff325h brg2 prescaler compare register prscm2 00h fffff328h brg3 prescaler mode register prsm3 00h fffff329h brg3 prescaler compare register prscm3 00h fffff340h iic division clock select register ocks0 00h fffff344h iic division clock select register ocks1 00h fffff400h port 0 register p0 00h note fffff402h port 1 register p1 r/w 00h note note the output latch is 00h or 0000h. when these registers are input, the pin statuses are read.
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 51 of 870 sep 30, 2010 (5/10) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff406h port 3 register p3 0000h note fffff406h port 3 register l p3l 00h note fffff407h port 3 register h p3h 00h note fffff408h port 4 register p4 00h note fffff40ah port 5 register p5 00h note fffff40eh port 7 register l p7l 00h note fffff40fh port 7 register h p7h 00h note fffff412h port 9 register p9 0000h note fffff412h port 9 register l p9l 00h note fffff413h port 9 register h p9h 00h note fffff420h port 0 mode register pm0 ffh fffff422h port 1 mode register pm1 ffh fffff426h port 3 mode register pm3 ffffh fffff426h port 3 mode register l pm3l ffh fffff427h port 3 mode register h pm3h ffh fffff428h port 4 mode register pm4 ffh fffff42ah port 5 mode register pm5 ffh fffff42eh port 7 mode register l pm7l ffh fffff42fh port 7 mode register h pm7h ffh fffff432h port 9 mode register pm9 ffffh fffff432h port 9 mode register l pm9l ffh fffff433h port 9 mode register h pm9h ffh fffff440h port 0 mode control register pmc0 00h fffff446h port 3 mode control register pmc3 0000h fffff446h port 3 mode control register l pmc3l 00h fffff447h port 3 mode control register h pmc3h 00h fffff448h port 4 mode control register pmc4 00h fffff44ah port 5 mode control register pmc5 00h fffff452h port 9 mode control register pmc9 0000h fffff452h port 9 mode control register l pmc9l 00h fffff453h port 9 mode control register h pmc9h 00h fffff460h port 0 function control register pfc0 00h fffff466h port 3 function control register pfc3 0000h fffff466h port 3 function control register l pfc3l 00h fffff467h port 3 function control register h pfc3h 00h fffff468h port 4 function control register pfc4 00h fffff46ah port 5 function control register pfc5 00h fffff472h port 9 function control register pfc9 0000h fffff472h port 9 function control register l pfc9l 00h fffff473h port 9 function control register h pfc9h r/w 00h note the output latch is 00h or 0000h. when these registers are input, the pin statuses are read.
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 52 of 870 sep 30, 2010 (6/10) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc aaaah fffff540h tmq0 control register 0 tq0ctl0 00h fffff541h tmq0 control register 1 tq0ctl1 00h fffff542h tmq0 i/o control register 0 tq0ioc0 00h fffff543h tmq0 i/o control register 1 tq0ioc1 00h fffff544h tmq0 i/o control register 2 tq0ioc2 00h fffff545h tmq0 option register 0 tq0opt0 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 0000h fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 counter read buffer register tq0cnt r 0000h fffff590h tmp0 control register 0 tp0ctl0 00h fffff591h tmp0 control register 1 tp0ctl1 00h fffff592h tmp0 i/o control register 0 tp0ioc0 00h fffff593h tmp0 i/o control register 1 tp0ioc1 00h fffff594h tmp0 i/o control register 2 tp0ioc2 00h fffff595h tmp0 option register 0 tp0opt0 00h fffff596h tmp0 capture/compare register 0 tp0ccr0 0000h fffff598h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter read buffer register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 00h fffff5a1h tmp1 control register 1 tp1ctl1 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 00h fffff5a3h tmp1 i/o control register 1 tp1ioc1 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 00h fffff5a5h tmp1 option register 0 tp1opt0 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter read buffer register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 00h fffff5b1h tmp2 control register 1 tp2ctl1 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 00h fffff5b5h tmp2 option register 0 tp2opt0 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 0000h fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter read buffer register tp2cnt r 0000h fffff5c0h tmp3 control register 0 tp3ctl0 00h fffff5c1h tmp3 control register 1 tp3ctl1 r/w 00h
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 53 of 870 sep 30, 2010 (7/10) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5c2h tmp3 i/o control register 0 tp3ioc0 00h fffff5c3h tmp3 i/o control register 1 tp3ioc1 00h fffff5c4h tmp3 i/o control register 2 tp3ioc2 00h fffff5c5h tmp3 option register 0 tp3opt0 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 1 tp3ccr1 r/w 0000h fffff5cah tmp3 counter read buffer register tp3cnt r 0000h fffff5d0h tmp4 control register 0 tp4ctl0 00h fffff5d1h tmp4 control register 1 tp4ctl1 00h fffff5d2h tmp4 i/o control register 0 tp4ioc0 00h fffff5d3h tmp4 i/o control register 1 tp4ioc1 00h fffff5d4h tmp4 i/o control register 2 tp4ioc2 00h fffff5d5h tmp4 option register 0 tp4opt0 00h fffff5d6h tmp4 capture/compare register 0 tp4ccr0 0000h fffff5d8h tmp4 capture/compare register 1 tp4ccr1 r/w 0000h fffff5dah tmp4 counter read buffer register tp4cnt r 0000h fffff5e0h tmp5 control register 0 tp5ctl0 00h fffff5e1h tmp5 control register 1 tp5ctl1 00h fffff5e2h tmp5 i/o control register 0 tp5ioc0 00h fffff5e3h tmp5 i/o control register 1 tp5ioc1 00h fffff5e4h tmp5 i/o control register 2 tp5ioc2 00h fffff5e5h tmp5 option register 0 tp5opt0 00h fffff5e6h tmp5 capture/compare register 0 tp5ccr0 0000h fffff5e8h tmp5 capture/compare register 1 tp5ccr1 r/w 0000h fffff5eah tmp5 counter read buffer register tp5cnt r 0000h fffff680h watch timer operation mode register wtm 00h fffff690h tmm0 control register 0 tm0ctl0 00h fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff6e0h real-time output buffer register 0l rtbl0 00h fffff6e2h real-time output buffer register 0h rtbh0 00h fffff6e4h real-time output port mode register 0 rtpm0 00h fffff6e5h real-time output port control register 0 rtpc0 00h fffff706h port 3 function control expansion register l pfce3l 00h fffff70ah port 5 function control expansion register pfce5 00h fffff712h port 9 function control expansion register pfce9 0000h fffff712h port 9 function control expansion register l pfce9l 00h fffff713h port 9 function control expansion register h pfce9h 00h fffff802h system status register sys 00h fffff80ch internal oscillation mode register rcm 00h fffff810h dma trigger factor register 0 dtfr0 r/w 00h
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 54 of 870 sep 30, 2010 (8/10) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff812h dma trigger factor register 1 dtfr1 00h fffff814h dma trigger factor register 2 dtfr2 00h fffff816h dma trigger factor register 3 dtfr3 00h fffff820h power save mode register psmr 00h fffff822h clock control register ckc r/w 0ah fffff824h lock register lockr r 00h fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operation clock status register ccls 00h fffff870h clock monitor mode register clm 00h fffff888h reset source flag register resf 00h fffff890h low-voltage detection register lvim 00h fffff891h low-voltage detection level select register lvis 00h fffff892h internal ram data status register rams 01h fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff9fch on-chip debug mode register ocdm 01h fffff9feh peripheral emul ation register 1 pemu1 note 00h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 ffh fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str r/w 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 transmit data register ua1tx ffh fffffa20h uarta2 control register 0 ua2ctl0 10h fffffa21h uarta2 control register 1 ua2ctl1 00h fffffa22h uarta2 control register 2 ua2ctl2 ffh fffffa23h uarta2 option control register 0 ua2opt0 14h fffffa24h uarta2 status register ua2str r/w 00h fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx ffh fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc06h external interrupt falling edge specification register 3 intf3 r/w 00h note only during emulation
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 55 of 870 sep 30, 2010 (9/10) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffc13h external interrupt falling edge specification register 9h intf9h 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc26h external interrupt rising edge specification register 3 intr3 00h fffffc33h external interrupt rising edge specification register 9h intr9h 00h fffffc60h port 0 function register pf0 00h fffffc66h port 3 function register pf3 0000h fffffc66h port 3 function register l pf3l 00h fffffc67h port 3 function register h pf3h 00h fffffc68h port 4 function register pf4 00h fffffc6ah port 5 function register pf5 00h fffffc72h port 9 function register pf9 0000h fffffc72h port 9 function register l pf9l 00h fffffc73h port function 9 register h pf9h 00h fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1 control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl 00h fffffd20h csib2 control register 0 cb2ctl0 01h fffffd21h csib2 control register 1 cb2ctl1 00h fffffd22h csib2 control register 2 cb2ctl2 00h fffffd23h csib2 status register cb2str r/w 00h fffffd24h csib2 receive data register cb2rx 0000h fffffd24h csib2 receive data register l cb2rxl r 00h fffffd26h csib2 transmit data register cb2tx 0000h fffffd26h csib2 transmit data register l cb2txl 00h fffffd30h csib3 control register 0 cb3ctl0 01h fffffd31h csib3 control register 1 cb3ctl1 00h fffffd32h csib3 control register 2 cb3ctl2 00h fffffd33h csib3 status register cb3str r/w 00h fffffd34h csib3 receive data register cb3rx 0000h fffffd34h csib3 receive data register l cb3rxl r 00h
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 56 of 870 sep 30, 2010 (10/10) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffd36h csib3 transmit data register cb3tx 0000h fffffd36h csib3 transmit data register l cb3txl 00h fffffd40h csib4 control register 0 cb4ctl0 01h fffffd41h csib4 control register 1 cb4ctl1 00h fffffd42h csib4 control register 2 cb4ctl2 00h fffffd43h csib4 status register cb4str r/w 00h fffffd44h csib4 receive data register cb4rx 0000h fffffd44h csib4 receive data register l cb4rxl r 00h fffffd46h csib4 transmit data register cb4tx 0000h fffffd46h csib4 transmit data register l cb4txl 00h fffffd80h iic shift register 0 iic0 00h fffffd82h iic control register 0 iicc0 00h fffffd83h slave address register 0 sva0 00h fffffd84h iic clock select register 0 iiccl0 00h fffffd85h iic function expansion register 0 iicx0 r/w 00h fffffd86h iic status register 0 iics0 r 00h fffffd8ah iic flag register 0 iicf0 00h fffffd90h iic shift register 1 iic1 00h fffffd92h iic control register 1 iicc1 00h fffffd93h slave address register 1 sva1 00h fffffd94h iic clock select register 1 iiccl1 00h fffffd95h iic function expansion register 1 iicx1 r/w 00h fffffd96h iic status register 1 iics1 r 00h fffffd9ah iic flag register 1 iicf1 00h fffffda0h iic shift register 2 iic2 00h fffffda2h iic control register 2 iicc2 00h fffffda3h slave address register 2 sva2 00h fffffda4h iic clock select register 2 iiccl2 00h fffffda5h iic function expansion register 2 iicx2 r/w 00h fffffda6h iic status register 2 iics2 r 00h fffffdaah iic flag register 2 iicf2 00h fffffdbeh external bus interface mode control register eximc r/w 00h
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 57 of 870 sep 30, 2010 3.4.7 special registers special registers are registers that are protected from being written with ille gal data due to a program hang-up. the v850es/jg3 has the following eight special registers. ? power save control register (psc) ? clock control register (ckc) ? processor clock control register (pcc) ? clock monitor mode register (clm) ? reset source flag register (resf) ? low-voltage detection register (lvim) ? internal ram data status register (rams) ? on-chip debug mode register (ocdm) in addition, the prcdm register is provided to protect agai nst a write access to the special registers so that the application system does not inadvertently stop due to a program ha ng-up. a write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the sys register.
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 58 of 870 sep 30, 2010 (1) setting data to special registers set data to the special registers in the following sequence. <1> disable dma operation. <2> prepare data to be set to the special register in a general-purpose register. <3> write the data prepared in <2> to the prcmd register. <4> write the setting data to the special re gister (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) (<5> to <9> insert nop instructions (5 instructions).) note <10> enable dma operation if necessary. [example] with psc register (setting standby mode) st.b r11, psmr[r0] ; set psmr register (setting idle1, idle2, and stop modes). <1>clr1 0, dchcn[r0] ; disable dma operation. n = 0 to 3 <2>mov0x02, r10 <3>st.b r10, prcmd[r0] ; write prcmd register. <4>st.b r10, psc[r0] ; set psc register. <5>nop note ; dummy instruction <6>nop note ; dummy instruction <7>nop note ; dummy instruction <8>nop note ; dummy instruction <9>nop note ; dummy instruction <10>set1 0, dchcn[r0] ; enable dma operation. n = 0 to 3 (next instruction) there is no special sequence to read a special register. note five nop instructions or more must be inserted immediately after setting the idle1 mode, idle2 mode, or stop mode (by setting the psc.stp bit to 1). cautions 1. when a store instruction is executed to store data in the command register, interrupts are not acknowledged. this is because it is assumed that steps <3> and <4> above are performed by successive store instructions. if another instru ction is placed between <3> and <4>, and if an interrupt is acknowledged by that instructi on, the above sequence may not be established, causing malfunction. 2. although dummy data is written to th e prcmd register, use the same general-purpose register used to set the special register (<4> in example) to write data to the prcmd register (<3> in example). the same a pplies when a general-purpose regi ster is used for addressing.
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 59 of 870 sep 30, 2010 (2) command register (prcmd) the prcmd register is an 8-bit register that protects the regist ers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. the first write access to a special register is valid after data has been written in adv ance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 60 of 870 sep 30, 2010 (3) system status register (sys) status flags that indicate the ope ration status of the overall system are allocated to this register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 protection error did not occur protection error occurred prerr 0 1 detects protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) (i) when data is written to a special register without writing anything to the prcmd register (when <4> is executed without executing <3> in 3.4.7 (1) setting data to special registers ) (ii) when data is written to an on-chip peripheral i/o register other than a sp ecial register (including execution of a bit manipulation instruction) after writing data to the prcmd register (if <4> in 3.4.7 (1) setting data to special registers is not the setting of a special register) remark even if an on-chip peripheral i/o register is read (except by a bit manipulation instruction) between an operation to write the prcmd register and an ope ration to write a special register, the prerr flag is not set, and the set data can be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the prerr flag (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcmd register, the prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to the prcmd register, which is not a special regi ster, immediately after a write access to the prcmd register , the prerr bit is set to 1.
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 61 of 870 sep 30, 2010 3.4.8 cautions (1) registers to be set first be sure to set the following registers first when using the v850es/jg3. ? system wait control register (vswc) ? on-chip debug mode register (ocdm) ? watchdog timer mode register 2 (wdtm2) after setting the vswc, ocdm, and wdtm2 registers, set the other registers as necessary. when using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related registers after setting the above registers. (a) system wait control register (vswc) the vswc register controls wait of bus access to the on-chip peripheral i/o registers. three clocks are required to access an on-chip peripheral i/o register (without a wait cycle). the v850es/jg3 requires wait cycles according to the operating frequency. set the following value to the vswc register in accordance with the frequency used. the vswc register can be read or written in 8-bit units (address: fffff06eh, default value: 77h). operating frequency (f clk ) set value of vswc number of waits 32 khz f clk < 16.6 mhz 00h 0 (no waits) 16.6 mhz f clk < 25 mhz 01h 1 25 mhz f clk 32 mhz 11h 2 (b) on-chip debug mode register (ocdm) for details, see chapter 28 on-chip debug function . (c) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time a nd the operation clock of watchdog timer 2. watchdog timer 2 automatically starts in the reset mode af ter reset is released. write the wdtm2 register to activate this operation. for details, refer to chapter 11 functions of watchdog timer 2 .
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 62 of 870 sep 30, 2010 (2) accessing specific on-chip peripheral i/o registers this product has two types of internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with low-speed peripheral hardware. the clock of the cpu bus and the clock of the periphera l bus are asynchronous. if an access to the cpu and an access to the peripheral hardware conflict, therefore, unex pected illegal data may be transferred. if there is a possibility of a conflict, the number of cycles for accessing the cpu changes when the peripheral hardware is accessed, so that correct data is transfe rred. as a result, the cpu does not st art processing of the next instruction but enters the wait state. if this wa it state occurs, the number of clocks r equired to execute an instruction increases by the number of wait clocks shown below. this must be taken into consideration if real-time processing is required. when specific on-chip peripheral i/o registers are accessed, more wait states may be required in addition to the wait states set by the vswc register. the access conditions and how to calculate the number of wait states to be inserted (number of cpu clocks) at this time are shown below. peripheral function register name access k tpncnt read 1 or 2 write ? 1st access: no wait ? continuous write: 3 or 4 16-bit timer/event counter p (tmp) (n = 0 to 5) tpnccr0, tpnccr1 read 1 or 2 tq0cnt read 1 or 2 write ? 1st access: no wait ? continuous write: 3 or 4 16-bit timer/event counter q (tmq) tq0ccr0 to tq0ccr3 read 1 or 2 watchdog timer 2 (wdt2) wdtm2 write (when wdt2 operating) 3 real-time output function (rto) rtbl0, rtbh0 write (rtpc0.rtpoe0 bit = 0) 1 ada0m0 read 1 or 2 ada0cr0 to ada0cr11 read 1 or 2 a/d converter ada0cr0h to ada0cr11h read 1 or 2 i 2 c00 to i 2 c02 iics0 to iics2 read 1 crc crcd write 1 number of clocks necessary for access = 3 + i + j + (2 + j) k caution accessing the above registers is prohibited in the following statuses. if a wait cycle is generated, it can only be cleared by a reset. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock remark i: values (0 or 1) of higher 4 bits of vswc register j: values (0 or 1) of lower 4 bits of vswc register
v850es/jg3 chapter 3 cpu function r01uh0015ej0300 rev.3.00 page 63 of 870 sep 30, 2010 (3) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request be fore the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sl d.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 ld.w [r11], r10 if the decode operation of the mo v instruction immediately before the sld instruction and an interrupt request conflic t before execution of the ld instruction is complete, the execution result of in struction may not be stored in a register. mov r10, r28 sld.w 0x28, r10 (b) countermeasure <1> when compiler (ca850) is used use ca850 ver. 2.61 or later because generation of the corresponding instruction sequence can be automatically suppressed. <2> countermeasure by assembler when executing the sld instruction immediately afte r instruction , avoid the above operation using either of the following methods. ? insert a nop instruction immediately before the sld instruction. ? do not use the same register as the sld instructi on destination register in t he above instruction executed immediately befor e the sld instruction. ? ? ?
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 64 of 870 sep 30, 2010 chapter 4 port functions 4.1 features { i/o ports: 84 ? 5 v tolerant/n-ch open-drain output selectable: 40 (ports 0, 3 to 5, 9) { input/output specifiable in 1-bit units 4.2 basic port configuration the v850es/jg3 features a total of 84 i/o por ts consisting of ports 0, 1, 3 to 5, 7, 9, cm, ct, dh, and dl. the port configuration is shown below. figure 4-1. port configuration diagram p02 p06 port 0 pcm0 pcm3 port cm p90 p915 port 9 pct0 pct1 pct4 pct6 port ct pdh0 pdh5 port dh pdl0 pdl15 port dl p30 p39 port 3 port 1 p40 p42 port 4 p50 p55 port 5 p70 p711 port 7 p10 p11 caution ports 0, 3 to 5, and 9 are 5 v tolerant. table 4-1. i/o buffer power supplies for pins power supply corresponding pins av ref0 port 7 av ref1 port 1 ev dd reset, ports 0, 3 to 5, 9, cm, ct, dh, dl
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 65 of 870 sep 30, 2010 4.3 port configuration table 4-2. port configuration item configuration control register port n mode register (pmn: n = 0, 1, 3 to 5, 7, 9, cd, cm, ct, dh, dl) port n mode control register (pmcn: n = 0, 3 to 5, 9, cm, ct, dh, dl) port n function control register (pfcn: n = 0, 3 to 5, 9) port n function control expansion register (pfcen: n = 3, 5, 9) port n function register (pfn: n = 0, 3 to 5, 9) ports i/o: 84 (1) port n register (pn) data is input from or output to an external device by writing or reading the pn register. the pn register consists of a port latch that holds output data, and a circ uit that reads the status of pins. each bit of the pn register corresponds to one pin of port n, and can be read or written in 1-bit units. pn7 outputs 0. outputs 1. pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h (output latch) r/w data is written to or read from the pn register as follows, regardless of the setting of the pmcn register. table 4-3. writing/reading pn register setting of pmn register writing to pn register reading from pn register output mode (pmnm = 0) data is written to the output latch note . in the port mode (pmcn = 0), the contents of the output latch are output from the pins. the value of the output latch is read. input mode (pmnm = 1) data is written to the output latch. the pin status is not affected note . the pin status is read. note the value written to the output latch is retained until a new value is written to the output latch.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 66 of 870 sep 30, 2010 (2) port n mode register (pmn) the pmn register specifies the input or output mode of the corresponding port pin. each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of input/output mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) the pmcn register specifies the port mode or alternate function. each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit units. port mode alternate function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 67 of 870 sep 30, 2010 (4) port n function control register (pfcn) the pfcn register specifies the alternat e function of a port pin to be used if the pin has two alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function (5) port n function control expansion register (pfcen) the pfcen register specifies the alternate function of a port pin to be used if the pin has three or more alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 68 of 870 sep 30, 2010 (6) port n function register (pfn) the pfn register specifies normal output or n-ch open-drain output. each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1- bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 control of normal output/n-ch open-drain output pfn after reset: 00h r/w note the pfnm bit of the pfn register is valid only when the pmnm bit of the pmn register is 0 (when the output mode is specified) in port mode (pmcnm bit = 0). when the pmnm bit is 1 (when the input mode is specified), the set value of the pfn register is invalid.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 69 of 870 sep 30, 2010 (7) port setting set a port as illustrated below. figure 4-2. setting of each register and pin function pmcn register output mode input mode pmn register ?0? ?1? ?0? ?1? ?0? ?1? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark set the alternate functions in the following sequence. <1> set the pfcn and pfcen registers. <2> set the pmcn register. <3> set the intrn or intfn register (to specify an external interrupt pin). if the pmcn register is set first, an unintende d function may be set while the pfcn and pfcen registers are being set.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 70 of 870 sep 30, 2010 4.3.1 port 0 port 0 is a 5-bit port for which i/o settings can be controlled in 1-bit units. port 0 includes the following alternate-function pins. table 4-4. port 0 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p02 17 nmi input l-1 p03 18 intp0/adtrg input n-1 p04 19 intp1 input l-1 p05 20 intp2/drst note input aa-1 p06 21 intp3 input selectable as n-ch open-drain output l-1 note the drst pin is for on-chip debugging. if on-chip debugging is not used, fix the p05/intp2/drs t pin to low level between when the reset signal of the reset pin is released and when the ocdm.ocdm0 bit is cleared (0). for details, see 4.6.3 cautions on on-chip debug pins . caution the p02 to p06 pins have hysteresis characteristi cs in the input mode of th e alternate function, but do not have hysteresis characteristics in the port mode. (1) port 0 register (p0) 0 outputs 0. outputs 1. p0n 0 1 output data control (in output mode) (n = 2 to 6) p0 p06 p05 p04 p03 p02 0 0 after reset: 00h (output latch) r/w address: fffff400h
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 71 of 870 sep 30, 2010 (2) port 0 mode register (pm0) 1 output mode input mode pm0n 0 1 i/o mode control (n = 2 to 6) pm0 pm06 pm05 pm04 pm03 pm02 1 1 after reset: ffh r/w address: fffff420h (3) port 0 mode control register (pmc0) 0 pmc0 pmc06 pmc05 pmc04 pmc03 pmc02 0 0 i/o port intp3 input pmc06 0 1 specification of p06 pin operation mode i/o port intp2 input pmc05 0 1 specification of p05 pin operation mode i/o port intp1 input pmc04 0 1 specification of p04 pin operation mode i/o port intp0 input/adtrg input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode after reset: 00h r/w address: fffff440h caution the p05/intp2/drst pin becomes the drst pin regardless of the value of the pmc05 bit when the ocdm.ocdm0 bit = 1.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 72 of 870 sep 30, 2010 (4) port 0 function control register (pfc0) pfc0 after reset: 00h r/w address: fffff460h 0 0 0 0 pfc03 0 0 0 intp0 input adtrg input pfc03 0 1 specification of p03 pin alternate function (5) port 0 function register (pf0) 0 normal output (cmos output) n-ch open drain output pf0n 0 1 control of normal output or n-ch open-drain output (n = 2 to 6) pf0 pf06 pf05 pf04 pf03 pf02 0 0 after reset: 00h r/w address: fffffc60h caution when an output pin is pulled up at ev dd or higher, be sure to set the pf0n bit to 1.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 73 of 870 sep 30, 2010 4.3.2 port 1 port 1 is a 2-bit port for which i/o settings can be controlled in 1-bit units. port 1 includes the following alternate-function pins. table 4-5. port 1 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p10 3 ano0 output ? a-2 p11 4 ano1 output ? a-2 (1) port 1 register (p1) 0 outputs 0. outputs 1. p1n 0 1 output data control (in output mode) (n = 0, 1) p1 0 0 0 0 0 p11 p10 after reset: 00h (output latch) r/w address: fffff402h caution do not read or write the p1 register during d/a conversion (see 14.4.3 cautions). (2) port 1 mode register (pm1) 1 output mode input mode pm1n 0 1 i/o mode control (n = 0, 1) pm1 1 1 1 1 1 pm11 pm10 after reset: ffh r/w address: fffff422h cautions 1. when using p1n as the alternate functi on (anon pin output), set the pm1n bit to 1. 2. when using one of the p10 and p11 pins as an i/o port and the other as a d/a output pin, do so in an application wher e the port i/o level does not change during d/a output.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 74 of 870 sep 30, 2010 4.3.3 port 3 port 3 is a 10-bit port for which i/o settings can be controlled in 1-bit units. port 3 includes the following alternate-function pins. table 4-6. port 3 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p30 25 txda0/sob4 output g-3 p31 26 rxda0/intp7/sib4 input n-3 p32 27 ascka0/sckb4/tip00/top00 i/o u-1 p33 28 tip01/top01 i/o g-1 p34 29 tip10/top10 i/o g-1 p35 30 tip11/top11 i/o g-1 p36 31 ? ? c-1 p37 32 ? ? c-1 p38 35 txda2/sda00 i/o g-12 p39 36 rxda2/scl00 i/o selectable as n-ch open-drain output g-6 caution the p31 to p35, p38, and p39 pins have hyster esis characteristics in the in put mode of the alternate- function pin, but do not have the hyster esis characteristics in the port mode.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 75 of 870 sep 30, 2010 (1) port 3 register (p3) outputs 0. outputs 1. p3n 0 1 output data control (in output mode) (n = 0 to 9) p3 (p3h) after reset: 0000h (output latch) r/w address: p3 fffff406h, p3l fffff406h, p3h fffff407h 0 0 0 0 0 0 p39 p38 p37 p36 p35 p34 p33 p32 p31 p30 8 9 10 11 12 13 14 15 (p3l) remarks 1. the p3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the p3 register as the p3h register and the lower 8 bits as the p3l register, p3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the p3h register. (2) port 3 mode register (pm3) 1 output mode input mode pm3n 0 1 i/o mode control (n = 0 to 9) 1 1 1 1 1 pm39 pm38 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: pm3 fffff426h, pm3l fffff426h, pm3h fffff427h 8 9 10 11 12 13 14 15 pm3 (pm3h) (pm3l) remarks 1. the pm3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pm3 register as the pm3h register and the lower 8 bits as the pm3l register, pm3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of t he pm3 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pm3h register.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 76 of 870 sep 30, 2010 (3) port 3 mode control register (pmc3) i/o port rxda2 input/scl00 i/o pmc39 0 1 specification of p39 pin operation mode i/o port txda2 output/sda00 i/o pmc38 0 1 specification of p38 pin operation mode after reset: 0000h r/w address: pmc3 fffff446h, pmc3l fffff446h, pmc3h fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pmc3 (pmc3h) (pmc3l) i/o port tip11 input/top11 output pmc35 0 1 specification of p35 pin operation mode i/o port tip10 input/top10 output pmc34 0 1 specification of p34 pin operation mode i/o port tip01 input/top01 output pmc33 0 1 specification of p33 pin operation mode i/o port ascka0 input/sckb4 i/o/tip00 input/top00 output pmc32 0 1 specification of p32 pin operation mode i/o port rxda0 input/sib4 input/intp7 input pmc31 0 1 specification of p31 pin operation mode i/o port txda0 output/sob4 output pmc30 0 1 specification of p30 pin operation mode caution be sure to set bits 15 to 10, 7, and 6 to ?0?. remarks 1. the pmc3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmc3 register as the pmc3h register and the lower 8 bits as the pmc3l register, pmc3 c an be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc3h register.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 77 of 870 sep 30, 2010 (4) port 3 function control register (pfc3) after reset: 0000h r/w address: pfc3 fffff466h, pfc3l fffff466h, pfc3h fffff467h 0 0 0 0 0 0 pfc39 pfc38 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfc3 (pfc3h) (pfc3l) remarks 1. for details of alternate function specification, see 4.3.3 (6) port 3 alternate function specifications . 2. the pfc3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc3 register as the pfc3h register and the lower 8 bits as the pfc3l register, pfc3 can be read or written in 8-bit and 1-bit units. 3. to read/write bits 8 to 15 of the pfc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc3h register. (5) port 3 function control ex pansion register l (pfce3l) pfce3l after reset: 00h r/w address: fffff706h 0 0 0 0 0 pfce32 0 0 caution be sure to set bits 7 to 3, 1, and 0 to ?0?. remark for details of alternate function specification, see 4.3.3 (6) port 3 alternate function specifications .
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 78 of 870 sep 30, 2010 (6) port 3 alternate function specifications pfc39 specification of p39 pin alternate function 0 rxda2 input 1 scl00 input pfc38 specification of p38 pin alternate function 0 txda2 output 1 sda00 i/o pfc35 specification of p35 pin alternate function 0 tip11 input 1 top11 output pfc34 specification of p34 pin alternate function 0 tip10 input 1 top10 output pfc33 specification of p33 pin alternate function 0 tip01 input 1 top01 output pfce32 pfc32 specification of p32 pin alternate function 0 0 ascka0 input 0 1 sckb4 i/o 1 0 tip00 input 1 1 top00 output pfc31 specification of p31 pin alternate function 0 rxda0 input/intp7 note input 1 sib4 input pfc30 specification of p30 pin alternate function 0 txda0 output 1 sob4 output note the intp7 pin and rxda0 pin are alternate-function pi ns. when using the pin as the rxda0 pin, disable edge detection for the intp7 alternate-function pin. (clear the intf3.intf31 bit and the intr3.intr31 bit to 0.) when using the pin as the intp7 pin, st op uarta0 reception. (clear the ua0ctl0.ua0rxe bit to 0.)
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 79 of 870 sep 30, 2010 (7) port 3 function register (pf3) after reset: 0000h r/w address: pf3 fffffc66h, pf3l fffffc66h, pf3h fffffc67h pf37 pf36 pf35 pf34 pf33 pf32 pf31 pf30 0 0 0 0 0 0 pf39 pf38 8 9 10 11 12 13 14 15 normal output (cmos output) n-ch open-drain output pf3n 0 1 control of normal output or n-ch open-drain output (n = 0 to 9) pf3 (pf3h) (pf3l) caution when an output pin is pulled up at ev dd or higher, be sure to set the pf3n bit to 1. remarks 1. the pf3 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pf3 register as the pf3h register and the lower 8 bits as the pf3l register, pf3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of th e pf3 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pf3h register.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 80 of 870 sep 30, 2010 4.3.4 port 4 port 4 is a 3-bit port that controls i/o in 1-bit units. port 4 includes the following alternate-function pins. table 4-7. port 4 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p40 22 sib0/sda01 i/o g-6 p41 23 sob0/scl01 i/o g-12 p42 24 sckb0 i/o selectable as n-ch open-drain output e-3 caution the p40 to p42 pins have hysteresis characteristi cs in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. (1) port 4 register (p4) 0 outputs 0. outputs 1. p4n 0 1 output data control (in output mode) (n = 0 to 2) p4 0 0 0 0 p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h (2) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 i/o mode control (n = 0 to 2) pm4 1 1 1 1 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 81 of 870 sep 30, 2010 (3) port 4 mode control register (pmc4) 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 i/o port sckb0 i/o pmc42 0 1 specification of p42 pin operation mode i/o port sob0 output/scl01 i/o pmc41 0 1 specification of p41 pin operation mode i/o port sib0 input/sda01 i/o pmc40 0 1 specification of p40 pin operation mode after reset: 00h r/w address: fffff448h (4) port 4 function control register (pfc4) pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 sob0 output scl01 i/o pfc41 0 1 specification of p41 pin alternate function sib0 input sda01 i/o pfc40 0 1 specification of p40 pin alternate function
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 82 of 870 sep 30, 2010 (5) port 4 function register (pf4) 0 normal output (cmos output) n-ch open-drain output pf4n 0 1 control of normal output or n-ch open-drain output (n = 0 to 2) pf4 0 0 0 0 pf42 pf41 pf40 after reset: 00h r/w address: fffffc68h caution when an output pin is pulled up at ev dd or higher, be sure to set the pf4n bit to 1.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 83 of 870 sep 30, 2010 4.3.5 port 5 port 5 is a 6-bit port that controls i/o in 1-bit units. port 5 includes the following alternate-function pins. table 4-8. port 5 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p50 37 tiq01/kr0/toq01/rtp00 i/o u-5 p51 38 tiq02/kr1/toq02/rtp01 i/o u-5 p52 39 tiq03/kr2/toq03/rtp02/ddi note i/o u-6 p53 40 sib2/kr3/tiq00/toq00/rtp03/ddo note i/o u-7 p54 41 sob2/kr4/rtp04/dck note i/o u-8 p55 42 sckb2/kr5/rtp05/dms note i/o selectable as n-ch open-drain output u-9 note the ddi, ddo, dck, and dms pins are for on-chip debugging. if on-chip debugging is not used, fix the p05/intp2/drs t pin to low level between when the reset signal of the reset pin is released and when the ocdm.ocdm0 bit is cleared (0). for details, see 4.6.3 cautions on on-chip debug pins . cautions 1. when the power is tu rned on, the p53 pin may output undefined level temporarily even during reset. 2. the p50 to p55 pins have hyst eresis characteristics in the input mode of the alternate function, but do not have hysteresis char acteristics in the port mode. (1) port 5 register (p5) 0 outputs 0 outputs 1 p5n 0 1 output data control (in output mode) (n = 0 to 5) p5 0 p55 p54 p53 p52 p51 p50 after reset: 00h (output latch) r/w address: fffff40ah
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 84 of 870 sep 30, 2010 (2) port 5 mode register (pm5) 1 output mode input mode pm5n 0 1 i/o mode control (n = 0 to 5) pm5 1 pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah (3) port 5 mode control register (pmc5) 0 pmc5 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 i/o port sckb2 i/o/kr5 input/rtp05 output pmc55 0 1 specification of p55 pin operation mode i/o port sob2 output/kr4 input/rtp04 output pmc54 0 1 specification of p54 pin operation mode i/o port sib2 input/kr3 input/tiq00 input/toq00 output/rtp03 output pmc53 0 1 specification of p53 pin operation mode i/o port tiq03 input/kr2 input/toq03 output/rtp02 output pmc52 0 1 specification of p52 pin operation mode i/o port tiq02 input/kr1 input/toq02 output/rtp01 output pmc51 0 1 specification of p51 pin operation mode i/o port tiq01 input/kr0 input/toq01 output/rtp00 output pmc50 0 1 specification of p50 pin operation mode after reset: 00h r/w address: fffff44ah
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 85 of 870 sep 30, 2010 (4) port 5 function control register (pfc5) 0 pfc5 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 after reset: 00h r/w address: fffff46ah remark for details of alternate function specification, see 4.3.5 (6) port 5 alternate function specifications . (5) port 5 function control expansion register (pfce5) 0 pfce5 0 pfce55 pfce54 pfce53 pfce52 pfce51 pfce50 after reset: 00h r/w address: fffff70ah remark for details of alternate function specification, see 4.3.5 (6) port 5 alternate function specifications . (6) port 5 alternate function specifications pfce55 pfc55 specification of p55 pin alternate function 0 0 sckb2 i/o 0 1 kr5 input 1 0 setting prohibited 1 1 rtp05 output pfce54 pfc54 specification of p54 pin alternate function 0 0 sob2 output 0 1 kr4 input 1 0 setting prohibited 1 1 rtp04 output pfce53 pfc53 specification of p53 pin alternate function 0 0 sib2 input 0 1 tiq00 input/kr3 note input 1 0 toq00 output 1 1 rtp03 output
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 86 of 870 sep 30, 2010 pfce52 pfc52 specification of p52 pin alternate function 0 0 setting prohibited 0 1 tiq03 input/kr2 note input 1 0 toq03 input 1 1 rtp02 output pfce51 pfc51 specification of p51 pin alternate function 0 0 setting prohibited 0 1 tiq02 input/kr1 note input 1 0 toq02 output 1 1 rtp01 output pfce50 pfc50 specification of p50 pin alternate function 0 0 setting prohibited 0 1 tiq01 input/kr0 note input 1 0 toq01 output 1 1 rtp00 output note the krn pin and tiq0m pin are alternate-function pins. when using the pin as the tiq0m pin, disable krn pin key return detection, which is the alternate f unction. (clear the krm.krmn bit to 0.) also, when using the pin as the krn pin, disable tiq0m pin edge dete ction, which is the alternate function (n = 0 to 3, m = 0 to 3). pin name use as tiq0m pin use as krn pin kr0/tiq01 krm.krm0 bit = 0 tq0ioc1. tq0tig2, tq0ioc1. tq0tig3 bits = 0 kr1/tiq02 krm.krm1 bit = 0 tq0ioc1.tq0tig4, tq0ioc1.tq0tig5 bits = 0 kr2/tiq03 krm.krm2 bit = 0 tq0ioc1.tq0tig6, tq0ioc1.tq0tig7 bits = 0 kr3/tiq00 krm.krm3 bit = 0 tq0ioc1.tq0tig0, tq0ioc1.tq0tig1 bits = 0 tq0ioc2.tq0ees0, tq0ioc2.tq0ees1 bits = 0 tq0ioc2.tq0ets0, tq0ioc2.tq0ets1 bits = 0 (7) port 5 function register (pf5) 0 normal output (cmos output) n-ch open-drain output pf5n 0 1 control of normal output or n-ch open-drain output (n = 0 to 5) pf5 0 pf55 pf54 pf53 pf52 pf51 pf50 after reset: 00h r/w address: fffffc6ah caution when an output pin is pulled up at ev dd or higher, be sure to set the pf5n bit to 1.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 87 of 870 sep 30, 2010 4.3.6 port 7 port 7 is a 12-bit port for which i/o settings can be controlled in 1-bit units. port 7 includes the following alternate-function pins. table 4-9. port 7 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p70 100 ani0 input a-1 p71 99 ani1 input a-1 p72 98 ani2 input a-1 p73 97 ani3 input a-1 p74 96 ani4 input a-1 p77 95 ani5 input a-1 p76 94 ani6 input a-1 p77 93 ani7 input a-1 p78 92 ani8 input a-1 p79 91 ani9 input a-1 p710 90 ani10 input a-1 p711 89 ani11 input ? a-1
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 88 of 870 sep 30, 2010 (1) port 7 register h, port 7 register l (p7h, p7l) outputs 0 outputs 1 p7n 0 1 output data control (in output mode) (n = 0 to 11) p7h p7l after reset: 00h (output latch) r/w address: p7l fffff40eh, p7h fffff40fh p77 p76 p75 p74 p73 p72 p71 p70 0 0 0 0 p711 p710 p79 p78 caution do not read/write the p7h and p7l re gisters during a/d conversion (see 13.6 (4) alternate i/o). remark these registers cannot be accessed in 16-bit units as the p7 register. they can be read or written in 8-bit or 1-bit units as the p7h and p7l registers. (2) port 7 mode register h, port 7 mode register l (pm7h, pm7l) 1 output mode input mode pm7n 0 1 i/o mode control (n = 0 to 11) pm7h pm7l 1 1 1 pm711 pm710 pm79 pm78 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 after reset: ffh r/w address: pm7l fffff42eh, pm7h fffff42fh caution when using the p7n pin as its alternate function (anin pin), set the pm7n bit to 1. remark these registers cannot be accessed in 16-bit units as the pm7 register. they can be read or written in 8-bit or 1-bit units as the pm7h and pm7l registers.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 89 of 870 sep 30, 2010 4.3.7 port 9 port 9 is a 16-bit port for which i/o settings can be controlled in 1-bit units. port 9 includes the following alternate-function pins. table 4-10. port 9 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p90 43 a0/kr6/txda1/sda02 i/o u-10 p91 44 a1/kr7/rxda1/scl02 i/o u-11 p92 45 a2/tip41/top41 i/o u-12 p93 46 a3/tip40/top40 i/o u-12 p94 47 a4/tip31/top31 i/o u-12 p95 48 a5/tip30/top30 i/o u-12 p96 49 a6/tip21/top21 i/o u-13 p97 50 a7/sib1/tip20/top20 i/o u-14 p98 51 a8/sob1 output g-3 p99 52 a9/sckb1 i/o g-5 p910 53 a10/sib3 i/o g-2 p911 54 a11/sob3 output g-3 p912 55 a12/sckb3 i/o g-5 p913 56 a13/intp4 i/o n-2 p914 57 a14/intp5/tip51/top51 i/o u-15 p915 58 a15/intp6/tip50/top50 i/o selectable as n-ch open-drain output u-15 caution the p90 to p97, p99, p910, and p912 to p915 pi ns have hysteresis characteristics in the input mode of the alternate-function pin, but do not have th e hysteresis characteristics in the port mode.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 90 of 870 sep 30, 2010 (1) port 9 register (p9) p915 outputs 0 outputs 1 p9n 0 1 output data control (in output mode) (n = 0 to 15) p914 p913 p912 p911 p910 p99 p98 after reset: 0000h (output latch) r/w address: p9 fffff412h, p9l fffff412h, p9h fffff413h p97 p96 p95 p94 p93 p92 p91 p90 8 9 10 11 12 13 14 15 p9 (p9h) (p9l) remarks 1. the p9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the p9 register as the p9h register and the lower 8 bits as the p9l register, p9 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the p9h register. (2) port 9 mode register (pm9) pm97 output mode input mode pm9n 0 1 i/o mode control (n = 0 to 15) pm96 pm95 pm94 pm93 pm92 pm91 pm90 after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h pm915 pm914 pm913 pm912 pm911 pm910 pm99 pm98 8 9 10 11 12 13 14 15 pm9 (pm9h) (pm9l) remarks 1. the pm9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pm9 register as the pm9h register and the lower 8 bits as the pm9l register, pm9 can be read or written in 8-bit and 1-bit units. 2. to read/write bits 8 to 15 of t he pm9 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pm9h register.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 91 of 870 sep 30, 2010 (3) port 9 mode control register (pmc9) (1/2) i/o port a15 output/intp6 input/tip50 input/top50 output pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 i/o port a14 output/intp5 input/tip51 input/top51 output pmc914 0 1 specification of p914 pin operation mode i/o port a11 output/sob3 output pmc911 0 1 specification of p911 pin operation mode i/o port a10 output/sib3 input pmc910 0 1 specification of p910 pin operation mode i/o port a9 output/sckb1 i/o pmc99 0 1 specification of p99 pin operation mode i/o port a13 output/intp4 input pmc913 0 1 specification of p913 pin operation mode i/o port a12 output/sckb3 i/o pmc912 0 1 specification of p912 pin operation mode 8 9 10 11 12 13 14 15 pmc9 (pmc9h) (pmc9l) remarks 1. the pmc9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmc9 register as the pmc9h register and the lower 8 bits as the pmc9l register, pmc9 c an be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc9h register.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 92 of 870 sep 30, 2010 (2/2) i/o port a8 output/sob1 output pmc98 0 1 specification of p98 pin operation mode i/o port a7 output/sib1 input/tip20 input/top20 output pmc97 0 1 specification of p97 pin operation mode i/o port a6 output/tip21 input/top21 output pmc96 0 1 specification of p96 pin operation mode i/o port a5 output/tip30 input/top30 output pmc95 0 1 specification of p95 pin operation mode i/o port a4 output/tip31 input/top31 output pmc94 0 1 specification of p94 pin operation mode i/o port a3 output/tip40 input/top40 output pmc93 0 1 specification of p93 pin operation mode i/o port a2 output/tip41 input/top41 output pmc92 0 1 specification of p92 pin operation mode i/o port a1 output/kr7 input/rxda1 input/scl02 i/o pmc91 0 1 specification of p91 pin operation mode i/o port a0 output/kr6 input/txda1 output/sda02 i/o pmc90 0 1 specification of p90 pin operation mode caution when using the a0 to a 15 pins as the alternate functions of the p90 to p915 pins, set all 16 bits of the pmc9 register to ffffh at once.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 93 of 870 sep 30, 2010 (4) port 9 function control register (pfc9) caution when performing separate address bus output (a0 to a15), set the pmc9 register to ffffh for all 16 bits at once after clearing the pfc9 or pfce9 register to 0000h. after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 8 9 10 11 12 13 14 15 pfc9 (pfc9h) (pfc9l) remarks 1. for details of alternate function specification, see 4.3.7 (6) port 9 alternate function specifications . 2. the pfc9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc9 register as the pfc9h register and the lower 8 bits as the pfc9l register, pfc9 c an be read or written in 8-bit or 1-bit units. 3. to read/write bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc9h register. (5) port 9 function control expansion register (pfce9) caution when performing separate address bus output (a0 to a15), set the pmc9 register to ffffh for all 16 bits at once after clearing the pf c9 or pfce9 register to 0000h. after reset: 0000h r/w address: pfce9 fffff712h, pfce9l fffff712h, pfce9h fffff713h pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 pfce915 pfce914 0 0 0 0 0 0 8 9 10 11 12 13 14 15 pfce9 (pfce9h) (pfce9l) remarks 1. for details of alternate function specification, see 4.3.7 (6) port 9 alternate function specifications . 2. the pfce9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfce9 register as the pfce9h register and the lower 8 bits as the pfce9l register, pfce9 can be read or written in 8-bit or 1- bit units. 3. to read/write bits 8 to 15 of t he pfce9 register in 8-bit or 1- bit units, specify them as bits 0 to 7 of the pfce9h register.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 94 of 870 sep 30, 2010 (6) port 9 alternate function specifications pfce915 pfc915 specification of p915 pin alternate function 0 0 a15 output 0 1 intp6 input 1 0 tip50 input 1 1 top50 output pfce914 pfc914 specification of p914 pin alternate function 0 0 a14 output 0 1 intp5 input 1 0 tip51 input 1 1 top51 output pfc913 specification of p913 pin alternate function 0 a13 output 1 intp4 input pfc912 specification of p912 pin alternate function 0 a12 output 1 sckb3 i/o pfc911 specification of p911 pin alternate function 0 a11 output 1 sob3 output pfc910 specification of p910 pin alternate function 0 a10 output 1 sib3 input pfc99 specification of p99 pin alternate function 0 a9 output 1 sckb1 i/o pfc98 specification of p98 pin alternate function 0 a8 output 1 sob1 output pfce97 pfc97 specification of p97 pin alternate function 0 0 a7 output 0 1 sib1 input 1 0 tip20 input 1 1 top20 output
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 95 of 870 sep 30, 2010 pfce96 pfc96 specification of p96 pin alternate function 0 0 a6 output 0 1 setting prohibited 1 0 tip21 input 1 1 top21 output pfce95 pfc95 specification of p95 pin alternate function 0 0 a5 output 0 1 tip30 input 1 0 top30 output 1 1 setting prohibited pfce94 pfc94 specification of p94 pin alternate function 0 0 a4 output 0 1 tip31 input 1 0 top31 output 1 1 setting prohibited pfce93 pfc93 specification of p93 pin alternate function 0 0 a3 output 0 1 tip40 input 1 0 top40 output 1 1 setting prohibited pfce92 pfc92 specification of p92 pin alternate function 0 0 a2 output 0 1 tip41 input 1 0 top41 output 1 1 setting prohibited pfce91 pfc91 specification of p91 pin alternate function 0 0 a1 output 0 1 kr7 input 1 0 rxda1 input/kr7 input note 1 1 scl02 i/o pfce90 pfc90 specification of p90 pin alternate function 0 0 a0 output 0 1 kr6 input 1 0 txda1 output 1 1 sda02 i/o note the rxda1 and kr7 pins must not be used at the same time. when using the rxda1 pin, do not use the kr7 pin. when using the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear the pfce91 bit to 0).
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 96 of 870 sep 30, 2010 (7) port 9 function register (pf9) after reset: 0000h r/w address: pf3 fffffc72h, pf9l fffffc72h, pf9h fffffc73h pf97 pf96 pf95 pf94 pf93 pf92 pf91 pf90 pf915 pf914 pf913 pf912 pf911 pf910 pf99 pf98 normal output (cmos output) n-ch open-drain output pf9n 0 1 control of normal output or n-ch open-drain output (n = 0 to 15) 8 9 10 11 12 13 14 15 pf9 (pf9h) (pf9l) caution when an output pin is pulled up at ev dd or higher, be sure to set the pf9n bit to 1. remarks 1. the pf9 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pf9 register as the pf9h register and the lower 8 bits as the pf9l register, pf9 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of th e pf9 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pf9h register.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 97 of 870 sep 30, 2010 4.3.8 port cm port cm is a 4-bit port for which i/o setti ngs can be controlled in 1-bit units. port cm includes the following alternate-function pins. table 4-11. port cm alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pcm0 61 wait input d-1 pcm1 62 clkout output d-2 pcm2 63 hldak output d-2 pcm3 64 hldrq input ? d-1 (1) port cm register (pcm) 0 outputs 0. outputs 1. pcmn 0 1 output data control (in output mode) (n = 0 to 3) pcm 0 0 0 pcm3 pcm2 pcm1 pcm0 after reset: 00h (output latch) r/w address: fffff00ch (2) port cm mode register (pmcm) 1 output mode input mode pmcmn 0 1 i/o mode control (n = 0 to 3) pmcm 1 1 1 pmcm3 pmcm2 pmcm1 pmcm0 after reset: ffh r/w address: fffff02ch
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 98 of 870 sep 30, 2010 (3) port cm mode control register (pmccm) 0 pmccm 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 i/o port hldrq input pmccm3 0 1 specification of pcm3 pin operation mode i/o port hldak output pmccm2 0 1 specification of pcm2 pin operation mode i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode i/o port wait input pmccm0 0 1 specification of pcm0 pin operation mode after reset: 00h r/w address: fffff04ch
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 99 of 870 sep 30, 2010 4.3.9 port ct port ct is a 4-bit port for which i/o setti ngs can be controlled in 1-bit units. port ct includes the following alternate-function pins. table 4-12. port ct alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pct0 65 wr0 output d-2 pct1 66 wr1 output d-2 pct4 67 rd output d-2 pct6 68 astb output ? d-2 (1) port ct register (pct) 0 outputs 0. outputs 1. pctn 0 1 output data control (in output mode) (n = 0, 1, 4, 6) pct pct6 0 pct4 0 0 pct1 pct0 after reset: 00h (output latch) r/w address: fffff00ah (2) port ct mode register (pmct) 1 output mode input mode pmctn 0 1 i/o mode control (n = 0, 1, 4, 6) pmct pmct6 1 pmct4 1 1 pmct1 pmct0 after reset: ffh r/w address: fffff02ah
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 100 of 870 sep 30, 2010 (3) port ct mode control register (pmcct) 0 pmcct pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 i/o port astb output pmcct6 0 1 specification of pct6 pin operation mode i/o port rd output pmcct4 0 1 specification of pct4 pin operation mode i/o port wr1 output pmcct1 0 1 specification of pct1 pin operation mode i/o port wr0 output pmcct0 0 1 specification of pct0 pin operation mode after reset: 00h r/w address: fffff04ah
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 101 of 870 sep 30, 2010 4.3.10 port dh port dh is a 6-bit port for which i/o settings can be controlled in 1-bit units. port dh includes the following alternate-function pins. table 4-13. port dh alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pdh0 87 a16 output d-2 pdh1 88 a17 output d-2 pdh2 59 a18 output d-2 pdh3 60 a19 output d-2 pdh4 6 a20 output d-2 pdh5 7 a21 output ? d-2 (1) port dh register (pdh) outputs 0. outputs 1. pdhn 0 1 output data control (in output mode) (n = 0 to 5) pdh after reset: 00h (output latch) r/w address: fffff006h 0 0 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 (2) port dh mode register (pmdh) 1 output mode input mode pmdhn 0 1 i/o mode control (n = 0 to 5) 1 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 102 of 870 sep 30, 2010 (3) port dh mode control register (pmcdh) i/o port am output (address bus output) (m = 16 to 21) pmcdhn 0 1 specification of pdhn pin operation mode (n = 0 to 5) 0 0 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h pmcdh
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 103 of 870 sep 30, 2010 4.3.11 port dl port dl is a 16-bit port for which i/o se ttings can be controll ed in 1-bit units. port dl includes the following alternate-function pins. table 4-14. port dl alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pdl0 71 ad0 i/o d-3 pdl1 72 ad1 i/o d-3 pdl2 73 ad2 i/o d-3 pdl3 74 ad3 i/o d-3 pdl4 75 ad4 i/o d-3 pdl5 76 ad5/flmd1 note i/o d-3 pdl6 77 ad6 i/o d-3 pdl7 78 ad7 i/o d-3 pdl8 79 ad8 i/o d-3 pdldl 80 ad9 i/o d-3 pdl10 81 ad10 i/o d-3 pdl11 82 ad11 i/o d-3 pdl12 83 ad12 i/o d-3 pdl13 84 ad13 i/o d-3 pdl14 85 ad14 i/o d-3 pdl15 86 ad15 i/o ? d-3 note since this pin is set in the flash memory progra mming mode, it does not need to be manipulated with the port control register. for details, see chapter 27 flash memory .
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 104 of 870 sep 30, 2010 (1) port dl register (pdl) pdl15 outputs 0. outputs 1. pdln 0 1 output data control (in output mode) (n = 0 to 15) pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 after reset: 0000h (output latch) r/w address: pdl fffff004h, pdll fffff004h, pdlh fffff005h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 pdl (pdlh) (pdll) remarks 1. the pdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pdl register as t he pdlh register and the lower 8 bits as the pdll register, pdl can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pdlh register. (2) port dl mode register (pmdl) pmdl7 output mode input mode pmdln 0 1 i/o mode control (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: pmdl fffff024h, pmdll fffff024h, pmdlh fffff025h pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 pmdl (pmdlh) (pmdll) remarks 1. the pmdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmdl register as the pmdlh register and the lower 8 bits as the pmdll register, pmdl can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmdlh register.
v850es/jg3 chapter 4 port functions r01uh0015ej0300 rev.3.00 page 105 of 870 sep 30, 2010 (3) port dl mode control register (pmcdl) i/o port adn i/o (address/data bus i/o) pmcdln 0 1 specification of pdln pin operation mode (n = 0 to 15) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 after reset: 0000h r/w address: pmcdl fffff044h, pmcdll fffff044h, pmcdlh fffff045h pmcdl15 pmcdl14pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 pmcdl (pmcdlh) (pmcdll) caution when the smsel bit of the eximc register = 1 (separat e mode) and the bs30 to bs00 bits of the bsc register = 0 (8-bit bus width ), do not specify the ad8 to ad15 pins. remarks 1. the pmcdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmcdl register as the pmcdlh register and the lower 8 bits as the pmcdll register, pmcdl can be read or written in 8-bit or 1- bit units. 2. to read/write bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcdlh register.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 106 of 870 sep 30, 2010 4.4 block diagrams figure 4-3. block diagram of type a-1 address rd a/d input signal wr pm pmmn wr port pmn pmn p-ch n-ch internal bus selector selector
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 107 of 870 sep 30, 2010 figure 4-4. block diagram of type a-2 rd d/a output signal wr pm pmmn wr port pmn pmn p-ch n-ch internal bus selector selector address
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 108 of 870 sep 30, 2010 figure 4-5. block diagram of type c-1 address rd wr port pmn wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch internal bus selector selector
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 109 of 870 sep 30, 2010 figure 4-6. block diagram of type d-1 wr port pmn wr pm pmmn wr pmc pmcmn rd input signal when alternate function is used pmn internal bus selector selector address
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 110 of 870 sep 30, 2010 figure 4-7. block diagram of type d-2 wr port pmn wr pm pmmn wr pmc pmcmn rd output signal when alternate function is used pmn internal bus selector selector selector address
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 111 of 870 sep 30, 2010 figure 4-8. block diagram of type d-3 wr port pmn wr pm pmmn wr pmc pmcmn rd pmn output signal when alternate function is used input signal when alternate function is used output enable signal of address/data bus input enable signal of address/data bus output buffer off signal internal bus selector selector selector selector address
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 112 of 870 sep 30, 2010 figure 4-9. block diagram of type e-3 rd wr port pmn wr pmc pmcmn wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch output signal when alternate function is used output enable signal when alternate function is used input signal when alternate function is used note internal bus selector selector selector address note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 113 of 870 sep 30, 2010 figure 4-10. block diagram of type g-1 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal when alternate function is used pmn ev dd ev ss p-ch n-ch note internal bus selector selector selector address note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 114 of 870 sep 30, 2010 figure 4-11. block diagram of type g-2 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal when alternate function is used pmn ev dd ev ss p-ch n-ch note internal bus selector selector selector address note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 115 of 870 sep 30, 2010 figure 4-12. block diagram of type g-3 output signal 2 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch internal bus selector selector selector selector address
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 116 of 870 sep 30, 2010 figure 4-13. block diagram of type g-5 rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch input signal when alternate function is used note internal bus selector selector selector selector address note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 117 of 870 sep 30, 2010 figure 4-14. block diagram of type g-6 output signal when alternate function is used input signal 1 when alternate function is used input signal 2 when alternate function is used note internal bus selector selector selector selector address rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 118 of 870 sep 30, 2010 figure 4-15. block diagram of type g-12 input signal when alternate function is used output signal 1 when alternate function is used output signal 2 when alternate function is used note internal bus selector address rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch selector selector selector note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 119 of 870 sep 30, 2010 figure 4-16. block diagram of type l-1 input signal 1 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch edge detection noise elimination note 2 internal bus selector selector address notes 1. see 19.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 120 of 870 sep 30, 2010 figure 4-17. block diagram of type n-1 input signal 1 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn input signal 2 when alternate function is used ev dd ev ss p-ch n-ch edge detection noise elimination note 2 internal bus selector selector selector address notes 1. see 19.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 121 of 870 sep 30, 2010 figure 4-18. block diagram of type n-2 internal bus address input signal when alternate function is used selector selector selector rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn ev dd ev ss p-ch n-ch edge detection noise elimination note 2 output signal when alternate function is used notes 1. see 19.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 122 of 870 sep 30, 2010 figure 4-19. block diagram of type n-3 input signal 1-1 when alternate function is used input signal 1-2 when alternate function is used input signal 2 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn ev dd ev ss p-ch n-ch note 2 internal bus selector selector selector address edge detection noise elimination notes 1. see 19.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 123 of 870 sep 30, 2010 figure 4-20. block diagram of type u-1 input signal 2 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 1 when alternate function is used input signal 3 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector address note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 124 of 870 sep 30, 2010 figure 4-21. block diagram of type u-5 input signal 1-1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 1-2 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address noise elimination note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 125 of 870 sep 30, 2010 figure 4-22. block diagram of type u-6 input signal 1-1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 1-2 when alternate function is used input signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 126 of 870 sep 30, 2010 figure 4-23. block diagram of type u-7 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 2-1 when alternate function is used input signal 2-2 when alternate function is used output signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 127 of 870 sep 30, 2010 figure 4-24. block diagram of type u-8 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 128 of 870 sep 30, 2010 figure 4-25. block diagram of type u-9 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used input signal when on-chip debugging output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 129 of 870 sep 30, 2010 figure 4-26. block diagram of type u-10 internal bus address input signal 1 when alternate function is used selector selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used output signal 2 when alternate function is used output signal 3 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn noise elimination note selector note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 130 of 870 sep 30, 2010 figure 4-27. block diagram of type u-11 internal bus address input signal 1 when alternate function is used selector selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 3 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn input signal 2 when alternate function is used ev dd ev ss p-ch n-ch wr pfce pfcemn noise elimination note selector note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 131 of 870 sep 30, 2010 figure 4-28. block diagram of type u-12 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 132 of 870 sep 30, 2010 figure 4-29. block diagram of type u-13 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 133 of 870 sep 30, 2010 figure 4-30. block diagram of type u-14 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address selector note hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 134 of 870 sep 30, 2010 figure 4-31. block diagram of type u-15 input signal 1 when alternate function is used input signal 2 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn wr pfce pfcemn pmmn pmn ev dd ev ss p-ch n-ch output signal 2 when alternate function is used output signal 1 when alternate function is used note 2 internal bus selector selector selector selector address edge detection noise elimination selector notes 1. see 19.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 135 of 870 sep 30, 2010 figure 4-32. block diagram of type aa-1 rd wr port pmn wr intf intfmn note 1 wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch n-ch wr intr intrmn note 1 ev ss input signal when on-chip debugging external reset signal input signal when alternate function is used note 2 internal bus selector selector address edge detection noise elimination notes 1. see 19.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 136 of 870 sep 30, 2010 4.5 port register settings when alternate function is used table 4-15 shows the port register settings when each port is used for an alternate function. when using a port pin as an alternate-function pin, refer to the description of each pin.
r01uh0015ej0300 rev.3.00 page 137 of 888 sep 30, 2010 v850es/jg3 chapter 4 port functions table 4-15. using port pin as alternate-function pin (1/7) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) p02 nmi input p02 = setting not required pm02 = setting not required pmc02 = 1 ? ? intp0 input p03 = setting not required pm03 = setting not required pmc03 = 1 ? pfc03 = 0 p03 adtrg input p03 = setting not required pm03 = setting not required pmc03 = 1 ? pfc03 = 1 p04 intp1 input p04 = setting not required pm04 = setting not required pmc04 = 1 ? ? intp2 input p05 = setting not required pm05 = setting not required pmc05 = 1 ? ? p05 drst input p05 = setting not required pm05 = setting not required pmc05 = setting not r equired ? ? ocdm0 (ocdm) = 1 p06 intp3 input p06 = setting not required pm06 = setting not required pmc06 = 1 ? ? p10 ano0 output p10 = setting not required pm10 = 1 ? ? ? p11 ano1 output p11 = setting not required pm11 = 1 ? ? ? txda0 output p30 = setting not required pm30 = setting not required pmc30 = 1 ? pfc30 = 0 p30 sob4 output p30 = setting not required pm30 = setting not required pmc30 = 1 ? pfc30 = 1 rxda0 input p31 = setting not required pm31 = setting not required pmc31 = 1 ? note , pfc31 = 0 intp7 input p31 = setting not required pm31 = setting not required pmc31 = 1 ? note , pfc31 = 0 p31 sib4 input p31 = setting not required pm31 = setting not required pmc31 = 1 ? pfc31 = 1 ascka0 input p32 = setting not required pm32 = setting not required pmc32 = 1 pfce32 = 0 pfc32 = 0 sckb4 i/o p32 = setting not required pm32 = setting not required pmc32 = 1 pfce32 = 0 pfc32 = 1 tip00 input p32 = setting not required pm32 = setting not required pmc32 = 1 pfce32 = 1 pfc32 = 0 p32 top00 output p32 = setting not required pm32 = setting not required pmc32 = 1 pfce32 = 1 pfc32 = 1 tip01 input p33 = setting not required pm33 = setting not required pmc33 = 1 ? pfc33 = 0 p33 top01 output p33 = setting not required pm33 = setting not required pmc33 = 1 ? pfc33 = 1 note the intp7 pin and rxda0 pin are alternate-function pins. when usi ng the pin as the rxda0 pin, disable edge detection for the a lternate-function intp7 pin (clear the intf3.intf31 bit and intr3.intr31 bit to 0). when using the pin as the intp7 pin, stop the uarta0 reception operation (clear t he ua0ctl0.ua0rxe bit to 0). caution when using one of the p10 and p11 pins as an i/o port and the other as a d/a output pin (ano0, ano1), do so in an appli cation where the port i/o level does not change during d/a output.
r01uh0015ej0300 rev.3.00 page 138 of 888 sep 30, 2010 v850es/jg3 chapter 4 port functions table 4-15. using port pin as alternate-function pin (2/7) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) tip10 input p34 = setting not required pm34 = setting not required pmc34 = 1 ? pfc34 = 0 p34 top10 output p34 = setting not required pm34 = setting not required pmc34 = 1 ? pfc34 = 1 tip11 input p35 = setting not required pm35 = setting not required pmc35 = 1 ? pfc35 = 0 p35 top11 output p35 = setting not required pm35 = setting not required pmc35 = 1 ? pfc35 = 1 txda2 output p38 = setting not required pm38 = setting not required pmc38 = 1 ? pfc38 = 0 p38 sda00 i/o p38 = setting not required pm38 = setting not required pmc38 = 1 ? pfc38 = 1 pf38 (pf3) = 1 rxda2 input p39 = setting not required pm39 = setting not required pmc39 = 1 ? pfc39 = 0 p39 scl00 i/o p39 = setting not required pm39 = setting not required pmc39 = 1 ? pfc39 = 1 pf39 (pf3) = 1 sib0 input p40 = setting not required pm40 = setting not required pmc40 = 1 ? pfc40 = 0 p40 sda01 i/o p40 = setting not required pm40 = setting not required pmc40 = 1 ? pfc40 = 1 pf40 (pf4) = 1 sob0 output p41 = setting not required pm41 = setting not required pmc41 = 1 ? pfc41 = 0 p41 scl01 i/o p41 = setting not required pm41 = setting not required pmc41 = 1 ? pfc41 = 1 pf41 (pf4) = 1 p42 sckb0 i/o p42 = setting not required pm42 = setting not required pmc42 = 1 ? ? tiq01 input p50 = setting not required pm50 = setting not required pmc50 = 1 pfce50 = 0 pfc50 = 1 krm0 (krm) = 0 kr0 input p50 = setting not required pm50 = setting not required pmc50 = 1 pfce50 = 0 pfc50 = 1 tq 0tig2, tq0tig3 (tq0ioc1) = 0 toq01 output p50 = setting not required pm50 = setting not required pmc50 = 1 pfce50 = 1 pfc50 = 0 p50 rtp00 output p50 = setting not required pm50 = setting not required pmc50 = 1 pfce50 = 1 pfc50 = 1 tiq02 input p51 = setting not required pm51 = setting not required pmc51 = 1 pfce51 = 0 pfc51 = 1 krm1 (krm) = 0 kr1 input p51 = setting not required pm51 = setting not required pmc51 = 1 pfce51 = 0 pfc51 = 1 tq 0tig4, tq0tig5 (tq0ioc1) = 0 toq02 output p51 = setting not required pm51 = setting not required pmc51 = 1 pfce51 = 1 pfc51 = 0 p51 rtp01 output p51 = setting not required pm51 = setting not required pmc51 = 1 pfce51 = 1 pfc51 = 1 tiq03 input p52 = setting not required pm52 = setting not required pmc52 = 1 pfce52 = 0 pfc52 = 1 krm2 (krm) = 0 kr2 input p52 = setting not required pm52 = setting not required pmc52 = 1 pfce52 = 0 pfc52 = 1 tq 0tig6, tq0tig7 (tq0i0c1) = 0 toq03 output p52 = setting not required pm52 = setting not required pmc52 = 1 pfce52 = 1 pfc52 = 0 rtp02 output p52 = setting not required pm52 = setting not required pmc52 = 1 pfce52 = 1 pfc52 = 1 p52 ddi input p52 = setting not required pm52 = setting not required pmc52 = setting not r equired pfce52 = setting not required pfc52 = setting not required ocdm0 (ocdm) = 1
r01uh0015ej0300 rev.3.00 page 139 of 888 sep 30, 2010 v850es/jg3 chapter 4 port functions table 4-15. using port pin as alternate-function pin (3/7) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) sib2 input p53 = setting not required pm53 = setting not required pmc53 = 1 pfce53 = 0 pfc53 = 0 tiq00 input p53 = setting not required pm53 = setting not required pmc53 = 1 pfce53 = 0 pfc53 = 1 krm3 (krm) = 0 kr3 input p53 = setting not required pm53 = setting not required pmc53 = 1 pfce53 = 0 pfc53 = 1 tq0tig0, tq0tig1 (tq0ioc1) = 0, tq0ees0, tq0ees1 (tq0ioc2) = 0, tq0ets0, tq0ets1 (tq0ioc2) = 0 toq00 input p53 = setting not required pm53 = setting not required pmc53 = 1 pfce53 = 1 pfc53 = 0 rtp03 output p53 = setting not required pm53 = setting not required pmc53 = 1 pfce53 = 1 pfc53 = 1 p53 ddo output p53 = setting not required pm53 = setting not required pmc53 = setting not r equired pfce53 = setting not required pfc53 = setting not required ocdm0 (ocdm) = 1 sob2 output p54 = setting not required pm54 = setting not required pmc54 = 1 pfce54 = 0 pfc54 = 0 kr4 input p54 = setting not required pm54 = setting not required pmc54 = 1 pfce54 = 0 pfc54 = 1 rtp04 output p54 = setting not required pm54 = setting not required pmc54 = 1 pfce54 = 1 pfc54 = 1 p54 dck input p54 = setting not required pm54 = setting not required pmc54 = setting not r equired pfce54 = setting not required pfc54 = setting not required ocdm0 (ocdm) = 1 sckb2 i/o p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 0 pfc55 = 0 kr5 input p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 0 pfc55 = 1 rtp05 output p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 1 pfc55 = 1 p55 dms input p55 = setting not required pm55 = setting not required pmc55 = setting not r equired pfce55 = setting not required pfc55 = setting not required ocdm0 (ocdm) = 1 p70 ani0 input p70 = setting not required pm70 = 1 ? ? ? p71 ani1 input p71 = setting not required pm71 = 1 ? ? ? p72 ani2 input p72 = setting not required pm72 = 1 ? ? ? p73 ani3 input p73 = setting not required pm73 = 1 ? ? ? p74 ani4 input p74 = setting not required pm74 = 1 ? ? ? p75 ani5 input p75 = setting not required pm75 = 1 ? ? ? p76 ani6 input p76 = setting not required pm76 = 1 ? ? ? p77 ani7 input p77 = setting not required pm77 = 1 ? ? ? p78 ani8 input p78 = setting not required pm78 = 1 ? ? ? p79 ani9 input p79 = setting not required pm79 = 1 ? ? ? p710 ani10 input p710 = setting not required pm710 = 1 ? ? ? p711 ani11 input p711 = setting not required pm711 = 1 ? ? ?
r01uh0015ej0300 rev.3.00 page 140 of 888 sep 30, 2010 v850es/jg3 chapter 4 port functions table 4-15. using port pin as alternate-function pin (4/7) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) a0 output p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 0 pfc90 = 0 note 1 kr6 input p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 0 pfc90 = 1 txda1 output p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 1 pfc90 = 0 p90 sda02 i/o p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 1 pfc90 = 1 pf90 (pf9) = 1 a1 output p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 0 pfc91 = 0 note 1 kr7 input p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 0 pfc91 = 1 rxda1/ kr7 note 2 input p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 1 pfc91 = 0 p91 scl02 i/o p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 1 pfc91 = 1 pf91 (pf9) = 1 a2 output p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 0 pfc92 = 0 note 1 tip41 input p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 0 pfc92 = 1 p92 top41 output p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 1 pfc92 = 0 a3 output p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 0 pfc93 = 0 note 1 tip40 input p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 0 pfc93 = 1 p93 top40 output p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 1 pfc93 = 0 a4 output p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 0 pfc94 = 0 note 1 tip31 input p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 0 pfc94 = 1 p94 top31 output p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 1 pfc94 = 0 a5 output p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 0 pfc95 = 0 note 1 tip30 input p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 0 pfc95 = 1 p95 top30 output p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 1 pfc95 = 0 a6 output p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 0 pfc96 = 0 note 1 tip21 input p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 1 pfc96 = 0 p96 top21 output p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 1 pfc96 = 1 notes 1. when setting pins a0 to a15 as the alternate function, set all 16 bits of the pmc9 register to ffffh at once. 2. the rxda1 and kr7 pins must not be used at the same time. when using the rxda1 pin, do not use the kr7 pin. when using the k r7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear the pfce91 bit to 0).
r01uh0015ej0300 rev.3.00 page 141 of 888 sep 30, 2010 v850es/jg3 chapter 4 port functions table 4-15. using port pin as alternate-function pin (5/7) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) a7 output p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 0 pfc97 = 0 note sib1 input p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 0 pfc97 = 1 tip20 input p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 1 pfc97 = 0 p97 top20 output p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 1 pfc97 = 1 a8 output p98 = setting not required pm98 = setting not required pmc98 = 1 ? pfc98 = 0 note p98 sob1 output p98 = setting not required pm98 = setting not required pmc98 = 1 ? pfc98 = 1 a9 output p99 = setting not required pm99 = setting not required pmc99 = 1 ? pfc99 = 0 note p99 sckb1 i/o p99 = setting not required pm99 = setting not required pmc99 = 1 ? pfc99 = 1 a10 output p910 = setting not required pm910 = setting not required pmc910 = 1 ? pfc910 = 0 note p910 sib3 input p910 = setting not required pm910 = setting not required pmc910 = 1 ? pfc910 = 1 a11 output p911 = setting not required pm911 = setting not required pmc911 = 1 ? pfc911 = 0 note p911 sob3 output p911 = setting not required pm911 = setting not required pmc911 = 1 ? pfc911 = 1 a12 output p912 = setting not required pm912 = setting not required pmc912 = 1 ? pfc912 = 0 note p912 sckb3 i/o p912 = setting not required pm912 = setting not required pmc912 = 1 ? pfc912 = 1 a13 output p913 = setting not required pm913 = setting not required pmc913 = 1 ? pfc913 = 0 note p913 intp4 input p913 = setting not required pm913 = setting not required pmc913 = 1 ? pfc913 = 1 a14 output p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 0 pfc914 = 0 note intp5 input p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 0 pfc914 = 1 tip51 input p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 1 pfc914 = 0 p914 top51 output p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 1 pfc914 = 1 a15 output p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 0 pfc915 = 0 note intp6 input p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 0 pfc915 = 1 tip50 input p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 1 pfc915 = 0 p915 top50 output p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 1 pfc915 = 1 note when setting pins a0 to a15 as the alternate function, se t all 16 bits of the pmc9 register to ffffh at once.
r01uh0015ej0300 rev.3.00 page 142 of 888 sep 30, 2010 v850es/jg3 chapter 4 port functions table 4-15. using port pin as alternate-function pin (6/7) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) pcm0 wait input pcm0 = setting not required pmcm0 = setting not required pmccm0 = 1 ? ? pcm1 clkout output pcm1 = setting not required pmcm1 = setting not required pmccm1 = 1 ? ? pcm2 hldak output pcm2 = setting not required pmcm2 = setting not required pmccm2 = 1 ? ? pcm3 hldrq input pcm3 = setting not required pmcm3 = setting not required pmccm3 = 1 ? ? pct0 wr0 output pct0 = setting not required pmct0 = setting not required pmcct0 = 1 ? ? pct1 wr1 output pct1 = setting not required pmct1 = setting not required pmcct1 = 1 ? ? pct4 rd output pct4 = setting not required pmct4 = setting not required pmcct4 = 1 ? ? pct6 astb output pct6 = setting not required pmct6 = setting not required pmcct6 = 1 ? ? pdh0 a16 output pdh0 = setting not required pmdh0 = setting not required pmcdh0 = 1 ? ? pdh1 a17 output pdh1 = setting not required pmdh1 = setting not required pmcdh1 = 1 ? ? pdh2 a18 output pdh2 = setting not required pmdh2 = setting not required pmcdh2 = 1 ? ? pdh3 a19 output pdh3 = setting not required pmdh3 = setting not required pmcdh3 = 1 ? ? pdh4 a20 output pdh4 = setting not required pmdh4 = setting not required pmcdh4 = 1 ? ? pdh5 a21 output pdh5 = setting not required pmdh5 = setting not required pmcdh5 = 1 ? ? pdl0 ad0 i/o pdl0 = setting not required pmdl0 = setting not required pmcdl0 = 1 ? ? pdl1 ad1 i/o pdl1 = setting not required pmdl1 = setting not required pmcdl1 = 1 ? ? pdl2 ad2 i/o pdl2 = setting not required pmdl2 = setting not required pmcdl2 = 1 ? ? pdl3 ad3 i/o pdl3 = setting not required pmdl3 = setting not required pmcdl3 = 1 ? ? pdl4 ad4 i/o pdl4 = setting not required pmdl4 = setting not required pmcdl4 = 1 ? ? ad5 i/o pdl5 = setting not required pmdl5 = setting not required pmcdl5 = 1 ? ? pdl5 flmd1 note input pdl5 = setting not required pmdl5 = setting not required pmcdl5 = setting not r equired ? ? pdl6 ad6 i/o pdl6 = setting not required pmdl6 = setting not required pmcdl6 = 1 ? ? pdl7 ad7 i/o pdl7 = setting not required pmdl7 = setting not required pmcdl7 = 1 ? ? note since this pin is set in the flash memory programming mode, it does not need to be manipulated using the port control register . for details, see chapter 27 flash memory .
r01uh0015ej0300 rev.3.00 page 143 of 888 sep 30, 2010 v850es/jg3 chapter 4 port functions table 4-15. using port pin as alternate-function pin (7/7) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) pdl8 ad8 i/o pdl8 = setting not required pmdl8 = setting not required pmcdl8 = 1 ? ? pdl9 ad9 i/o pdl9 = setting not required pmdl9 = setting not required pmcdl9 = 1 ? ? pdl10 ad10 i/o pdl10 = setting not required pmdl10 = setting not required pmcdl10 = 1 ? ? pdl11 ad11 i/o pdl11 = setting not required pmdl11 = setting not required pmcdl11 = 1 ? ? pdl12 ad12 i/o pdl12 = setting not required pmdl12 = setting not required pmcdl12 = 1 ? ? pdl13 ad13 i/o pdl13 = setting not required pmdl13 = setting not required pmcdl13 = 1 ? ? pdl14 ad14 i/o pdl14 = setting not required pmdl14 = setting not required pmcdl14 = 1 ? ? pdl15 ad15 i/o pdl15 = setting not required pmdl15 = setting not required pmcdl15 = 1 ? ?
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 144 of 870 sep 30, 2010 4.6 cautions 4.6.1 cautions on setting port pins (1) in the v850es/jg3, the general-purpose port function an d several peripheral function i/o pin share a pin. to switch between the general-purpose port (port mode) and the perip heral function i/o pin (alternate-function mode), set by the pmcn register. in regards to this regi ster setting sequence, note with caution the following. (a) cautions on switching from por t mode to alternate-function mode to switch from the port mode to alternat e-function mode in the following order. <1> set the pfn register note : n-ch open-drain setting <2> set the pfcn and pfcen regist ers: alternate-function selection <3> set the corresponding bit of the pmcn regist er to 1: switch to alternate-function mode if the pmcn register is set first, not e with caution that, at that moment or depending on the change of the pin states in accordance with the setti ng of the pfn, pfcn, and pfcen re gisters, unexpected operations may occur. a concrete example is shown as example below. note no-ch open-drain output pin only caution regardless of the port mode /alternate-function mode, the pn re gister is read and written as follows. ? pn register read: read the port output latch value (when pmn.pmnm bit = 0), or read the pin states (pmn.pmnm bit = 1). ? pn register write: write to the port output latch [example] scl01 pin setting example the scl01 pin is used alternately with the p41/sob0 pin. select the valid pin functions with the pmc4, pfc4, and pf4 registers. pmc41 bit pfc41 bit pf41 bit valid pin functions 0 don?t care 1 p41 (in output port mode, n-ch open-drain output) 0 1 sob0 output (n-ch open-drain output) 1 1 1 scl01 i/o (n-ch open-drain output)
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 145 of 870 sep 30, 2010 the order of setting in which malfunction may occur on switching from the p41 pin to the scl01 pin are shown below. setting order setting contents pin states pin level <1> initial value (pmc41 bit = 0, pfc41 bit = 0, pf41 bit = 0) port mode (input) hi-z <2> pmc41 bit 1 sob0 output low level (high level depending on the csib0 setting) <3> pfc41 bit 1 scl01 i/o high level (cmos output) <4> pf41 bit 1 scl01 i/o hi-z (n-ch open-drain output) in <2>, i 2 c communication may be affected since the altern ate-function sob0 out put is output to the pin. in the cmos output period of <2> or <3>, unnecessary current may be generated. (b) cautions on alternate-function mode (input) the input signal to the alternate-function block is low level when the pmcn.pmcnm bit is 0 due to the and output of the pmcn register set va lue and the pin level. thus, depending on the port setting and alternate- function operation enable timing, unexpected operations ma y occur. therefore, switch between the port mode and alternate-function mode in the following sequence. ? to switch from port mode to alternate-function mode (input) set the pins to the alternate-function mode using the pmcn register and then enab le the alternate-function operation. ? to switch from alternate-function mode (input) to port mode stop the alternate-function operation and then switch the pins to the port mode. the concrete examples are show n as example 1 and example 2. [example 1] switch from general-purpose por t (p02) to external interrupt pin (nmi) when the p02/nmi pin is pulled up as shown in figure 4-33 and the rising edge is specified in the nmi pin edge detection setting, even though high level is input continuously to the nmi pin during switching from the p02 pin to the an nmi pin (pmc02 bit = 0 1), this is detected as a rising edge as if the low level changed to high level, and an nmi interrupt occurs. to avoid it, set the nmi pin?s valid edge after switching from the p02 pin to the nmi pin.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 146 of 870 sep 30, 2010 figure 4-33. example of switching from p02 to nmi (incorrect) pmc0 nmi interrupt occurrence 76543 2 p02/nmi 3 v 10 0 1 pmc0m bit = 0: port mode pmc0m bit = 1: alternate-function mode rising edge detector pmc02 bit = 0: low level pmc02 bit = 1: high level remark m = 0 to 7 [example 2] switch from external pin (nmi) to general-purpose port (p02) when the p02/nmi pin is pulled up as shown in figure 4-34 and the falling edge is specified in the nmi pin edge detection setting, even though high le vel is input continuously to the nmi pin at switching from the nmi pin to the p02 pin (pmc02 bit = 1 0), this is detected as falling edge as if high level changed to low level, and nmi interrupt occurs. to avoid this, set the nmi pin edge detection as ?no edge detected? before switching to the p02 pin. figure 4-34. example of switching from nmi to p02 (incorrect) pmc0 76543 2 p02/nmi 3 v 10 nmi interrupt occurrence 1 0 pmc0m bit = 0: port mode pmc0m bit = 1: alternate-function mode falling edge detector pmc02 bit = 1: high level pmc02 bit = 0: low level remark m = 0 to 7 (2) in port mode, the pfn.pfnm bit is valid only in the output mode (pmn.pmnm bit = 0). in the input mode (pmnm bit = 1), the value of the pfnm bit is not reflected in the buffer.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 147 of 870 sep 30, 2010 4.6.2 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. when p90 pin is an output port, p91 to p97 pins are input ports (all pin status es are high level), and the value of the port latch is 00h, if the output of p90 pin is changed from low level to high level via a bit manipulation instruction, the va lue of the port latch is ffh. explanation: the targets of writing to and reading from the pn regi ster of a port whose pmnm bit is 1 are the output latch and pin status, respectively. a bit manipulation instruction is executed in the following order in the v850es/jg3. <1> the pn register is read in 8-bit units. <2> the targeted one bit is manipulated. <3> the pn register is written in 8-bit units. in step <1>, the value of the output latch (0) of p90 pin, which is an output port, is read, while the pin statuses of p91 to p97 pins, which are input ports, are read. if the pi n statuses of p91 to p97 pins are high level at this time, the read value is feh. the value is changed to ffh by the manipulation in <2>. ffh is written to the output la tch by the manipulation in <3>. figure 4-35. bit manipula tion instruction (p90 pin) low-level output bit manipulation instruction (set1 0, p9l[r0]) is executed for p90 bit. pin status: high level p90 p91 to p97 port 9l latch 00000000 high-level output pin status: high level p90 p91 to p97 port 9l latch 11111111 bit manipulation instruction for p90 bit <1> p9l register is read in 8-bit units. ? in the case of p90, an output port, the value of the port latch (0) is read. ? in the case of p91 to p97, input ports, the pin status (1) is read. <2> set (1) p90 bit. <3> write the results of <2> to the output latch of p9l register in 8-bit units.
v850es/jg3 chaptrer 4 port functions r01uh0015ej0300 rev.3.00 page 148 of 870 sep 30, 2010 4.6.3 cautions on on-chip debug pins the drst, dck, dms, ddi, and ddo pins are on-chip debug pins. after reset by the reset pin, the p05/in tp2/drst pin is initialized to function as an on-chip debug pin (drst). if a high level is input to the drst pin at this time, the on-ch ip debug mode is set, and the dck, dms, ddi, and ddo pins can be used. the following action must be taken if on-chip debugging is not used. ? clear the ocdm0 bit of the ocdm register (special register) (0) at this time, fix the p05/intp2/drst pin to low level from when reset by the reset pin is released until the above action is taken. if a high level is input to the drst pin before the above acti on is taken, it may cause a malfunction (cpu deadlock). handle the p05 pin with the utmost care. caution after reset by the wdt2res signal, clock m onitor (clm), or low-voltage detector (lvi), the p05/intp2/drst pin is not initialized to function as an on-chip debug pin (drst). the ocdm register holds the current value. 4.6.4 cautions on p05/intp2/drst pin the p05/intp2/drst pin has an internal pull-down resistor (30 k typ.). after a reset by the reset pin, a pull-down resistor is connected. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0). 4.6.5 cautions on p53 pin when power is turned on when the power is turned on, the following pin may output an undefined level temporarily, even during reset. ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin 4.6.6 hysteresis characteristics in port mode, the following port pins do not have hysteresis characteristics. p02 to p06 p31 to p35, p38, p39 p40 to p42 p50 to p55 p90 to p97, p99, p910, p912 to p915
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 149 of 870 sep 30, 2010 chapter 5 bus control function the v850es/jg3 is provided with an external bus interface function by which external memories such as rom and ram, and i/o can be connected. 5.1 features output is selectable from a multip lexed bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles. 8-bit/16-bit data bus selectable wait function ? programmable wait function of up to 7 states ? external wait function using wait pin idle state function bus hold function up to 4 mb of physical memory connectable
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 150 of 870 sep 30, 2010 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins (multiplexed bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus a16 to a21 pdh0 to pdh5 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control table 5-2. external control pins (separate bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o data bus a0 to a15 p90 to p915 output address bus a16 to a21 pdh0 to pdh5 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal hldrq pcm3 input hldak pcm2 output bus hold control 5.2.1 pin status when internal rom, internal ram, or on-chip peripheral i/o is accessed when the internal rom, internal ram, or on-chip peripheral i/o are accessed, the status of each pin is as follows. table 5-3. pin statuses when in ternal rom, internal ram, or on-chip peripheral i/o is accessed separate bus mode multiplexed bus mode address bus (a21 to a0) undefined a ddress bus (a21 to a16) undefined data bus (ad15 to ad0) hi-z address/data bus (ad15 to ad0) undefined control signal inactive control signal inactive caution when a write access is perfo rmed to the internal rom area, addr ess, data, and control signals are activated in the same way as access to the external memory area. 5.2.2 pin status in each operation mode for the pin status of the v850 es/jg3 in each operation mode, see 2.2 pin states .
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 151 of 870 sep 30, 2010 5.3 memory block function the 16 mb external memory space is divided into memory blocks of (lower) 2 mb, 2 mb, 4 mb, and 8 mb. the programmable wait function and bus cycl e operation mode for each of these blocks can be indep endently controlled in one-block units. figure 5-1. data memory map: physical address (64 kb) use prohibited memory block 3 (8 mb) internal rom area note 2 (1 mb) external memory area note 1 (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) memory block 2 (4 mb) memory block 1 (2 mb) memory block 0 (2 mb) 03ffffffh 03ff0000h 03feffffh 01000000h 00ffffffh 00800000h 007fffffh 00400000h 003fffffh 00200000h 001fffffh 00000000h 03ffffffh 03fff000h 03ffefffh 001fffffh 00100000h 000fffffh 00000000h 03ff0000h external memory area note 1 notes 1. the v850es/jg3 has 22 address pins, and the external memory area is viewed as a repetition of an image of 4 mb. 2. this area is an external memory area in the case of a data write access.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 152 of 870 sep 30, 2010 5.4 external bus interface mode control function the v850es/jg3 includes the following two external bus interface modes. ? multiplexed bus mode ? separate bus mode these two modes can be selected by using the eximc register. (1) external bus interface mode control register (eximc) the eximc register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 multiplexed bus mode separate bus mode smsel 0 1 mode selection eximc 0 0 0 0 0 0 smsel after reset: 00h r/w address: ffffffbeh caution set the eximc register fr om the internal rom or internal ram area before making an external access. after setting the eximc register, be sure to insert a nop instruction.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 153 of 870 sep 30, 2010 5.5 bus access 5.5.1 number of clocks for access the following table shows the number of basic clocks required for accessing each resource. area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 note 1 3 + n note 2 instruction fetch (branch) 2 2 note 1 3 + n note 2 operand data access 3 1 3 + n note 2 notes 1. increases by 1 if a conflict with a data access occurs. 2. 2 + n clocks (n: number of wait states ) when the separate bus mode is selected. remark unit: clocks/access 5.5.2 bus size setting function each external memory area selected by memory block can be set by using the bsc register. however, the bus size can be set to 8 bits and 16 bits only. the external memory area of the v850es/jg3 is selected by memory blocks 0 to 3. (1) bus size configuration register (bsc) the bsc register can be read or written in 16-bit units. reset sets this register to 5555h. caution write to the bsc register after reset, and th en do not change the set values. also, do not access an external memory area until the initial se ttings of the bsc register are complete. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits bsc 1 bs30 0 0 1 bs20 0 0 1 bs10 0 0 1 bs00 8 9 10 11 12 13 data bus width of csn space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block 2 memory block 1 caution be sure to set bits 14, 12, 10, and 8 to ?1?, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to ?0?.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 154 of 870 sep 30, 2010 5.5.3 access by bus size the v850es/jg3 accesses the on-chip peripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is described below. all data is accessed starting from the lower side. the v850es/jg3 supports only the little-endian format. figure 5-2. little-endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) data space the v850es/jg3 has an address misalign function. with this function, data can be placed at all addresses, re gardless of the format of the data (word data or halfword data). however, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (a) halfword-length data access a byte-length bus cycle is generated twice if the least significant bit of the address is 1. (b) word-length data access (i) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) a halfword-length bus cycle is generated twic e if the lower 2 bits of the address are 10.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 155 of 870 sep 30, 2010 (2) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 156 of 870 sep 30, 2010 (3) halfword access (16 bits) (a) with 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus first access second access 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 halfword data external data bus 2n address halfword data external data bus address 2n + 1 (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus first access second access 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 157 of 870 sep 30, 2010 (4) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 158 of 870 sep 30, 2010 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 159 of 870 sep 30, 2010 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 160 of 870 sep 30, 2010 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access word data external data bus address word data external data bus address word data external data bus address word data external data bus address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 161 of 870 sep 30, 2010 5.6 wait function 5.6.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each memory block space. the number of wait states can be programmed by using the dwc0 regi ster . immediately after system reset, 7 data wait states are inserted for all the blocks. the dwc0 register can be read or written in 16-bit units. reset sets this register to 7777h. cautions 1. the internal rom and internal ram areas are not subject to programmable wait, and are always accessed without a wait state. the on-ch ip peripheral i/o area is also not subject to programmable wait, and only wa it control from each periphe ral function is performed. 2. write to the dwc0 register after reset, and then do not change the set values. also, do not access an external memory area until the initial se ttings of the dwc0 register are complete. 3. when the v850es/jg3 is used in separate bus mode and operated at f xx > 20 mhz, be sure to insert one or more waits. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 none setting prohibited dwc0 dw32 dw12 dw31 dw11 dw30 dw10 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 number of wait states inserted in memory block n space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block 2 memory block 1 multiplexed bus separate bus f xx 20 mhz f xx > 20 mhz caution be sure to clear bits 15, 11, 7, and 3 to ?0?.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 162 of 870 sep 30, 2010 5.6.2 external wait function to synchronize an extremely slow external memory, i/o, or asynchronous system, any num ber of wait states can be inserted in the bus cycle by using the external wait pin (wait). when the pcm0 pin is set to alternate function, the external wait function is enabled. access to each area of the internal rom, internal ram, and on-chip peripheral i/o is not subject to control by the external wait function, in the same man ner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle in the multiple xed bus mode. in the separate bus mode, it is sampled at the rising edge of the clock immediately after the t1 and tw states of the bus cycle. if the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 163 of 870 sep 30, 2010 5.6.3 relationship between programm able wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the programmable wait and the wa it pin signal is as illustrat ed below, three wait states will be inserted in the bus cycle. figure 5-3. inserting wait example (a) multiplexed bus clkout t1 t2 tw tw tw t3 wait pin wait via wait pin programmable wait wait control (b) separate bus t1 tw tw tw t2 clkout wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 164 of 870 sep 30, 2010 5.6.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be se t by using the awc register. address wait insertion is set for each memory block area (memory blocks 0 to 3). if an address setup wait is inserted, it s eems that the high-clock period of the t1 state is extended by 1 clock. if an address hold wait is inserted, it seems that the low-cl ock period of the t1 state is extended by 1 clock. (1) address wait control register (awc) the awc register can be read or written in 16-bit units. reset sets this register to ffffh. cautions 1. address setup wait and address hold wait cycles are not inserted when the internal rom area, internal ram area, and on-chip peripheral i/o areas are accessed. 2. write to the awc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the awc register are complete. 3. when the v850es/jg3 is operated at f xx > 20 mhz, be sure to insert the address hold wait and the address setup wait. after reset: ffffh r/w address: fffff488h 1 ahw3 awc 1 asw3 1 ahw2 1 asw2 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted setting prohibited inserted specifies insertion of address setup wait (n = 0 to 3) memory block 0 memory block 3 memory block 2 memory block 1 f xx 20 mhz f xx > 20 mhz ahwn 0 1 not inserted inserted setting prohibited inserted specifies insertion of address hold wait (n = 0 to 3) f xx 20 mhz f xx > 20 mhz caution be sure to set bits 15 to 8 to ?1?.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 165 of 870 sep 30, 2010 5.7 idle state insertion function to facilitate interfacing with low-speed memories, one idle state (ti) can be insert ed after the t3 state in the bus cycle that is executed for each space selected as the memory bloc k in the multiplex address/data bus mode. in the separate bus mode, one idle state (ti) can be inserted a fter the t2 state. by inserting an idle state, the data output float delay time of the memory can be secured during read access (an id le state cannot be inserted during write access). whether the idle state is to be inserted c an be programmed by using the bcc register. an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control register (bcc) the bcc register can be read or written in 16-bit units. reset sets this register to aaaah. cautions 1. the internal rom, internal ram, and on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and th en do not change the set values. also, do not access an external memory area until the initial settings of the bcc register are complete. after reset: aaaah r/w address: fffff48ah 1 bc31 bcn1 0 1 not inserted inserted bcc 0 0 1 bc21 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block 2 memory block 1 caution be sure to set bits 15, 13, 11, and 9 to ?1?, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to ?0?.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 166 of 870 sep 30, 2010 5.8 bus hold function 5.8.1 functional outline the hldrq and hldak functions are valid if the pc m2 and pcm3 pins are set to alternate function. when the hldrq pin is asserted (low level), indicating th at another bus master has requested bus mastership, the external address/data bus goes into a hi gh-impedance state and is released (bus hold status). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in the internal rom and internal ram is continued until an on- chip peripheral i/o register or the external memory is accessed. the bus hold status is indicated by assertion of the hldak pin (low leve l). the bus hold function enables the configuration of mult i-processor type systems in which two or more bus masters exist. note that the bus hold request is not ac knowledged during a multiple-access cycle initiated by the bus sizing function or a bit manipulation instruction. status data bus width access type timing at which bus hold request is not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ? ? between read access and write access
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 167 of 870 sep 30, 2010 5.8.2 bus hold procedure the bus hold status transition procedure is shown below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.8.3 operation in power save mode because the internal system clock is stopped in the stop, idle1, and idle2 modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asserted, and the bus hold status is entered. when the hldrq pin is later deas serted, the hldak pin is also deasserted, and the bus hold status is cleared.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 168 of 870 sep 30, 2010 5.9 bus priority bus hold, dma transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. bus hold has the highest priority, followed by dma transfer, operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-4. bus priority priority external bus cycle bus master bus hold external device dma transfer dmac operand data access cpu instruction fetch (branch) cpu high low instruction fetch (successive) cpu
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 169 of 870 sep 30, 2010 5.10 bus timing figure 5-4. multiplexed bus read timing (bus size: 16 bits, 16-bit access) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a21 to a16 astb wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-5. multiplexed bus r ead timing (bus size: 8 bits) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a21 to a16, ad15 to ad8 astb wait ad7 to ad0 rd remark the broken lines indicate high impedance.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 170 of 870 sep 30, 2010 figure 5-6. multiplexed bus write timi ng (bus size: 16 bits, 16-bit access) a1 11 00 11 11 00 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a21 to a16 astb wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active figure 5-7. multiplexed bus wr ite timing (bus size: 8 bits) a1 11 10 11 11 10 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a21 to a16, ad15 to ad8 astb wait ad7 to ad0 wr1, wr0
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 171 of 870 sep 30, 2010 figure 5-8. multiplexed bus hold timing (bus si ze: 16 bits, 16-bit access) t1 a1 undefined a1 a2 t2 t3 ti note th th th th ti note t1 t2 t3 d1 clkout hldrq hldak a21 to a16 astb ad15 to ad0 rd undefined undefined undefined a2 d2 note this idle state (ti) does not de pend on the bcc register settings. remarks 1. see table 2-2 for the pin statuses in the bus hold mode. 2. the broken lines indicate high impedance.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 172 of 870 sep 30, 2010 figure 5-9. separate bus read timi ng (bus size: 16 bits, 16-bit access) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a21 to a0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-10. separate bus r ead timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a21 to a0 wait ad7 to ad0 rd remark the broken lines indicate high impedance.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 173 of 870 sep 30, 2010 figure 5-11. separate bus write timi ng (bus size: 16 bits, 16-bit access) t1 a1 11 00 00 00 11 11 11 11 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a21 to a0 wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active remark the broken lines indicate high impedance. figure 5-12. separate bus writ e timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a21 to a0 wait ad7 to ad0 wr1, wr0 11 10 10 10 11 11 11 11 remark the broken lines indicate high impedance.
v850es/jg3 chapter 5 bus control function r01uh0015ej0300 rev.3.00 page 174 of 870 sep 30, 2010 figure 5-13. separate bus hold ti ming (bus size: 8 bits, write) clkout t1 t2 a1 d1 d2 undefined a2 undefined 11 11 10 d3 a3 t1 t2 th ti note ti note th th th t1 t2 hldrq hldak a21 to a0 ad7 to ad0 wr1, wr0 11 10 11 10 11 note this idle state (ti) does not de pend on the bcc register settings. remark the broken lines indicate high impedance. figure 5-14. address wait timing (separate bus read, bus size: 16 bits, 16-bit access) tasw t1 tahw t2 clkout astb a21 to a0 wait ad15 to ad0 rd d1 a1 t1 t2 clkout astb a21 to a0 wait ad15 to ad0 rd d1 a1 remarks 1. tasw (address setup wait): image of hi gh-level width of t1 state expanded. 2. tahw (address hold wait): image of lo w-level width of t1 state expanded. 3. the broken lines indicate high impedance.
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 175 of 870 sep 30, 2010 chapter 6 clock generation function 6.1 overview the following clock generation functions are available. main clock oscillator ? in clock-through mode f x = 2.5 to 10 mhz (f xx = 2.5 to 10 mhz) ? in pll mode f x = 2.5 to 5 mhz ( 4: f xx = 10 to 20 mhz) f x = 2.5 to 4 mhz ( 8: f xx = 20 to 32 mhz) subclock oscillator ? f xt = 32.768 khz multiply ( 4/ 8) function by pll (phase locked loop) ? clock-through mode/pll mode selectable internal oscillator ? f r = 220 khz (typ.) internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) peripheral clock generation clock output function remark f x : main clock oscillation frequency f xx : main clock frequency f xt : subclock frequency f r : internal oscillation clock frequency
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 176 of 870 sep 30, 2010 6.2 configuration figure 6-1. clock generator selector selector note frc bit mfrc bit mck bit ck2 to ck0 bits selpll bit pllon bit cls, ck3 bits stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock watch timer clock timer m clock watch timer clock, watchdog timer 2 clock peripheral clock, watchdog timer 2 clock watchdog timer 2 clock, timer m clock internal system clock prescaler 3 main clock oscillator main clock oscillator stop control rstop bit internal oscillator 1/8 divider xt1 xt2 clkout x1 x2 idle mode pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1,024 f brg = f x /2 to f x /2 12 f xt f xt f xx f x f r f r /8 idle control selector selector note the internal oscillation clock is selected when wa tchdog timer 2 overflows during the oscillation stabilization time. remark f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f brg : watch timer clock frequency f r : internal oscillation clock frequency
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 177 of 870 sep 30, 2010 (1) main clock oscillator the main resonator oscillates the following frequencies (f x ). ? in clock-through mode f x = 2.5 to 10 mhz ? in pll mode f x = 2.5 to 5 mhz ( 4) f x = 2.5 to 4 mhz ( 8) (2) subclock oscillator the sub-resonator oscillates a frequency of 32.768 khz (f xt ). (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscillat or is stopped in the stop mode or w hen the pcc.mck bit = 1 (valid only when the pcc.cls bit = 1). (4) internal oscillator oscillates a frequency (f r ) of 220 khz (typ.). (5) prescaler 1 this prescaler generates the clock (f xx to f xx /1,024) to be supplied to the follo wing on-chip peripheral functions: tmp0 to tmp5, tmq0, tmm0, csib0 to csib4, uarta0 to uarta2, i 2 c00 to i 2 c02, adc, and wdt2 (6) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, rom, and ram blocks, and can be output from the clkout pin. (7) prescaler 3 this circuit divides the clock generated by the main clock oscillator (f x ) to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. for details, see chapter 10 watch timer functions . (8) pll this circuit multiplies the clock generated by the main clock oscillator (f x ) by 4 or 8. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be selected by using the pllctl.selpll bit. whether the clock is multiplied by 4 or 8 is selected by the ckc.ckdiv0 bit, and pll is started or stopped by the pllctl.pllon bit.
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 178 of 870 sep 30, 2010 6.3 registers (1) processor clock control register (pcc) the pcc register is a special register. data can be wri tten to this register only in combination of specific sequences (see 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 03h.
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 179 of 870 sep 30, 2010 frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 main clock oscillator control used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w address: fffff828h main clock operation subclock operation cls note 0 1 status of cpu clock (f cpu ) even if the mck bit is set (1) while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. before setting the mck bit from 0 to 1, stop the on-chip peripheral functions operating with the main clock. when the main clock is stopped and the device is operating with the subclock, clear (0) the mck bit and secure the oscillation stabilization time by software before switching the cpu clock to the main clock or operating the on-chip peripheral functions. ? ? ? < > < > < > f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 note the cls bit is a read-only bit. cautions 1. do not change the cpu clock (by using the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation instruction to ma nipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. remark : don?t care
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 180 of 870 sep 30, 2010 (a) example of setting main clock operation subclock operation <1> ck3 bit 1: use of a bit manipulation instruction is recommended. do not change the ck2 to ck0 bits. <2> subclock operation: read the cls bit to check if s ubclock operation has started. it takes the following time after the ck3 bit is set unt il subclock operation is started. max.: 1/f xt (1/subclock frequency) <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. cautions 1. when stopping the main clock, stop th e pll. also stop the operations of the on-chip peripheral functions operati ng with the main clock. 2. if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied, then change to the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 remark internal system clock (f clk ): clock generated from the main clock (f xx ) by setting bits ck2 to ck0 [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit 1 <2> _check_cls : tst1 4, pcc[r0] -- wait until subclock operation starts. bz _check_cls <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit 1, main clock is stopped. _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. no te that in <2> above, the cls bit is read in a closed loop.
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 181 of 870 sep 30, 2010 (b) example of setting subclock operation main clock operation <1> mck bit 0: main clock starts oscillating <2> insert waits by the program and wait until the oscillation stabilizat ion time of the main clock elapses. <3> ck3 bit 0: use of a bit manipulation instructi on is recommended. do not change the ck2 to ck0 bits. <4> main clock operation: it takes the following time af ter the ck3 bit is set until main clock operation is started. max.: 1/f xt (1/subclock frequency) therefore, insert one no p instruction immediately after setting the ck3 bit to 0 or read the cls bit to check if main clock operation has started. caution enable operation of the on-chip peripheral functions operating with the main clock only after the oscillation of the main clock stabilizes. if their operations are en abled before the lapse of the oscillation stabilization time, a malfunction may occur. [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _start_main_osc : st.b r0, prcmd[r0] -- release of protection of special registers clr1 6, pcc[r0] -- main clock starts oscillating. <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time. _wait_ost : nop nop nop addi -1, r11, r11 cmp r0, r11 bne _wait_ost <3> st.b r0, prcmd[r0] clr1 3, pcc[r0] -- ck3 0 <4> _check_cls : tst1 4, pcc[r0] -- wait until main clock operation starts. bnz _check_cls _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. no te that in <4> above, the cls bit is read in a closed loop.
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 182 of 870 sep 30, 2010 (2) internal oscillation mode register (rcm) the rcm register is an 8-bit register that sets the operation mode of the internal oscillator. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 rcm 0 0 0 00 0 rstop internal oscillator oscillation internal oscillator stopped rstop 0 1 oscillation/stop of internal oscillator after reset: 00h r/w address: fffff80ch < > cautions 1. the internal oscilla tor cannot be stopped while the cpu is operating on the internal oscillation clock (ccls.cclsf bit = 1). do not set the rstop bit to 1. 2. the internal oscillator o scillates if the ccls.cclsf bit is set to 1 (when wdt overflow occurs during oscillation stabilizat ion) even when the rstop bit is set to 1. at this time, the rstop bit remains being set to 1. (3) cpu operation clock status register (ccls) the ccls register indicates the stat us of the cpu operation clock. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 0 ccls 0 0 0 0 0 0 cclsf after reset: 00h note r address: fffff82eh operating on main clock (f x ) or subclock (f xt ). operating on internal oscillation clock (f r ). cclsf 0 1 cpu operation clock status note if wdt overflow occurs during oscillation stabilization after a reset is releas ed, the cclsf bit is set to 1 and the reset value is 01h.
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 183 of 870 sep 30, 2010 6.4 operation 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock pcc register clk bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 register setting and operation status target clock during reset during oscillation stabilization time count halt mode idle1, idle2 mode stop mode subclock mode sub-idle mode subclock mode sub-idle mode main clock oscillator (f x ) subclock oscillator (f xt ) cpu clock (f cpu ) internal system clock (f clk ) main clock (in pll mode, f xx ) note peripheral clock (f xx to f xx /1,024) wt clock (main) wt clock (sub) wdt2 clock (internal oscillation) wdt2 clock (main) wdt2 clock (sub) note lockup time remark : operable : stopped 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the pcc.ck3 to pcc.ck0 bits. the clkout pin functions alternately as the pcm1 pin and functions as a clock out put pin if so specif ied by the control register of port cm. the status of the clkout pin is the same as the internal system clo ck in table 6-1 and the pin can output the clock when it is in the operable status. it outputs a low level in the stopped status. however, t he clkout pin is in the port mode (pcm1 pin: input mode) after reset and until it is set in the output mode. therefore, t he status of the pin is hi-z.
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 184 of 870 sep 30, 2010 6.5 pll function 6.5.1 overview in the v850es/jg3, an operating clock that is 4 or 8 ti mes higher than the oscilla tion frequency output by the pll function or the clock-through mode can be selected as the operating clock of the cpu and on-chip peripheral functions. when pll function is used ( 4): input clock = 2.5 to 5 mhz (output: 10 to 20 mhz) when pll function is used ( 8): input clock = 2.5 to 4 mhz (output: 20 to 32 mhz) clock-through mode: input clock = 2.5 to 10 mhz (output: 2.5 to 10 mhz) 6.5.2 registers (1) pll control register (pllctl) the pllctl register is an 8-bit regi ster that controls the pll function. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. 0 pllctl 0 0 0 00 selpll pllon pll stopped pll operating (after pll operation starts, a lockup time is required for frequency stabilization) pllon 0 1 pll operation stop register clock-through mode pll mode selpll 0 1 cpu operation clock selection register after reset: 01h r/w address: fffff82ch < > < > cautions 1. when the pllon bit is cleared to 0, the selpll bit is automatically clear ed to 0 (clock- through mode). 2. the selpll bit can be set to 1 only when the pll clock frequency is stabilized. if not (unlocked), ?0? is written to the sel pll bit if data is written to it.
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 185 of 870 sep 30, 2010 (2) clock control register (ckc) the ckc register is a special register. data can be wri tten to this register only in a combination of specific sequence (see 3.4.7 special registers ). the ckc register controls the inte rnal system clock in the pll mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 0ah. 0 ckc 0 0 0 1 0 1 ckdiv0 after reset: 0ah r/w address: fffff822h f xx = 4 f x (f x = 2.5 to 5.0 mhz) f xx = 8 f x (f x = 2.5 to 4.0 mhz) ckdiv0 0 1 internal system clock (f xx ) in pll mode cautions 1. the pll mode cannot be used at f x = 5.0 to 10.0 mhz. 2. before changing the multip lication factor between 4 and 8 by using the ckc register, set the clock-through mode and stop the pll. 3. be sure to set bits 3 and 1 to ?1 ? and clear bits 7 to 4 and 2 to ?0?. remark both the cpu clock and peripheral clock are divid ed by the ckc register, but only the cpu clock is divided by the pcc register.
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 186 of 870 sep 30, 2010 (3) lock register (lockr) phase lock occurs at a given frequency following power application or immediately after the stop mode is released, and the time required for stabilization is the lo ckup time (frequency stabilization time). this state until stabilization is called the lockup status, and the stabilized state is called the locked status. the lockr register includes a lock bit that re flects the pll frequency stabilization status. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 0 lockr 0 0 0 00 0 lock locked status unlocked status lock 0 1 pll lock status check after reset: 00h r address: fffff824h < > caution the lock register does not reflect the lock status of the p ll in real time. the set/clear conditions are as follows. [set conditions] ? upon system reset note ? in idle2 or stop mode ? upon setting of pll stop (clearing of pllctl.pllon bit to 0) ? upon stopping main clock and using cpu with subc lock (setting of pcc.ck3 bit to 1 and setting of pcc.mck bit to 1) note this register is set to 01h by reset and cleared to 00h after the reset has been released and the oscillation stabilization time has elapsed. [clear conditions] ? upon overflow of oscillation stabilization time fo llowing reset release (osts register default time (see 21.2 (3) oscillation stabilization time select register (osts) )) ? upon oscillation stabilization timer overflow (tim e set by osts register) following stop mode release, when the stop mode was set in the pll operating status ? upon pll lockup time timer overflow (time set by plls register) when the pllctl.pllon bit is changed from 0 to 1 ? after the setup time inserted upon release of the id le2 mode is released (time set by the osts register) when the idle2 mode is set during pll operation.
v850es/jg3 chapter 6 cl ock generation function r01uh0015ej0300 rev.3.00 page 187 of 870 sep 30, 2010 (4) pll lockup time specification register (plls) the plls register is an 8-bit register used to select the pll lockup time when the pllctl.pllon bit is changed from 0 to 1. this register can be read or written in 8-bit units. reset sets this register to 03h. 0 2 10 /f x 2 11 f x 2 12 /f x 2 13 /f x (default value) plls1 0 0 1 1 plls0 0 1 0 1 selection of pll lockup time plls 0 0 0 0 0 plls1 plls0 after reset: 03h r/w address: fffff6c1h cautions 1. set so that the lockup time is 800 s or longer. 2. do not change the plls regi ster setting during the lockup period. 6.5.3 usage (1) when pll is used ? after the reset signal has been released, the pll o perates (pllctl.pllon bit = 1), but because the default mode is the clock-through mode (pllctl.selpll bi t = 0), select the pll mode (selpll bit = 1). ? to enable pll operation, first set the pllon bit to 1, and then set the selpll bit to 1 after the lockr.lock bit = 0. to stop the pll, first select the clock-throug h mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0). ? the pll stops during transition to the idle2 or stop mode regardless of the setting and is restored from the idle2 or stop mode to the status before transition. the time requir ed for restoration is as follows. (a) when transiting to the idle2 or st op mode from the clock through mode ? stop mode: set the osts register so that the o scillation stabilization time is 1 ms (min.) or longer. ? idle2 mode: set the osts register so that the setup time is 350 s (min.) or longer. (b) when transiting to the idle 2 or stop m ode while remaining in the pll operation mode ? stop mode: set the osts register so that the o scillation stabilization time is 1 ms (min.) or longer. ? idle2 mode: set the osts register so that the setup time is 800 s (min.) or longer. when transiting to the idle1 mode, the pll does not stop. stop the pll if necessary. (2) when pll is not used ? the clock-through mode (selpll bit = 0) is selected a fter the reset signal has been released, but the pll is operating (pllon bit = 1) and must t herefore be stopped (pllon bit = 0).
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 188 of 870 sep 30, 2010 chapter 7 16-bit timer/event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. the v850es/jg3 has nine timer/event counter channels, tmp0 to tmp5. 7.1 overview an outline of tmpn is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 2 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? timer output pins: 2 remark n = 0 to 5 7.2 functions tmpn has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 189 of 870 sep 30, 2010 7.3 configuration tmpn includes the following hardware. table 7-1. configuration of tmpn item configuration timer register 16-bit counter registers tmpn capture/compare registers 0, 1 (tpnccr0, tpnccr1) tmpn counter read buffer register (tpncnt) ccr0, ccr1 buffer registers timer inputs 2 (tipn0 note 1 , tipn1 pins) timer outputs 2 (topn0, topn1 pins) control registers note 2 tmpn control registers 0, 1 (tpnctl0, tpnctl1) tmpn i/o control registers 0 to 2 (tpnioc0 to tpnioc2) tmpn option register 0 (tpnopt0) notes 1. the tipn0 pin functions alternat ely as a capture trigger input signal, external event count input signal, and external trigger input signal. 2. when using the functions of the tip n0, tipn1,topn0, and topn1 pins, see table 4-15 using port pin as alternate-function pin . remark n = 0 to 5 figure 7-1. block diagram of tmpn f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 note 1 , f xx /256 note 2 f xx /128 note 1 , f xx /512 note 2 selector internal bus internal bus topn0 topn1 tipn0 tipn1 selector edge detector ccr0 buffer register ccr1 buffer register tpnccr0 tpnccr1 16-bit counter tpncnt inttpnov inttpncc0 inttpncc1 output controller clear notes 1. tmp0, tmp2, tmp4 2. tmp1, tmp3, tmp5 remark f xx : main clock frequency
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 190 of 870 sep 30, 2010 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tpncnt register. when the tpnctl0.tpnce bit = 0, the valu e of the 16-bit counter is ffffh. if t he tpncnt register is read at this time, 0000h is read. reset sets the tpnce bit to 0. therefor e, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tpnccr0 register is used as a compare regist er, the value written to the tpnccr0 register is transferred to the ccr0 buffer register. when the count va lue of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tpnccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tpnccr1 register is used as a compare regist er, the value written to the tpnccr1 register is transferred to the ccr1 buffer register. when the count va lue of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tpnccr1 register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the tipn0 and tipn1 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the va lid edge by using the tpnioc1 and tpnioc2 registers. (5) output controller this circuit controls the output of the topn0 and topn1 pi ns. the output controller is controlled by the tpnioc0 register. (6) selector this selector selects the count clock for the 16-bit counter. eight types of internal clocks or an external event can be selected as the count clock.
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 191 of 870 sep 30, 2010 7.4 registers the registers that control tmpn are as follows. ? tmpn control register 0 (tpnctl0) ? tmpn control register 1 (tpnctl1) ? tmpn i/o control register 0 (tpnioc0) ? tmpn i/o control register 1 (tpnioc1) ? tmpn i/o control register 2 (tpnioc2) ? tmpn option register 0 (tpnopt0) ? tmpn capture/compare register 0 (tpnccr0) ? tmpn capture/compare register 1 (tpnccr1) ? tmpn counter read buffer register (tpncnt) remarks 1. when using the functions of the tip n0, tipn1,topn0, and topn1 pins, see table 4-15 using port pin as alternate-function pin . 2. n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 192 of 870 sep 30, 2010 (1) tmpn control register 0 (tpnctl0) the tpnctl0 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tpnctl0 register by software. tpnce tmpn operation disabled (tmpn reset asynchronously note ). tmpn operation enabled. tmpn operation started. tpnce 0 1 tmpn operation control tpnctl0 (n = 0 to 5) 0 0 0 0 tpncks2 tpncks1 tpncks0 654321 after reset: 00h r/w address: tp0ctl0 fffff590h, tp1ctl0 fffff5a0h, tp2ctl0 fffff5b0h, tp3ctl0 fffff5c0h, tp4ctl0 fffff5d0h, tp5ctl0 fffff5e0h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 tpncks2 0 0 0 0 1 1 1 1 internal count clock selection n = 0, 2, 4 n = 1, 3, 5 tpncks1 0 0 1 1 0 0 1 1 tpncks0 0 1 0 1 0 1 0 1 note tpn0pt0.tpnovf bit, 16-bit counter, timer output (topn0, topn1 pins) cautions 1. set the tpncks2 to tpncks0 bits when the tpnce bit = 0. when the value of the tpnce bi t is changed from 0 to 1, the tpncks2 to tpncks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency (2) tmpn control register 1 (tpnctl1) the tpnctl1 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h.
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 193 of 870 sep 30, 2010 0 tpnest 0 1 software trigger control tpnctl1 (n = 0 to 5) tpnest tpneee 0 0 tpnmd2 tpnmd1 tpnmd0 <6> <5> 4 3 2 1 after reset: 00h r/w address: tp0ctl1 fffff591h, tp1ctl1 fffff5a1h, tp2ctl1 fffff5b1h, tp3ctl1 fffff5c1h, tp4ctl1 fffff5d1h, tp5ctl1 fffff5e1h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tpnest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tpnest bit as the trigger. disable operation with external event count input. (perform counting with the count clock selected by the tpnctl0.tpnck0 to tpnck2 bits.) tpneee 0 1 count clock selection the tpneee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tpnmd2 0 0 0 0 1 1 1 1 timer mode selection tpnmd1 0 0 1 1 0 0 1 1 tpnmd0 0 1 0 1 0 1 0 1 enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) ? cautions 1. the tpnest bit is valid only in the external trigger pulse output mode or one-shot pulse output mode . in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tpneee bit. 3. set the tpneee and tpnmd2 to tpnmd0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) the operation is not guaranteed when rewriting is performed with the tpnce bit = 1. if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 4. be sure to clear bits 3, 4, and 7 to ?0?.
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 194 of 870 sep 30, 2010 (3) tmpn i/o control register 0 (tpnioc0) the tpnioc0 register is an 8-bit register that controls the timer output (topn0, topn1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnol1 0 1 topn1 pin output level setting note topn1 pin output starts at high level topn1 pin output starts at low level tpnioc0 (n = 0 to 5) 0 0 0 tpnol1 tpnoe1 tpnol0 tpnoe0 6543<2>1 after reset: 00h r/w address: tp0ioc0 fffff592h, tp1ioc0 fffff5a2h, tp2ioc0 fffff5b2h, tp3ioc0 fffff5c2h, tp4ioc0 fffff5d2h, tp5ioc0 fffff5e2h tpnoe1 0 1 topn1 pin output setting timer output disabled ? when tpnol1 bit = 0: low level is output from the topn1 pin ? when tpnol1 bit = 1: high level is output from the topn1 pin tpnol0 0 1 topn0 pin output level setting note topn0 pin output starts at high level topn0 pin output starts at low level tpnoe0 0 1 topn0 pin output setting timer output disabled ? when tpnol0 bit = 0: low level is output from the topn0 pin ? when tpnol0 bit = 1: high level is output from the topn0 pin 7 <0> timer output enabled (a square wave is output from the topn1 pin). timer output enabled (a square wave is output from the topn0 pin). note the output level of t he timer output pin (topnm) specified by the tpnolm bit is shown below (m = 0, 1). tpnce bit topnm output pin 16-bit counter ? when tpnolm bit = 0 tpnce bit topnm output pin 16-bit counter ? when tpnolm bit = 1 cautions 1. rewrite the tpnol1, tpnoe1, tpnol0, and tpnoe0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. even if the tpnolm bit is manipulated when the tpnce and tpnoem bits are 0, the topnm pin output level varies (m = 0, 1).
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 195 of 870 sep 30, 2010 (4) tmpn i/o control register 1 (tpnioc1) the tpnioc1 register is an 8-bit regist er that controls the valid edge of t he capture trigger input signals (tipn0, tipn1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnis3 0 0 1 1 tpnis2 0 1 0 1 capture trigger input signal (tipn1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tpnioc1 (n = 0 to 5) 0 0 0 tpnis3 tpnis2 tpnis1 tpnis0 654321 after reset: 00h r/w address: tp0ioc1 fffff593h, tp1ioc1 fffff5a3h, tp2ioc1 fffff5b3h, tp3ioc1 fffff5c3h, tp4ioc1 fffff5d3h, tp5ioc1 fffff5e3h tpnis1 0 0 1 1 tpnis0 0 1 0 1 capture trigger input signal (tipn0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnis3 to tpnis0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnis3 to tpnis0 bits are valid only in the free- running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible.
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 196 of 870 sep 30, 2010 (5) tmpn i/o control register 2 (tpnioc2) the tpnioc2 register is an 8-bit register that controls the valid edge of the ex ternal event count input signal (tipn0 pin) and external trigger input signal (tipn0 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnees1 0 0 1 1 tpnees0 0 1 0 1 external event count input signal (tipn0 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tpnioc2 (n = 0 to 5) 0 0 0 tpnees1 tpnees0 tpnets1 tpnets0 654321 after reset: 00h r/w address: tp0ioc2 fffff594h, tp1ioc2 fffff5a4h, tp2ioc2 fffff5b4h, tp3ioc2 fffff5c4h, tp4ioc2 fffff5d4h, tp5ioc2 fffff5e4h tpnets1 0 0 1 1 tpnets0 0 1 0 1 external trigger input signal (tipn0 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnees1, tpnees0, tpnets1, and tpnets0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnees1 and tpnees0 bits are valid only when the tpnctl1.tpneee bit = 1 or when the external event count mode (tpnctl1.tpnmd 2 to tpnctl1.tpnmd0 bits = 001) has been set. 3. the tpnets1 and tpnets0 bits are valid only when the external trigger pulse output mode (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 bits = 010) or the one-shot pulse output mode (tpnctl1.tpn md2 to tpnctl1.tpnmd0 = 011) is set.
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 197 of 870 sep 30, 2010 (6) tmpn option register 0 (tpnopt0) the tpnopt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnccs1 0 1 tpnccr1 register capture/compare selection the tpnccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tpnopt0 (n = 0 to 5) 0 tpnccs1 tpnccs0 0 0 0 tpnovf 654321 after reset: 00h r/w address: tp0opt0 fffff595h, tp1opt0 fffff5a5h, tp2opt0 fffff5b5h, tp3opt0 fffff5c5h, tp4opt0 fffff5d5h, tp5opt0 fffff5e5h tpnccs0 0 1 tpnccr0 register capture/compare selection the tpnccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tpnovf set (1) reset (0) tmpn overflow detection flag ? the tpnovf bit is set when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an interrupt request signal (inttpnov) is generated at the same time that the tpnovf bit is set to 1. the inttpnov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tpnovf bit is not cleared even when the tpnovf bit or the tpnopt0 register are read when the tpnovf bit = 1. ? the tpnovf bit can be both read and written, but the tpnovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmpn. overflow occurred tpnovf bit 0 written or tpnctl0.tpnce bit = 0 7 <0> cautions 1. rewrite the tpnccs1 and tpnccs0 bits when the tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mi stakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3, 6, and 7 to ?0?.
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 198 of 870 sep 30, 2010 (7) tmpn capture/compare register 0 (tpnccr0) the tpnccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt 0.tpnccs0 bit. in the pulse width measurement mode, the tpnccr0 register can be used only as a capture register. in an y other mode, this register can be used only as a compare register. the tpnccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tpnccr0 register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tpnccr0 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr0 fffff596h, tp1ccr0 fffff5a6h, tp2ccr0 fffff5b6h, tp3ccr0 fffff5c6h, tp4ccr0 fffff5d6h, tp5ccr0 fffff5e6h 14 0 13 11 9 7 5 3 15 1
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 199 of 870 sep 30, 2010 (a) function as compare register the tpnccr0 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr 0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. if topn0 pin output is enabled at this time, the output of the topn0 pin is inverted. when the tpnccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse out put mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count value ma tches the value of the ccr0 buffer register. (b) function as capture register when the tpnccr0 register is used as a capture register in the free-runn ing timer mode, the count value of the 16-bit counter is stored in the tpn ccr0 register if the valid edge of the capture trigger input pin (tipn0 pin) is detected. in the pulse-width m easurement mode, the count value of t he 16-bit counter is stored in the tpnccr0 register and the 16-bit counter is cleared (0000h) if the valid edg e of the capture trigger input pin (tipn0) is detected. even if the capture operation and read ing the tpnccr0 register conflict, the correct value of the tpnccr0 register can be read. the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 7-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ?
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 200 of 870 sep 30, 2010 (8) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt 0.tpnccs1 bit. in the pulse width measurement mode, the tpnccr1 register can be used only as a capture register. in an y other mode, this register can be used only as a compare register. the tpnccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tpnccr1 register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tpnccr1 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr1 fffff598h, tp1ccr1 fffff5a8h, tp2ccr1 fffff5b8h, tp3ccr1 fffff5c8h, tp4ccr1 fffff5d8h, tp5ccr1 fffff5e8h 14 0 13 11 9 7 5 3 15 1
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 201 of 870 sep 30, 2010 (a) function as compare register the tpnccr1 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr 1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. if topn1 pin output is enabled at this time, the output of the topn1 pin is inverted. (b) function as capture register when the tpnccr1 register is used as a capture register in the free-runn ing timer mode, the count value of the 16-bit counter is stored in the tpn ccr1 register if the valid edge of the capture trigger input pin (tipn1 pin) is detected. in the pulse-width m easurement mode, the count value of t he 16-bit counter is stored in the tpnccr1 register and the 16-bit counter is cleared (0000h) if the valid edg e of the capture trigger input pin (tipn1) is detected. even if the capture operation and read ing the tpnccr1 register conflict, the correct value of the tpnccr1 register can be read. the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 7-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ?
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 202 of 870 sep 30, 2010 (9) tmpn counter read bu ffer register (tpncnt) the tpncnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tpnctl0.tpnce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tpncnt register is cleared to 0000h when the tpnce bit = 0. if the tpncnt register is read at this time, the value of the 16-bit counter (ffffh) is not read, but 0000h is read. the value of the tpncnt register is cleared to 000 0h after reset, as the tpnce bit is cleared to 0. caution accessing the tpncnt register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tpncnt (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r address: tp0cnt fffff59ah, tp1cnt fffff5aah, tp2cnt fffff5bah, tp3cnt fffff5cah, tp4cnt fffff5dah, tp5cnt fffff5eah 14 0 13 11 9 7 5 3 15 1
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 203 of 870 sep 30, 2010 7.5 operation tmpn can perform the following operations. operation tpnctl1.tpnest bit (software trigger bit) tipn0 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count mode, specify that the valid edge of the tipn0 pin c apture trigger input is not detected (by clearing the tpnioc1.tpnis1 and tpnioc1.tpnis0 bits to ?00?). 2. when using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tpnctl1.tpneee bit to 0). remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 204 of 870 sep 30, 2010 7.5.1 interval timer mode (t pnmd2 to tpnmd0 bits = 000) in the interval timer mode, an interrupt request signal (in ttpncc0) is generated at the specified interval if the tpnctl0.tpnce bit is set to 1. a square wave whose half cycle is equal to the interval can be output from the topn0 pin. usually, the tpnccr1 register is not used in the interval timer mode. figure 7-2. configuration of interval timer 16-bit counter output controller ccr0 buffer register tpnce bit tpnccr0 register count clock selection clear match signal topn0 pin inttpncc0 signal remark n = 0 to 5 figure 7-3. basic timing of op eration in interval timer mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 205 of 870 sep 30, 2010 when the tpnce bit is set to 1, the value of the 16-bit coun ter is cleared from ffffh to 0000h in synchronization with the count clock, and the counter starts counting. at this time , the output of the topn0 pin is inverted. additionally, the se t value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the topn0 pin is inverted, and a compare match interrupt request signal (inttpncc0) is generated. the interval can be calculated by the following expression. interval = (set value of tpnccr0 register + 1) count clock cycle remark n = 0 to 5 figure 7-4. register setting for in terval timer mode operation (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0 0/1 note 00 tpnctl1 0, 0, 0: interval timer mode 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count with external event count input signal 000 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest note this bit can be set to 1 only when the interrupt request signals (inttpncc0 and inttpncc1) are masked by the interrupt mask flags (tpnccmk0 and tpnccm k1) and timer output (topn1) is performed at the same time. however, set the tpnccr0 and tpnccr1 registers to the same value (see 7.5.1 (2) (d) operation of tpnccr1 register ).
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 206 of 870 sep 30, 2010 figure 7-4. register setting for in terval timer mode operation (2/2) (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level with operation of topn0 pin disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of output level with operation of topn1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 (d) tmpn counter read bu ffer register (tpncnt) by reading the tpncnt register, the count va lue of the 16-bit counter can be read. (e) tmpn capture/compare register 0 (tpnccr0) if the tpnccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tmpn capture/compare register 1 (tpnccr1) usually, the tpnccr1 register is not used in the inte rval timer mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register. a compare match interrupt request signal (inttpncc1) is generated when the count value of t he 16-bit counter matches the value of the ccr1 buffer register. therefore, mask the interrupt request by using the corresponding interrupt mask flag (tpnccmk1). remarks 1. tmpn i/o control register 1 (tpnioc1), tmpn i/o control register 2 (tpnioc2), and tmpn option register 0 (tpnopt0) are not used in the interval timer mode. 2. n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 207 of 870 sep 30, 2010 (1) interval timer mode operation flow figure 7-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal d 0 d 0 d 0 d 0 <1> <2> tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnccr0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 208 of 870 sep 30, 2010 (2) interval timer mode operation timing (a) operation if tpnccr0 re gister is set to 0000h if the tpnccr0 register is set to 0000h, the inttpncc0 signal is generated at each count clock subsequent to the first count clock, and the out put of the topn0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal 0000h interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 209 of 870 sep 30, 2010 (b) operation if tpnccr0 register is set to ffffh if the tpnccr0 register is set to ffffh, the 16-bit counter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing. the inttpncc0 signal is generated and the output of the topn0 pin is inverted. at this time, an overflow interrupt request signal (inttpnov) is not generated, nor is the overflow flag (tpnopt0.tpnovf bit) set to 1. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 210 of 870 sep 30, 2010 (c) notes on rewriting tpnccr0 register to change the value of the tpnccr0 re gister to a smaller value, stop counting once and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register tpnol0 bit topn0 pin output inttpncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. n = 0 to 5 if the value of the tpnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tpnccr0 register has been rewritten. consequently, the value of t he 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter co unts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttpncc0 signal is generated and the output of the to pn0 pin is inverted. therefore, the inttpncc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?.
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 211 of 870 sep 30, 2010 (d) operation of tpnccr1 register figure 7-6. configuration of tpnccr1 register ccr0 buffer register tpnccr0 register tpnccr1 register ccr1 buffer register topn0 pin inttpncc0 signal topn1 pin inttpncc1 signal 16-bit counter output controller tpnce bit count clock selection clear match signal output controller match signal remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 212 of 870 sep 30, 2010 if the set value of the tpnccr1 register is less than the set value of the tpnccr0 register, the inttpncc1 signal is generated once per cycle. at the same time, the output of the topn1 pin is inverted. the topn1 pin outputs a square wave with the sa me cycle as that output by the topn0 pin. figure 7-7. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal tpnccr1 register topn1 pin output inttpncc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 213 of 870 sep 30, 2010 if the set value of the tpnccr1 register is greater than the set value of the tpnccr0 register, the count value of the 16-bit counter does not match the value of the tpnccr1 register. consequently, the inttpncc1 signal is not generated, nor is the out put of the topn1 pin changed. figure 7-8. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal tpnccr1 register topn1 pin output inttpncc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 214 of 870 sep 30, 2010 7.5.2 external event count mode (tpnmd2 to tpnmd0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tpnctl0.tpnce bit is set to 1, and an interrupt request sig nal (inttpncc0) is generated eac h time the specified number of edges have been counted. the topn0 pin cannot be used. usually, the tpnccr1 register is not us ed in the external event count mode. figure 7-9. configuration in external event count mode 16-bit counter ccr0 buffer register tpnce bit tpnccr0 register edge detector clear match signal inttpncc0 signal tipn0 pin (external event count input) remark n = 0 to 5 figure 7-10. basic timing in external event count mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 0 d 0 d 0 d 0 16-bit counter tpnccr0 register inttpncc0 signal external event count input (tipn0 pin input) d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) remarks 1. this figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. 2. n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 215 of 870 sep 30, 2010 when the tpnce bit is set to 1, the value of the 16-bit c ounter is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count input is dete cted. additionally, the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttpncc0) is generated. the inttpncc0 signal is generated each time the valid edge of the external event count input has been detected (set value of tpnccr0 register + 1) times. figure 7-11. register setting for operati on in external event count mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 0: stop counting 1: enable counting 000 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 00000 tpnctl1 0, 0, 1: external event count mode 001 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest (c) tmpn i/o control register 0 (tpnioc0) 00000 tpnioc0 0: disable topn0 pin output 0: disable topn1 pin output 000 tpnoe1 tpnol0 tpnoe0 tpnol1 (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 216 of 870 sep 30, 2010 figure 7-11. register setting for operati on in external event count mode (2/2) (e) tmpn counter read bu ffer register (tpncnt) the count value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register 0 (tpnccr0) if d 0 is set to the tpnccr0 register, the counter is cleared and a compare match interrupt request signal (inttpncc0) is generated when the number of external event counts reaches (d 0 + 1). (g) tmpn capture/compare register 1 (tpnccr1) usually, the tpnccr1 register is not used in the extern al event count mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer r egister. when the count va lue of the 16-bit counter matches the value of the ccr1 buffer register, a co mpare match interrupt request signal (inttpncc1) is generated. therefore, mask the interrupt signal by using the interrupt mask flag (tpnccmk1). caution when an external clock is used as the count clock, the external clock can be input only from the tipn0 pin. at this time, set the tp nioc1.tpnis1 and tpnioc1.tpnis0 bits to 00 (capture trigger input (tipn0 pin): no edge detection). remarks 1. tmpn i/o control register 1 (tpnioc1) and tm pn option register 0 (tpnopt0) are not used in the external event count mode. 2. n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 217 of 870 sep 30, 2010 (1) external event count mode operation flow figure 7-12. flow of software processing in external event count mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 0 d 0 d 0 d 0 <1> <2> tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 218 of 870 sep 30, 2010 (2) operation timing in external event count mode cautions 1. in the external event count mode , do not set the tpnccr0 register to 0000h. 2. in the external event count mode, use of th e timer output is disabled. if performing timer output using external event count input, set th e interval timer mode, and select the operation enabled by the external event count input for the count clock (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 bits = 000, tpnctl1.tpneee bit = 1). (a) operation if tpnccr0 register is set to ffffh if the tpnccr0 register is set to ffffh, the 16-bit coun ter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-b it counter is cleared to 0000h in synchronization with the next count-up timing, and the inttpncc0 signal is gen erated. at this time, the tpnopt0.tpnovf bit is not set. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 219 of 870 sep 30, 2010 (b) notes on rewriting the tpnccr0 register to change the value of the tpnccr0 re gister to a smaller value, stop counting once and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) remark n = 0 to 5 if the value of the tpnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tpnccr0 register has been rewritten. consequently, the value that is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter co unts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttpncc0 signal is generated. therefore, the inttpncc0 signal may not be generated at the va lid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?.
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 220 of 870 sep 30, 2010 (c) operation of tpnccr1 register figure 7-13. configuration of tpnccr1 register ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal inttpncc1 signal edge detector tipn0 pin remark n = 0 to 5 if the set value of the tpnccr1 register is smalle r than the set value of the tpnccr0 register, the inttpncc1 signal is generated once per cycle. figure 7-14. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 221 of 870 sep 30, 2010 if the set value of the tpnccr1 register is greater t han the set value of the tpnccr0 register, the inttpncc1 signal is not generated because the c ount value of the 16-bit counter and the value of the tpnccr1 register do not match. figure 7-15. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 222 of 870 sep 30, 2010 7.5.3 external trigger pulse output m ode (tpnmd2 to tpnmd0 bits = 010) in the external trigger pulse output mode, 16-bit timer/ev ent counter p waits for a trigger when the tpnctl0.tpnce bit is set to 1. when the valid edge of an external trigger input signal is detected, 16-bit timer/ event counter p starts counting , and outputs a pwm waveform from the topn1 pin. pulses can also be output by generating a software trigger inst ead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the topn0 pin. figure 7-16. configuration in external trigger pulse output mode ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) output controller topn1 pin inttpncc1 signal topn0 pin count clock selection count start control edge detector software trigger generation tipn0 pin transfer transfer s r remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 223 of 870 sep 30, 2010 figure 7-17. basic timing in exte rnal trigger pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) 16-bit timer/event counter p waits for a trigger when the tpnce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counting at the same time, and outputs a pwm waveform from the topn1 pin. if the trigger is generated again while the counter is o perating, the counter is cleared to 0000h and restarted. (the output of the topn0 pin is inverted. t he topn1 pin outputs a high-level regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 regist er)/(set value of tpnccr0 register + 1) the compare match request signal inttpncc0 is generated when the 16-bit counter counts ne xt time after its count value matches the value of the ccr0 buffer register, and t he 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttpncc1 is generated when the c ount value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tpnccrm register is transferred to th e ccrm buffer register when t he count value of the 16-bit counter matches the value of the ccrm buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal, or setting the software trigger (tpnctl1.tpnest bit) to 1 is used as the trigger. remark n = 0 to 5, m = 0, 1
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 224 of 870 sep 30, 2010 figure 7-18. register setting for operation in external trigger pulse output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0/1 0 0 0 tpnctl1 generate software trigger when 1 is written 010 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 0, 1, 0: external trigger pulse output mode (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output settings of output level while operation of topn0 pin is disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output specifies active level of topn1 pin output 0: active-high 1: active-low 0/1 0/1 note 0/1 note tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 note clear this bit to 0 when the topn0 pin is not used in the external trigger pulse output mode.
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 225 of 870 sep 30, 2010 figure 7-18. register setting for operation in external trigger pulse output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 00000 tpnioc2 select valid edge of external trigger input 0 0/1 0/1 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tm pn option register 0 (tpnopt0) are not used in the external trigger pulse output mode. 2. n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 226 of 870 sep 30, 2010 (1) operation flow in extern al trigger pulse output mode figure 7-19. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 227 of 870 sep 30, 2010 figure 7-19. software processing flow in ex ternal trigger pulse output mode (2/2) tpnce bit = 1 setting of tpnccr0 register register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting is enabled (tpnce bit = 1). trigger wait status tpnccr1 register write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. start setting of tpnccr1 register <1> count operation start flow <2> tpnccr0 and tpnccr1 register setting change flow setting of tpnccr0 register when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. setting of tpnccr1 register <4> tpnccr0, tpnccr1 register setting change flow only writing of the tpnccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. setting of tpnccr1 register <3> tpnccr0, tpnccr1 register setting change flow tpnce bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0 to 5 m = 0, 1
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 228 of 870 sep 30, 2010 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccrm register after writing the tpnccr 1 register after the inttpncc0 signal is detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 229 of 870 sep 30, 2010 in order to transfer data from the tpnccrm register to the ccrm buffer register, the tpnccr1 register must be written. to change both the cycle and active level width of the pw m waveform at this time, first set the cycle to the tpnccr0 register and then set the active level width to the tpnccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tpnccr0 register, and then write the same value to the tpnccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. after data is written to the tpnccr1 register, the value written to the tpnccrm register is transferred to the ccrm buffer register in synchronization with clearing of the 16-bit counter, and is us ed as the value compared with the 16-bit counter. to write the tpnccr0 or tpnccr1 register again afte r writing the tpnccr1 register once, do so after the inttpncc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the tpnccrm register to the ccrm buffer register conflicts with writing the tpnccrm register. remark n = 0 to 5 m = 0, 1
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 230 of 870 sep 30, 2010 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. if the set value of the tpnccr0 register is ffffh, the inttpncc1 signal is generated periodically. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark n = 0 to 5 to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 231 of 870 sep 30, 2010 (c) conflict between trigger detecti on and match with tpnccr1 register if the trigger is detected immediately after the inttp ncc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the topn1 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened remark n = 0 to 5 if the trigger is detected immediately before the inttpncc1 signal is generated, the inttpncc1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. the output signal of the topn1 pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 232 of 870 sep 30, 2010 (d) conflict between trigger detecti on and match with tpnccr0 register if the trigger is detected immediately after the inttpncc0 signal is generated, the 16- bit counter is cleared to 0000h and continues counting up. therefore, the active period of the topn1 pin is extended by time from generation of the inttpncc0 signal to trigger detection. 16-bit counter tpnccr0 register inttpncc0 signal topn1 pin output external trigger input (tipn0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark n = 0 to 5 if the trigger is detected immediately before the inttpncc0 signal is generated, the inttpncc0 signal is not generated. the 16-bit counter is cleared to 0000h, t he topn1 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter tpnccr0 register inttpncc0 signal topn1 pin output external trigger input (tipn0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark n = 0 to 5
v850es/jg3 chapter 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 233 of 870 sep 30, 2010 (e) generation timing of compare match interrupt request signal (inttpncc1) the timing of generation of the inttpncc1 signal in th e external trigger pulse output mode differs from the timing of other inttpncc1 signals; the inttpncc1 si gnal is generated when the co unt value of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5 usually, the inttpncc1 signal is generated in synchroniza tion with the next count up, after the count value of the 16-bit counter matches the value of the tpnccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of changin g the output signal of the topn1 pin.
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 234 of 870 sep 30, 2010 7.5.4 one-shot pulse output mode (tpnmd2 to tpnmd0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event counte r p waits for a trigger when the tpnctl0.tpnce bit is set to 1. when the valid edge of an external trigger input is det ected, 16-bit timer/event counter p starts counting, and outputs a one-shot pulse from the topn1 pin. instead of the external trigger, a software trigger can al so be generated to output the pulse. when the software trigger is used, the topn0 pin outputs the active level while the 16-bit counter is counti ng, and the inactive level when the counter is stopped (waiting for a trigger). figure 7-20. configuration in one-shot pulse output mode ccr0 buffer register tpnce bit tpnccr0 register tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) topn1 pin inttpncc1 signal topn0 pin count clock selection count start control edge detector software trigger generation tipn0 pin transfer transfer s r output controller (rs-ff) s r 16-bit counter remark n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 235 of 870 sep 30, 2010 figure 7-21. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) delay (d 1 ) delay (d 1 ) active level width (d 0 ? d 1 + 1) active level width (d 0 ? d 1 + 1) active level width (d 0 ? d 1 + 1) when the tpnce bit is set to 1, 16-bit timer/event counter p waits for a trigger. when the trigger is generated, the 16- bit counter is cleared from ffffh to 0000h, starts counting, and outputs a one-shot pulse from the topn1 pin. after the one-shot pulse is output, the 16-bit counter is set to ffffh, stops counting, and waits for a trigger. if a trigger is generated again while the one-shot pul se is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tpnccr1 register) count clock cycle active level width = (set value of tpnccr0 register ? set value of tpnccr1 register + 1) count clock cycle the compare match interrupt request signal inttpncc0 is generated when the 16-bit counter counts after its count value matches the value of the ccr0 buffer register. the compare match interrupt request signal inttpncc1 is generated when the count value of the 16-bit counter matches the val ue of the ccr1 buffer register. the valid edge of an external trigger input or setting the software trigger (tpnctl1.tpnest bit) to 1 is used as the trigger. remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 236 of 870 sep 30, 2010 figure 7-22. register setting for operati on in one-shot pulse output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0/1 0 0 0 tpnctl1 generate software trigger when 1 is written 011 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 0, 1, 1: one-shot pulse output mode (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level while operation of topn0 pin is disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output specifies active level of topn1 pin output 0: active-high 1: active-low 0/1 0/1 note 0/1 note tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 note clear this bit to 0 when the topn0 pin is not used in the one-shot pulse output mode.
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 237 of 870 sep 30, 2010 figure 7-22. register setting for operati on in one-shot pulse output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 00000 tpnioc2 select valid edge of external trigger input 0 0/1 0/1 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 0 ? d 1 + 1) count clock cycle output delay period = (d 1 ) count clock cycle caution one-shot pulses are not output even in th e one-shot pulse output mode, if the value set in the tpnccr1 register is greater th an that set in the tpnccr0 register. remarks 1. tmpn i/o control register 1 (tpnioc1) and tm pn option register 0 (tpnopt0) are not used in the one-shot pulse output mode. 2. n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 238 of 870 sep 30, 2010 (1) operation flow in one-shot pulse output mode figure 7-23. software processing flow in one-shot pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) <1> <3> tpnce bit = 1 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). trigger wait status start <1> count operation start flow tpnce bit = 0 count operation is stopped stop <3> count operation stop flow d 10 d 00 d 11 d 01 d 00 d 10 d 11 <2> d 01 setting of tpnccr0, tpnccr1 registers as rewriting the tpnccrm register immediately forwards to the ccrm buffer register, rewriting immediately after the generation of the inttpnccr0 signal is recommended. <2> tpnccr0, tpnccr1 register setting change flow remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 239 of 870 sep 30, 2010 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tpnccrm register to change the set value of the tpnccrm register to a smaller value, stop counting once, and then change the set value. if the value of the tpnccrm register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 delay (d 10 ) delay (d 10 ) active level width (d 00 ? d 10 + 1) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) when the tpnccr0 register is rewritten from d 00 to d 01 and the tpnccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the tpnccr1 register is rewritten when the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the tpnccr0 register is rewritt en when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter counts up to ffffh and t hen counts up again from 0000h. when the count value matches d 11 , the counter generates the inttpncc1 signal and asserts the topn1 pin. when the count value matches d 01 , the counter generates the in ttpncc0 signal, deasserts the topn1 pin, and stops counting. therefore, the counter may output a pul se with a delay period or active per iod different from that of the one- shot pulse that is originally expected. remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 240 of 870 sep 30, 2010 (b) generation timing of compare match interrupt request signal (inttpncc1) the generation timing of the inttpncc1 signal in the one-shot pulse output mode is different from other inttpncc1 signals; the inttpncc1 signal is generated when the count value of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5 usually, the inttpncc1 signal is generated when the 16-bi t counter counts up next time after its count value matches the value of the tpnccr1 register. in the one-shot pulse output mode, however, it is gene rated one clock earlier. this is because the timing is changed to match the change timing of the topn1 pin. remark n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 241 of 870 sep 30, 2010 7.5.5 pwm output mode (tpnmd 2 to tpnmd0 bits = 100) in the pwm output mode, a pwm waveform is output from the topn1 pin when the tpnctl0.tpnce bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the topn0 pin. figure 7-24. configuration in pwm output mode ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) output controller topn1 pin inttpncc1 signal topn0 pin count clock selection transfer transfer s r remark n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 242 of 870 sep 30, 2010 figure 7-25. basic timing in pwm output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal topn0 pin output tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 ? d 10 + 1) when the tpnce bit is set to 1, the 16-bit counter is cl eared from ffffh to 0000h, starts counting, and outputs a pwm waveform from the topn1 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register ) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 regist er)/(set value of tpnccr0 register + 1) the pwm waveform can be changed by rewriting the tpnccrm register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttpncc0 is gen erated when the 16-bit counter counts next time after its count value matches the value of the ccr 0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttpncc1 is generated when the count value of the 16-bit c ounter matches the value of the ccr1 buffer register. the value set to the tpnccrm register is transferred to th e ccrm buffer register when t he count value of the 16-bit counter matches the value of the ccrm buffer regi ster and the 16-bit counter is cleared to 0000h. remark n = 0 to 5, m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 243 of 870 sep 30, 2010 figure 7-26. register setting for op eration in pwm output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 1 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 100 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 0, 0: pwm output mode 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count external event input signal (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level while operation of topn0 pin is disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output specifies active level of topn1 pin output 0: active-high 1: active-low 0/1 0/1 note 2 0/1 note 2 tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 notes 1. the setting is invalid when the tpnctl1.tpneee bit = 1. 2. clear this bit to 0 when the topn0 pin is not used in the pwm output mode.
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 244 of 870 sep 30, 2010 figure 7-26. register setting for op eration in pwm output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input. 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tm pn option register 0 (tpnopt0) are not used in the pwm output mode. 2. n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 245 of 870 sep 30, 2010 (1) operation flow in pwm output mode figure 7-27. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal topn0 pin output tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <2> <3> <4> <5> <1> remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 246 of 870 sep 30, 2010 figure 7-27. software processing flow in pwm output mode (2/2) tpnce bit = 1 setting of tpnccr0 register register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting is enabled (tpnce bit = 1). tpnccr1 write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. start setting of tpnccr1 register <1> count operation start flow <2> tpnccr0, tpnccr1 register setting change flow setting of tpnccr0 register when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. setting of tpnccr1 register <4> tpnccr0, tpnccr1 register setting change flow only writing of the tpnccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of compare register m is transferred to the ccrm buffer register. setting of tpnccr1 register <3> tpnccr0, tpnccr1 register setting change flow tpnce bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 247 of 870 sep 30, 2010 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccrm register after writing the tpnccr 1 register after the inttpncc1 signal is detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register tpnccr1 register ccr1 buffer register topn1 pin output inttpncc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the tpnccrm register to the c crm buffer register, the tpnccr1 register must be written. to change both the cycle and active level of the pwm wave form at this time, first set the cycle to the tpnccr0 register and then set the active level to the tpnccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tpnccr0 register, and then write the same value to the tpnccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. after data is written to the tpnccr1 register, the value written to the tpnccrm register is transferred to the ccrm buffer register in synchronization with clearing of the 16-bit counter, and is us ed as the value compared with the 16-bit counter. to write the tpnccr0 or tpnccr1 register again afte r writing the tpnccr1 register once, do so after the inttpncc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the tpnccrm register to the ccrm buffer register conflicts with writing the tpnccrm register. remark n = 0 to 5, m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 248 of 870 sep 30, 2010 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. if the set value of the tpnccr0 register is ffffh, the inttpncc1 signal is generated periodically. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 remark n = 0 to 5 to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 remark n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 249 of 870 sep 30, 2010 (c) generation timing of compare match interrupt request signal (inttpncc1) the timing of generation of the inttpncc1 signal in the pwm output mode differs from the timing of other inttpncc1 signals; the inttpncc1 signal is generated when the count value of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5 usually, the inttpncc1 signal is generated in synchroni zation with the next counting up after the count value of the 16-bit counter matches the value of the tpnccr1 register. in the pwm output mode, however, it is generated one cl ock earlier. this is because the timing is changed to match the change timing of the out put signal of the topn1 pin.
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 250 of 870 sep 30, 2010 7.5.6 free-running timer mode (t pnmd2 to tpnmd0 bits = 101) in the free-running timer mode, 16-bit timer/event counter p starts counting when the tpnctl0.tpnce bit is set to 1. at this time, the tpnccrm register can be used as a compare register or a capture register , depending on the setting of the tpnopt0.tpnccs0 and tpnopt0.tpnccs1 bits. figure 7-28. configuration in free-running timer mode tpnccr0 register (capture) tpnce bit tpnccr1 register (compare) 16-bit counter tpnccr1 register (compare) tpnccr0 register (capture) output controller tpnccs0, tpnccs1 bits (capture/compare selection) topn0 pin output output controller topn1 pin output edge detector count clock selection edge detector edge detector tipn0 pin (external event count input/ capture trigger input) tipn1 pin (capture trigger input) internal count clock 0 1 0 1 inttpnov signal inttpncc1 signal inttpncc0 signal remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 251 of 870 sep 30, 2010 when the tpnce bit is set to 1, 16-bit timer/event counter p starts counting, and the out put signals of the topn0 and topn1 pins are inverted. when the count value of the 16-bit counter later matches the set value of the tpnccrm register, a compare match interrupt request signal (inttpnccm) is gener ated, and the output signal of the topnm pin is inverted. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttpnov) at t he next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tpnopt0.t pnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the tpnccrm register can be rewritten while the counter is operat ing. if it is rewritten, the new value is reflected at that time, and compared with the count value. figure 7-29. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn0 pin output tpnccr1 register inttpncc1 signal topn1 pin output inttpnov signal tpnovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 252 of 870 sep 30, 2010 when the tpnce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tipnm pin is detected, the count value of the 16-bit counter is stored in the tpnccrm r egister, and a capture interrupt request signal (inttpnccm) is generated. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttpnov) at t he next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tpnopt0.t pnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. figure 7-30. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal tipn1 pin input tpnccr1 register inttpncc1 signal inttpnov signal tpnovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 253 of 870 sep 30, 2010 figure 7-31. register setting in free-running timer mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note the setting is invalid when the tpnctl1.tpneee bit = 1 (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 101 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 0, 1: free-running mode 0: operate with count clock selected by tpncks0 to tpncks2 bits 1: count on external event count input signal (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level with operation of topn0 pin disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of output level with operation of topn1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 254 of 870 sep 30, 2010 figure 7-31. register setting in free-running timer mode (2/2) (d) tmpn i/o control register 1 (tpnioc1) 0 0 0 0 0/1 tpnioc1 select valid edge of tipn0 pin input select valid edge of tipn1 pin input 0/1 0/1 0/1 tpnis2 tpnis1 tpnis0 tpnis3 (e) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 (f) tmpn option register 0 (tpnopt0) 0 0 0/1 0/1 0 tpnopt0 overflow flag specifies if tpnccr0 register functions as capture or compare register specifies if tpnccr1 register functions as capture or compare register 0 0 0/1 tpnccs0 tpnovf tpnccs1 (g) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (h) tmpn capture/compare regist ers 0 and 1 (tpnccr0 and tpnccr1) these registers function as capture registers or compare regi sters depending on the setting of the tpnopt0.tpnccsm bit. when the registers function as capture registers, they store the c ount value of the 16-bit counter when the valid edge input to the tipnm pin is detected. when the registers function as compare registers and when d m is set to the tpnccrm register, the inttpnccm signal is generated when the counter reaches (d m + 1), and the output signal of the topnm pin is inverted. remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 255 of 870 sep 30, 2010 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 7-32. software processing flow in fr ee-running timer mode (c ompare function) (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn0 pin output tpnccr1 register inttpncc1 signal topn1 pin output inttpnov signal tpnovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction set value changed cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3> set value changed remark n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 256 of 870 sep 30, 2010 figure 7-32. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tpnce bit = 1 read tpnopt0 register (check overflow flag). register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnopt0 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). start execute instruction to clear tpnovf bit (clr tpnovf). <1> count operation start flow <2> overflow flag clear flow tpnce bit = 0 counter is initialized and counting is stopped by clearing tpnce bit to 0. stop <3> count operation stop flow tpnovf bit = 1 no yes remark n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 257 of 870 sep 30, 2010 (b) when using capture/compare register as capture register figure 7-33. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal tipn1 pin input tpnccr1 register inttpncc1 signal inttpnov signal tpnovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> remark n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 258 of 870 sep 30, 2010 figure 7-33. software processing flow in fr ee-running timer mode (c apture function) (2/2) tpnce bit = 1 read tpnopt0 register (check overflow flag). register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc1 register, tpnopt0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). start execute instruction to clear tpnovf bit (clr tpnovf). <1> count operation start flow <2> overflow flag clear flow tpnce bit = 0 counter is initialized and counting is stopped by clearing tpnce bit to 0. stop <3> count operation stop flow tpnovf bit = 1 no yes remark n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 259 of 870 sep 30, 2010 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter p is used as an interval timer with the tpnccrm register used as a compare register, software processing is necessary for setting a co mparison value to generate the next interrupt request signal each time the inttpnccm signal has been detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn pin output tpnccr1 register inttpncc1 signal topn1 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the co rresponding tpnccrm register must be re-set in the interrupt servicing that is executed when the inttpnccm signal is detected. the set value for re-setting the tpnccrm register ca n be calculated by the following expression, where ?d m ? is the interval period. compare register default value: d m ? 1 value set to compare register second and subsequent time: previous set value + d m (if the calculation resu lt is greater than ffffh, subtract 10000h fr om the result and set this value to the register.) remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 260 of 870 sep 30, 2010 (b) pulse width measurement with capture register when pulse width measurement is perfo rmed with the tpnccrm register us ed as a capture register, software processing is necessary for reading the capture regi ster each time the inttpnccm signal has been detected and for calculating an interval. ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal tipn1 pin input tpnccr1 register inttpncc1 signal inttpnov signal tpnovf bit 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 pulse interval (d 00 ) pulse interval (10000h + d 01 ? d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calculat ed by reading the value of the tpnccrm register in synchronization with the inttpnccm signal, and calcul ating the difference between the read value and the previously read value. remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 261 of 870 sep 30, 2010 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register tipn1 pin input tpnccr1 register inttpnov signal tpnovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tpnccr0 register (setting of t he default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the tipn1 pin input). <3> read the tpnccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tpnccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtai n the correct pulse width. use software when using two capture registers. an example of how to use software is shown below.
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 262 of 870 sep 30, 2010 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tpnce bit inttpnov signal tpnovf bit tpnovf0 flag note tipn0 pin input tpnccr0 register tpnovf1 flag note tipn1 pin input tpnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> read the tpnccr0 register (setting of t he default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the tipn1 pin input). <3> an overflow occurs. set the tpnovf0 and tpnovf1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tpnccr0 register. read the tpnovf0 flag. if the tpnovf0 flag is 1, clear it to 0. because the tpnovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tpnccr1 register. read the tpnovf1 flag. if the tpnovf1 flag is 1, clear it to 0 (the tpnovf0 flag is cleared in <4>, and the tpnovf1 flag remains 1). because the tpnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 263 of 870 sep 30, 2010 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tpnce bit inttpnov signal tpnovf bit tpnovf0 flag note tipn0 pin input tpnccr0 register tpnovf1 flag note tipn1 pin input tpnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> read the tpnccr0 register (setting of t he default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the tipn1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tpnccr0 register. read the overflow flag. if the overflow flag is 1, set only the tpnovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tpnccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tpnovf1 flag. if the tpnovf1 flag is 1, clear it to 0. because the tpnovf1 flag is 1, the pul se width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 264 of 870 sep 30, 2010 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tpnce bit tipnm pin input tpnccrm register inttpnov signal tpnovf bit d m0 d m1 d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the tpnccrm register (setting of t he default value of the tipnm pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tpnccrm register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d m1 ? d m0 ) (incorrect). actually, the pulse width must be (20000h + d m1 ? d m0 ) because an overflow occurs twice. if an overflow occurs twice or more when the capture trigge r interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next.
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 265 of 870 sep 30, 2010 example when capture trigger interval is long ffffh 16-bit counter 0000h tpnce bit tipnm pin input tpnccrm register inttpnov signal tpnovf bit overflow counter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tpnccrm register (setting of t he default value of the tipnm pin input). <2> an overflow occurs. increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tpnccrm register. read the overflow counter. when the overflow counter is ?n?, the pulse width can be calculated by (n 10000h + d m1 ? d m0 ). in this example, the pulse width is (20000h + d m1 ? d m0 ) because an overflow occurs twice. clear the overflow counter (0h).
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 266 of 870 sep 30, 2010 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tpno vf bit to 0 with the clr in struction and by writing 8- bit data (bit 0 is 0) to the tpnopt0 register. to accura tely detect an overflow, read the tpnovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tpnovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tpnovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tpnovf bit) overflow flag (tpnovf bit) l h l remark n = 0 to 5 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without checking if the flag is 1, t he set information of overflow may be erased by writing 0 ((ii) in the above chart) . therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction.
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 267 of 870 sep 30, 2010 7.5.7 pulse width measurement mode (tpnmd2 to tpnmd0 bits = 110) in the pulse width measurement mode, 16-bit timer/event c ounter p starts counting when t he tpnctl0.tpnce bit is set to 1. each time the valid edge input to the tipnm pin has b een detected, the count value of t he 16-bit counter is stored in the tpnccrm register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by readi ng the tpnccrm register after a capture interrupt request signal (inttpnccm) occurs. select either the tipn0 or tipn1 pin as the capture trigger input pin. specif y ?no edge detected? by using the tpnioc1 register for the unused pins. figure 7-34. configuration in pulse width measurement mode tpnccr0 register (capture) tpnce bit tpnccr1 register (capture) edge detector count clock selection edge detector edge detector tipn0 pin (external event count input/capture trigger input) tipn1 pin (capture trigger input) internal count clock clear inttpnov signal inttpncc0 signal inttpncc1 signal 16-bit counter remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 268 of 870 sep 30, 2010 figure 7-35. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tpnce bit tipnm pin input tpnccrm register inttpnccm signal inttpnov signal tpnovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark n = 0 to 5 m = 0, 1 when the tpnce bit is set to 1, the 16-bi t counter starts counting. when the valid edge input to the tipnm pin is later detected, the count value of the 16-bit counter is stored in the tpnccrm register, the 16-bi t counter is cleared to 0000h, and a capture interrupt request signal (inttpnccm) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tipnm pin even when the 16-bit counter c ounted up to ffffh, an overflow interrupt request signal (inttpnov) is generated at the next coun t clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tpnovf bit set (1) count + captured value) count clock cycle remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 269 of 870 sep 30, 2010 figure 7-36. register setting in pu lse width measurement mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 00000 tpnctl1 110 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 1, 0: pulse width measurement mode (c) tmpn i/o control register 1 (tpnioc1) 0 0 0 0 0/1 tpnioc1 select valid edge of tipn0 pin input select valid edge of tipn1 pin input 0/1 0/1 0/1 tpnis2 tpnis1 tpnis0 tpnis3
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 270 of 870 sep 30, 2010 figure 7-36. register setting in pu lse width measurement mode (2/2) (d) tmpn option register 0 (tpnopt0) 00000 tpnopt0 overflow flag 0 0 0/1 tpnccs0 tpnovf tpnccs1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) these registers store the count valu e of the 16-bit counter when the vali d edge input to the tipnm pin is detected. remarks 1. tmpn i/o control register 0 (tpnioc0) and tm pn i/o control register 2 (tpnioc2) are not used in the pulse width measurement mode. 2. n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 271 of 870 sep 30, 2010 (1) operation flow in pul se width measurement mode figure 7-37. software processing flow in pulse width measurement mode <1> <2> set tpnctl0 register (tpnce bit = 1) tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits), tpnctl1 register, tpnioc1 register, tpnioc2 register, tpnopt0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal d 0 0000h 0000h d 1 d 2 remark n = 0 to 5
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 272 of 870 sep 30, 2010 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tpno vf bit to 0 with the clr in struction and by writing 8- bit data (bit 0 is 0) to the tpnopt0 register. to accura tely detect an overflow, read the tpnovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tpnovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tpnovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tpnovf bit) overflow flag (tpnovf bit) l h l remark n = 0 to 5 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without checking if the flag is 1, t he set information of overflow may be erased by writing 0 ((ii) in the above chart) . therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction.
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 273 of 870 sep 30, 2010 7.5.8 timer output operations the following table shows the operations and out put levels of the topn0 and topn1 pins. table 7-4. timer output control in each mode operation mode topn1 pin topn0 pin interval timer mode square wave output external event count mode square wave output ? external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output square wave output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? remark n = 0 to 5 table 7-5. truth table of topn0 and topn1 pins under control of timer output control bits tpnioc0.tpnolm bit tpnioc0.tpnoem bit tpnctl0.tpnce bit level of topnm pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark n = 0 to 5 m = 0, 1
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 274 of 870 sep 30, 2010 7.6 selector function in the v850es/jg3, the capture trigger input for tmp can be se lected from the input signal via the port/timer alternate- function pin and the peripheral i/o (tmp/uarta) input signal. this function makes the following possible. ? the tip10 and tip11 input si gnals for tmp1 can be selected from the si gnals via the port/timer alternate-function pins (tip10 and tip11) and the signals via the uarta reception alternate-function pins (rxda0 and rxda1). when the rxda0 and rxda1 signals for uarta0 and uart a1 are selected, the baud rate error of the uarta lin reception transfer rate can be calculated. cautions 1. when using the selector function, be sure to set the port/timer alternate function pins for tmp to be connected to the capture trigger input. 2. disable the peripheral i/os to be connected (tmp/uarta) before setting the selector function. the capture trigger input can be sele cted using the following register.
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 275 of 870 sep 30, 2010 (1) selector operation control register 0 (selcnt0) the selcnt0 register is an 8-bit register that selects the capture trigger for tmp1. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 selcnt0 0 0 isel4 isel3 0 0 0 tip11 pin input rxda1 pin input isel4 0 1 selection of tip11 input signal (tmp1) tip10 pin input rxda0 pin input isel3 0 1 selection of tip10 input signal (tmp1) after reset: 00h r/w address: fffff308h < > < > cautions 1. when setting the isel3 or i sel4 bit to ?1?, be sure to set the corresponding alternate-function pins to the capture trigger input. 2. be sure to clear bits 7 to 5, and 2 to 0 to ?0?.
v850es/jg3 chaptrer 7 16-bit timer/event counter p (tmp) r01uh0015ej0300 rev.3.00 page 276 of 870 sep 30, 2010 7.7 cautions (1) capture operation when the capture operation is used and a slow clock is selected as the count clock, ffffh , not 0000h, may be captured in the tpnccr0 and tpnccr1 registers if the capt ure trigger is input immediately after the tpnce bit is set to 1. (a) free-running timer mode count clock 0000h ffffh tpnce bit tpnccr0 register ffffh 0001h 0000h tipn0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tpnce bit tpnccr0 register tipn0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 277 of 870 sep 30, 2010 chapter 8 16-bit timer/event counter q (tmq) timer q (tmq) is a 16-bit timer/event counter. the v850es/jg3 incorporates tmq0. 8.1 overview an outline of tmq0 is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 4 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 4 ? capture/compare match interrupt request signals: 4 ? timer output pins: 4 8.2 functions tmq0 has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 278 of 870 sep 30, 2010 8.3 configuration tmq0 includes the following hardware. table 8-1. configuration of tmq0 item configuration timer register 16-bit counter registers tmq0 capture/compare registers 0 to 3 (tq0ccr0 to tq0ccr3) tmq0 counter read buffer register (tq0cnt) ccr0 to ccr3 buffer registers timer inputs 4 (tiq00 note 1 to tiq03 pins) timer outputs 4 (toq00 to toq03 pins) control registers note 2 tmq0 control registers 0, 1 (tq0ctl0, tq0ctl1) tmq0 i/o control registers 0 to 2 (tq0ioc0 to tq0ioc2) tmq0 option register 0 (tq0opt0) notes 1. the tiq00 pin functions alternat ely as a capture trigger input signal, external event count input signal, and external trigger input signal. 2. when using the functions of the tiq00 to tiq03 and toq00 to toq03 pins, see table 4-15 using port pin as alternate-function pin . figure 8-1. block diagram of tmq0 tq0cnt tq0ccr0 tq0ccr1 tq0ccr2 toq00 inttq0ov ccr2 buffer register tq0ccr3 ccr3 buffer register toq01 toq02 toq03 inttq0cc0 inttq0cc1 inttq0cc2 inttq0cc3 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tiq00 tiq01 tiq02 tiq03 selector internal bus internal bus selector edge detector ccr0 buffer register ccr1 buffer register 16-bit counter output controller clear remark f xx : main clock frequency
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 279 of 870 sep 30, 2010 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tq0cnt register. when the tq0ctl0.tq0ce bit = 0, the val ue of the 16-bit counter is ffffh. if the tq0cnt register is read at this time, 0000h is read. reset sets the tq0ce bit to 0. therefor e, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr0 register is used as a compare regist er, the value written to the tq0ccr0 register is transferred to the ccr0 buffer register. when the count va lue of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttq0cc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tq0ccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr1 register is used as a compare regist er, the value written to the tq0ccr1 register is transferred to the ccr1 buffer register. when the count va lue of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttq0cc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tq0ccr1 register is cleared to 0000h. (4) ccr2 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr2 register is used as a compare regist er, the value written to the tq0ccr2 register is transferred to the ccr2 buffer register. when the count va lue of the 16-bit counter ma tches the value of the ccr2 buffer register, a compare match interrupt request signal (inttq0cc2) is generated. the ccr2 buffer register cannot be read or written directly. the ccr2 buffer register is cleared to 0000h after reset, as the tq0ccr2 register is cleared to 0000h. (5) ccr3 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr3 register is used as a compare regist er, the value written to the tq0ccr3 register is transferred to the ccr3 buffer register. when the count va lue of the 16-bit counter ma tches the value of the ccr3 buffer register, a compare match interrupt request signal (inttq0cc3) is generated. the ccr3 buffer register cannot be read or written directly. the ccr3 buffer register is cleared to 0000h after reset, as the tq0ccr3 register is cleared to 0000h. (6) edge detector this circuit detects the valid edges input to the tiq00 and tiq03 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the va lid edge by using the tq0ioc1 and tq0ioc2 registers. (7) output controller this circuit controls the output of t he toq00 to toq03 pins. the output cont roller is controlled by the tq0ioc0 register. (8) selector this selector selects the count clock for the 16-bit counter. eight types of internal clocks or an external event can be selected as the count clock.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 280 of 870 sep 30, 2010 8.4 registers the registers that control tmq0 are as follows. ? tmq0 control register 0 (tq0ctl0) ? tmq0 control register 1 (tq0ctl1) ? tmq0 i/o control register 0 (tq0ioc0) ? tmq0 i/o control register 1 (tq0ioc1) ? tmq0 i/o control register 2 (tq0ioc2) ? tmq0 option register 0 (tq0opt0) ? tmq0 capture/compare register 0 (tq0ccr0) ? tmq0 capture/compare register 1 (tq0ccr1) ? tmq0 capture/compare register 2 (tq0ccr2) ? tmq0 capture/compare register 3 (tq0ccr3) ? tmq0 counter read buffer register (tq0cnt) remark when using the functions of the tiq00 to tiq03 and toq00 to toq03 pins, see table 4-15 using port pin as alternate-function pin .
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 281 of 870 sep 30, 2010 (1) tmq0 control register 0 (tq0ctl0) the tq0ctl0 register is an 8-bit register that controls the operation of tmq0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tq0ctl0 register by software. tq0ce tmq0 operation disabled (tmq0 reset asynchronously note ). tmq0 operation enabled. tmq0 operation started. tq0ce 0 1 tmq0 operation control tq0ctl0 0 0 0 0 tq0cks2 tq0cks1 tq0cks0 654321 after reset: 00h r/w address: fffff540h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tq0cks2 0 0 0 0 1 1 1 1 internal count clock selection tq0cks1 0 0 1 1 0 0 1 1 tq0cks0 0 1 0 1 0 1 0 1 note tq0opt0.tq0ovf bit, 16-bit counter, timer output (toq00 to toq03 pins) cautions 1. set the tq0cks2 to tq0 cks0 bits when the tq0ce bit = 0. when the value of the tq0ce bi t is changed from 0 to 1, the tq0cks2 to tq0cks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 282 of 870 sep 30, 2010 (2) tmq0 control register 1 (tq0ctl1) the tq0ctl1 register is an 8-bit register that controls the operation of tmq0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tq0est 0 1 software trigger control tq0ctl1 tq0est tq0eee 0 0 tq0md2 tq0md1 tq0md0 <6> <5> 4 3 2 1 after reset: 00h r/w address: fffff541h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tq0est bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tq0est bit as the trigger. disable operation with external event count input. (perform counting with the count clock selected by the tq0ctl0.tq0ck0 to tq0ck2 bits.) tq0eee 0 1 count clock selection the tq0eee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tq0md2 0 0 0 0 1 1 1 1 timer mode selection tq0md1 0 0 1 1 0 0 1 1 tq0md0 0 1 0 1 0 1 0 1 enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) ? cautions 1. the tq0est bit is valid on ly in the external trigger pulse output mode or one-shot pulse output mode . in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tq0eee bit. 3. set the tq0eee and tq0md2 to tq0md0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) the op eration is not guaranteed when rewriting is performed with the tq0ce bit = 1. if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 4. be sure to clear bits 3, 4, and 7 to ?0?.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 283 of 870 sep 30, 2010 (3) tmq0 i/o control register 0 (tq0ioc0) the tq0ioc0 register is an 8-bit register that controls the timer output (toq00 to toq03 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tq0ol3 tq0olm 0 1 toq0m pin output level setting (m = 0 to 3) note toq0m pin output starts at high level toq0m pin output starts at low level tq0ioc0 tq0oe3 tq0ol2 tq0oe2 tq0ol1 tq0oe1 tq0ol0 tq0oe0 <6> 5 <4> 3 <2> 1 after reset: 00h r/w address: fffff542h tq0oem 0 1 toq0m pin output setting (m = 0 to 3) timer output disabled ? when tq0olm bit = 0: low level is output from the toq0m pin ? when tq0olm bit = 1: high level is output from the toq0m pin 7 <0> timer output enabled (a square wave is output from the toq0m pin). note the output level of the timer out put pin (toq0m) specified by the tq0olm bit is shown below. tq0ce bit toq0m output pin 16-bit counter ? when tq0olm bit = 0 tq0ce bit toq0m output pin 16-bit counter ? when tq0olm bit = 1 cautions 1. rewrite the tq0olm and tq0oem bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. even if the tq0olm bit is manipulated when the tq0ce and tq0oem bits are 0, the toq0 m pin output level varies. remark m = 0 to 3
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 284 of 870 sep 30, 2010 (4) tmq0 i/o control register 1 (tq0ioc1) the tq0ioc1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (tiq00 to tiq03 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tq0is7 tq0is7 0 0 1 1 tq0is6 0 1 0 1 capture trigger input signal (tiq03 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0ioc1 tq0is6 tq0is5 tq0is4 tq0is3 tq0is2 tq0is1 tq0is0 654321 after reset: 00h r/w address: fffff543h tq0is5 0 0 1 1 tq0is4 0 1 0 1 capture trigger input signal (tiq02 pin) valid edge detection no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 tq0is3 0 0 1 1 tq0is2 0 1 0 1 capture trigger input signal (tiq01 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0is1 0 0 1 1 tq0is0 0 1 0 1 capture trigger input signal (tiq00 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges cautions 1. rewrite the tq0is7 to tq0is0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. the tq0is7 to tq0is0 bi ts are valid only in the free- running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 285 of 870 sep 30, 2010 (5) tmq0 i/o control register 2 (tq0ioc2) the tq0ioc2 register is an 8-bit regist er that controls the va lid edge of the external event count input signal (tiq00 pin) and external trigger input signal (tiq00 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tq0ees1 0 0 1 1 tq0ees0 0 1 0 1 external event count input signal (tiq00 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tq0ioc2 0 0 0 tq0ees1 tq0ees0 tq0ets1 tq0ets0 654321 after reset: 00h r/w address: fffff544h tq0ets1 0 0 1 1 tq0ets0 0 1 0 1 external trigger input signal (tiq00 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tq0ees1, tq0ees0, tq0ets1, and tq0ets0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. the tq0ees1 and tq0ees0 bits are valid only when the tq0ctl1.tq0eee bit = 1 or when the external event count mode (tq0ctl1.tq0md 2 to tq0ctl1.tq0md0 bits = 001) has been set. 3. the tq0ets1 and tq0ets0 bits are valid only when the external trigger pulse output mode (tq0ctl1.tq0md2 to tq0ctl1.tq0md0 bits = 010) or the one-shot pulse output mode (tq0ctl1.tq0 md2 to tq0ctl1.tq0md0 = 011) is set.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 286 of 870 sep 30, 2010 (6) tmq0 option register 0 (tq0opt0) the tq0opt0 register is an 8-bit register used to set the capture/co mpare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tq0ccs3 tq0ccsm 0 1 tq0ccrm register capture/compare selection the tq0ccsm bit setting is valid only in the free-running timer mode. compare register selected capture register selected tq0opt0 tq0ccs2 tq0ccs1 tq0ccs0 0 0 0 tq0ovf 654321 after reset: 00h r/w address: fffff545h tq0ovf set (1) reset (0) tmq0 overflow detection ? the tq0ovf bit is set when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an interrupt request signal (inttq0ov) is generated at the same time that the tq0ovf bit is set to 1. the inttq0ov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tq0ovf bit is not cleared even when the tq0ovf bit or the tq0opt0 register are read when the tq0ovf bit = 1. ? the tq0ovf bit can be both read and written, but the tq0ovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmq0. overflow occurred tq0ovf bit 0 written or tq0ctl0.tq0ce bit = 0 7 <0> cautions 1. rewrite the tq0ccs 3 to tq0ccs0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3 to ?0?. remark m = 0 to 3
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 287 of 870 sep 30, 2010 (7) tmq0 capture/compare register 0 (tq0ccr0) the tq0ccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the tq0opt 0.tq0ccs0 bit. in the pulse wid th measurement mode, the tq0ccr0 register can be used only as a capture register. in an y other mode, this register can be used only as a compare register. the tq0ccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tq0ccr0 register is prohibited in the following stat uses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tq0ccr0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff546h 14 0 13 11 9 7 5 3 15 1
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 288 of 870 sep 30, 2010 (a) function as compare register the tq0ccr0 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register , a compare match interrupt request signal (inttq0cc0) is generated. if toq00 pin output is enabled at th is time, the output of t he toq00 pin is inverted. when the tq0ccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse out put mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count value ma tches the value of the ccr0 buffer register. (b) function as capture register when the tq0ccr0 register is used as a capture register in the free-runn ing timer mode, the count value of the 16-bit counter is stored in the tq 0ccr0 register if the valid edge of the capture trigger input pin (tiq00 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tq0ccr0 register and the 16-bit counter is cleared (0000h) if the valid edg e of the capture trigger input pin (tiq00 pin) is detected. even if the capture operation and readi ng the tq0ccr0 register conflict, the correct value of the tq0ccr0 register can be read. the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 8-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ?
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 289 of 870 sep 30, 2010 (8) tmq0 capture/compare register 1 (tq0ccr1) the tq0ccr1 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the tq0opt 0.tq0ccs1 bit. in the pulse wid th measurement mode, the tq0ccr1 register can be used only as a capture register. in an y other mode, this register can be used only as a compare register. the tq0ccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tq0ccr1 register is prohibited in the following stat uses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tq0ccr1 12 10 8 6 4 2 after reset: 0000h r/w address: fffff548h 14 0 13 11 9 7 5 3 15 1
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 290 of 870 sep 30, 2010 (a) function as compare register the tq0ccr1 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register , a compare match interrupt request signal (inttq0cc1) is generated. if toq01 pin output is enabled at th is time, the output of t he toq01 pin is inverted. (b) function as capture register when the tq0ccr1 register is used as a capture register in the free-runn ing timer mode, the count value of the 16-bit counter is stored in the tq 0ccr1 register if the valid edge of the capture trigger input pin (tiq01 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tq0ccr1 register and the 16-bit counter is cleared (0000h) if the valid edg e of the capture trigger input pin (tiq01 pin) is detected. even if the capture operation and readi ng the tq0ccr1 register conflict, the correct value of the tq0ccr1 register can be read. the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 8-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ?
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 291 of 870 sep 30, 2010 (9) tmq0 capture/compare register 2 (tq0ccr2) the tq0ccr2 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the tq0opt 0.tq0ccs2 bit. in the pulse wid th measurement mode, the tq0ccr2 register can be used only as a capture register. in an y other mode, this register can be used only as a compare register. the tq0ccr2 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tq0ccr2 register is prohibited in the following stat uses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tq0ccr2 12 10 8 6 4 2 after reset: 0000h r/w address: fffff54ah 14 0 13 11 9 7 5 3 15 1
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 292 of 870 sep 30, 2010 (a) function as compare register the tq0ccr2 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr2 register is transferred to the ccr2 buffer register. when the value of the 16-bit counter matches the value of the ccr2 buffer register , a compare match interrupt request signal (inttq0cc2) is generated. if toq02 pin output is enabled at th is time, the output of t he toq02 pin is inverted. (b) function as capture register when the tq0ccr2 register is used as a capture register in the free-runn ing timer mode, the count value of the 16-bit counter is stored in the tq 0ccr2 register if the valid edge of the capture trigger input pin (tiq02 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tq0ccr2 register and the 16-bit counter is cleared (0000h) if the valid edg e of the capture trigger input pin (tiq02 pin) is detected. even if the capture operation and readi ng the tq0ccr2 register conflict, the correct value of the tq0ccr2 register can be read. the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 8-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ?
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 293 of 870 sep 30, 2010 (10) tmq0 capture/compare register 3 (tq0ccr3) the tq0ccr3 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the tq0opt 0.tq0ccs3 bit. in the pulse wid th measurement mode, the tq0ccr3 register can be used only as a capture register. in an y other mode, this register can be used only as a compare register. the tq0ccr3 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tq0ccr3 register is prohibited in the following stat uses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tq0ccr3 12 10 8 6 4 2 after reset: 0000h r/w address: fffff54ch 14 0 13 11 9 7 5 3 15 1
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 294 of 870 sep 30, 2010 (a) function as compare register the tq0ccr3 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr3 register is transferred to the ccr3 buffer register. when the value of the 16-bit counter matches the value of the ccr3 buffer register , a compare match interrupt request signal (inttq0cc3) is generated. if toq03 pin output is enabled at th is time, the output of t he toq03 pin is inverted. (b) function as capture register when the tq0ccr3 register is used as a capture register in the free-runn ing timer mode, the count value of the 16-bit counter is stored in the tq 0ccr3 register if the valid edge of the capture trigger input pin (tiq03 pin) is detected. in the pulse-width measurement mode, the count value of the 16-bit counter is stored in the tq0ccr3 register and the 16-bit counter is cleared (0000h) if the valid edg e of the capture trigger input pin (tiq03 pin) is detected. even if the capture operation and readi ng the tq0ccr3 register conflict, the correct value of the tq0ccr3 register can be read. the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 8-5. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ?
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 295 of 870 sep 30, 2010 (11) tmq0 counter read buffer register (tq0cnt) the tq0cnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tq0ctl0.tq0ce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tq0cnt register is cleared to 0000h when the tq0ce bit = 0. if the tq0cnt register is read at this time, the value of the 16-bit counter (ffffh) is not read, but 0000h is read. the value of the tq0cnt register is cleared to 0000h after reset, as the tq0ce bit is cleared to 0. caution accessing the tq0cnt register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tq0cnt 12 10 8 6 4 2 after reset: 0000h r address: fffff54eh 14 0 13 11 9 7 5 3 15 1
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 296 of 870 sep 30, 2010 8.5 operation tmq0 can perform the following operations. operation tq0ctl1.tq0est bit (software trigger bit) tiq00 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count mode, specify that the valid edge of the tiq00 pin c apture trigger input is not detected (by clearing the tq0ioc1.tq0is1 and tq0ioc1.tq0is0 bits to ?00?). 2. when using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tq0ctl1.tq0eee bit to 0).
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 297 of 870 sep 30, 2010 8.5.1 interval timer mode (t q0md2 to tq0md0 bits = 000) in the interval timer mode, an interrupt request signal (in ttq0cc0) is generated at the specified interval if the tq0ctl0.tq0ce bit is set to 1. a square wave whose half cycle is equal to the interval can be output from the toq00 pin. usually, the tq0ccr1 to tq0ccr3 registers are not used in the interval timer mode. figure 8-2. configuration of interval timer 16-bit counter output controller ccr0 buffer register tq0ce bit tq0ccr0 register count clock selection clear match signal toq00 pin inttq0cc0 signal figure 8-3. basic timing of op eration in interval timer mode ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1)
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 298 of 870 sep 30, 2010 when the tq0ce bit is set to 1, the valu e of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and the counter st arts counting. at this time , the output of the toq00 pin is inverted. additionally, the se t value of the tq0ccr0 register is tr ansferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the toq00 pin is inverted, and a compare match interrupt request signal (inttq0cc0) is generated. the interval can be calculated by the following expression. interval = (set value of tq0ccr0 register + 1) count clock cycle figure 8-4. register setting for in terval timer mode operation (1/2) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 note 00 tq0ctl1 0, 0, 0: interval timer mode 000 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0: operate on count clock selected by bits tq0cks0 to tq0cks2 1: count with external event count input signal note this bit can be set to 1 only when the interrupt request signals (inttq0cc0 and inttq0cck) are masked by the interrupt mask flags (tq0ccmk0 to tq0ccmkk) and the timer output (toq0k) is performed at the same time. however, the tq0ccr0 and tq0ccrk re gisters must be set to the same value (see 8.5.1 (2) (d) operation of tq0ccr1 to tq0ccr3 registers ) (k = 1 to 3).
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 299 of 870 sep 30, 2010 figure 8-4. register setting for in terval timer mode operation (2/2) (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output 1: enable toq00 pin output setting of output level with operation of toq00 pin disabled 0: low level 1: high level 0: disable toq01 pin output 1: enable toq01 pin output setting of output level with operation of toq01 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tq0oe1 tq0ol0 tq0oe0 tq0ol1 0: disable toq02 pin output 1: enable toq02 pin output setting of output level with operation of toq02 pin disabled 0: low level 1: high level 0: disable toq03 pin output 1: enable toq03 pin output setting of output level with operation of toq03 pin disabled 0: low level 1: high level tq0oe3 tq0ol2 tq0oe2 tq0ol3 (d) tmq0 counter read buffer register (tq0cnt) by reading the tq0cnt register, the count va lue of the 16-bit counter can be read. (e) tmq0 capture/compare register 0 (tq0ccr0) if the tq0ccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tmq0 capture/compare register s 1 to 3 (tq0ccr1 to tq0ccr3) usually, the tq0ccr1 to tq0ccr3 registers are not us ed in the interval timer mode. however, the set value of the tq0ccr1 to tq0ccr3 registers are transferred to the ccr1 to ccr3 buffer registers. the compare match interrupt request signals (inttq0cc1 to inttq0ccr3) is generated when the count value of the 16-bit counter matches the va lue of the ccr1 to ccr3 buffer registers. therefore, mask the interrupt request by using the corresponding interrupt mask flags (tq0ccmk1 to tq0ccmk3). remark tmq0 i/o control register 1 (tq0ioc1), tmq0 i/o control register 2 (tq0ioc2), and tmq0 option register 0 (tq0opt0) are not used in the interval timer mode.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 300 of 870 sep 30, 2010 (1) interval timer mode operation flow figure 8-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tq0ce bit = 1 tq0ce bit = 0 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ccr0 register initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). the counter is initialized and counting is stopped by clearing the tq0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 301 of 870 sep 30, 2010 (2) interval timer mode operation timing (a) operation if tq0ccr0 re gister is set to 0000h if the tq0ccr0 register is set to 0000h, the inttq0cc0 signal is generated at each count clock subsequent to the first count clock, and the out put of the toq00 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal 0000h interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h (b) operation if tq0ccr0 re gister is set to ffffh if the tq0ccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing. the inttq0cc0 signal is generated and the output of the toq00 pin is inverted. at this time, an overflow interrupt request signal (inttq0ov) is not generated, nor is the overflow flag (tq0opt0.tq0ovf bit) set to 1. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 302 of 870 sep 30, 2010 (c) notes on rewriting tq0ccr0 register to change the value of the tq0ccr0 register to a sm aller value, stop counting once and then change the set value. if the value of the tq0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register tq0ol0 bit toq00 pin output inttq0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remark interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle if the value of the tq0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as t he tq0ccr0 register has been rewritten. consequently, the value of t he 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter co unts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttq0cc0 signal is generated and the output of the t oq00 pin is inverted. therefore, the inttq0cc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 303 of 870 sep 30, 2010 (d) operation of tq0ccr1 to tq0ccr3 registers figure 8-6. configuration of tq0ccr1 to tq0ccr3 registers ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal tq0ccr3 register ccr3 buffer register match signal toq02 pin inttq0cc2 signal tq0ccr2 register ccr2 buffer register match signal output controller count clock selection output controller output controller output controller 16-bit counter
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 304 of 870 sep 30, 2010 if the set value of the tq0ccrk regi ster is less than the set value of the tq0ccr0 register, the inttq0cck signal is generated once per cycle. at the same ti me, the output of the topq0k pin is inverted. the toq0k pin outputs a square wave with the sa me cycle as that output by the toq00 pin. remark k = 1 to 3 figure 8-7. timing chart when d 01 d k1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal tq0ccr1 register toq01 pin output inttq0cc1 signal tq0ccr2 register toq02 pin output inttq0cc2 signal tq0ccr3 register toq03 pin output inttq0cc3 signal
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 305 of 870 sep 30, 2010 if the set value of the tq0ccrk regist er is greater than the set value of the tq0ccr0 register, the count value of the 16-bit counter does not match the value of the tq0ccrk register. consequently, the inttq0cck signal is not generated, nor is the ou tput of the toq0k pin changed. remark k = 1 to 3 figure 8-8. timing chart when d 01 < d k1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal tq0ccr1 register toq01 pin output inttq0cc1 signal tq0ccr2 register toq02 pin output inttq0cc2 signal tq0ccr3 register toq03 pin output inttq0cc3 signal
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 306 of 870 sep 30, 2010 8.5.2 external event count mode (tq0md2 to tq0md0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tq0ctl0.tq0ce bit is set to 1, and an interrupt reques t signal (inttq0cc0) is generated each time the specified number of edges have been counted . the toq00 pin cannot be used. usually, the tq0ccr1 to tq0ccr3 registers are not used in the external event count mode. figure 8-9. configuration in external event count mode 16-bit counter ccr0 buffer register tq0ce bit tq0ccr0 register edge detector clear match signal inttq0cc0 signal tiq00 pin (external event count input) figure 8-10. basic timing in external event count mode ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal d 0 d 0 d 0 d 0 16-bit counter tq0ccr0 register inttq0cc0 signal external event count input (tiq00 pin input) d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) remark this figure shows the basic timing when the risi ng edge is specified as the valid edge of the external event count input.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 307 of 870 sep 30, 2010 when the tq0ce bit is set to 1, the value of the 16-bit co unter is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count input is dete cted. additionally, the set value of the tq0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttq0cc0) is generated. the inttq0cc0 signal is generated each time the valid edge of the external event count input has been detected (set value of tq0ccr0 register + 1) times. figure 8-11. register setting for operati on in external event count mode (1/2) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 0: stop counting 1: enable counting 000 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 00000 tq0ctl1 0, 0, 1: external event count mode 001 tq0md2 tq0md1 tq0md0 tq0eee tq0est (c) tmq0 i/o control register 0 (tq0ioc0) 00000 tq0ioc0 0: disable toq00 pin output 0: disable toq01 pin output 000 tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 0: disable toq02 pin output 0: disable toq03 pin output (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the count value of the 16-bit counter can be read by reading the tq0cnt register.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 308 of 870 sep 30, 2010 figure 8-11. register setting for operati on in external event count mode (2/2) (f) tmq0 capture/compare register 0 (tq0ccr0) if d 0 is set to the tq0ccr0 register, the counter is cleared and a compare match interrupt request signal (inttq0cc0) is generated when the number of external event counts reaches (d 0 + 1). (g) tmq0 capture/compare regist ers 1 to 3 (tq0ccr1 to tq0ccr3) usually, the tq0ccr1 to tq0ccr3 registers are not us ed in the external event count mode. however, the set value of the tq0ccr1 to tq0ccr3 regist ers are transferred to the ccr1 to ccr3 buffer registers. when the count value of the 16-bit counter matches the value of the ccr1 to ccr3 buffer registers, compare match interrupt request si gnals (inttq0cc1 to inttq0cc3) are generated. therefore, mask the interrupt signal by using t he interrupt mask flags (t q0ccmk1 to tq0ccmk3). caution when an external clock is used as the count clock, the external clock can be input only from the tiq00 pin. at this time, set the tq0ioc1.tq0is1 and tq0ioc1.tq0is0 bits to 00 (capture trigger input (tiq00 pin): no edge detection). remark the tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the external event count mode.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 309 of 870 sep 30, 2010 (1) external event count mode operation flow figure 8-12. flow of software processing in external event count mode ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tq0ce bit = 1 tq0ce bit = 0 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0ccr0 register initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). the counter is initialized and counting is stopped by clearing the tq0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 310 of 870 sep 30, 2010 (2) operation timing in external event count mode cautions 1. in the external event count mode , do not set the tq0ccr0 register to 0000h. 2. in the external event count mode, use of th e timer output is disabled. if performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (tq0ctl1.tq0md2 to tq0ctl1.tq0md0 bits = 000, tq0ctl1.tq0eee bit = 1). (a) operation if tq0ccr0 re gister is set to ffffh if the tq0ccr0 register is set to ffffh, the 16-bit c ounter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-b it counter is cleared to 0000h in synchronization with the next count-up timing, and the inttq0cc0 signal is gen erated. at this time, t he tq0opt0.tq0ovf bit is not set. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 311 of 870 sep 30, 2010 (b) notes on rewriting the tq0ccr0 register to change the value of the tq0ccr0 register to a sm aller value, stop counting once and then change the set value. if the value of the tq0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) if the value of the tq0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as t he tq0ccr0 register has been rewritten. consequently, the value that is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter co unts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttq0cc0 signal is generated. therefore, the inttq0cc0 signal may not be generated at the va lid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 312 of 870 sep 30, 2010 (c) operation of tq0ccr1 to tq0ccr3 registers figure 8-13. configuration of tq0ccr1 to tq0ccr3 registers ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal inttq0cc3 signal tiq00 pin tq0ccr1 register ccr1 buffer register match signal inttq0cc1 signal tq0ccr3 register ccr3 buffer register match signal inttq0cc2 signal tq0ccr2 register ccr2 buffer register match signal 16-bit counter edge detector
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 313 of 870 sep 30, 2010 if the set value of the tq0ccrk register is smalle r than the set value of the tq0ccr0 register, the inttq0cck signal is generated once per cycle. remark k = 1 to 3 figure 8-14. timing chart when d 01 d k1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal tq0ccr1 register inttq0cc1 signal tq0ccr2 register inttq0cc2 signal tq0ccr3 register inttq0cc3 signal
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 314 of 870 sep 30, 2010 if the set value of the tq0ccrk register is greater than the set value of the tq0ccr0 register, the inttq0cck signal is not generated because the count value of the 16-bit count er and the value of the tq0ccrk register do not match. remark k = 1 to 3 figure 8-15. timing chart when d 01 < d k1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal tq0ccr1 register inttq0cc1 signal tq0ccr2 register inttq0cc2 signal tq0ccr3 register inttq0cc3 signal
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 315 of 870 sep 30, 2010 8.5.3 external trigger pulse output m ode (tq0md2 to tq0md0 bits = 010) in the external trigger pulse output mode, 16-bit timer/ev ent counter q waits for a trig ger when the tq0ctl0.tq0ce bit is set to 1. when the valid edge of an external trigger input signal is detected, 16-bit timer/ event counter q starts counting , and outputs a pwm waveform from the toq01 to toq03 pins. pulses can also be output by generating a software trigger inst ead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the toq00 pin. figure 8-16. configuration in external trigger pulse output mode ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin tiq00 pin transfer s r tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal transfer transfer s r tq0ccr3 register ccr3 buffer register match signal transfer toq02 pin inttq0cc2 signal s r tq0ccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control edge detector software trigger generation output controller (rs-ff) output controller output controller (rs-ff) output controller
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 316 of 870 sep 30, 2010 figure 8-17. basic timing in exte rnal trigger pulse output mode d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 1 d 2 d 3 active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 3 ) active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) wait for trigger active level width (d 3 ) cycle (d 0 + 1) ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register inttq0cc0 signal toq00 pin output (only when software trigger is used) tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) d 0 d 1 d 3 d 2 d 0 d 0 d 0 d 0 16-bit timer/event counter q waits for a trigger when the tq0ce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counting at the same time, and out puts a pwm waveform from the toq0k
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 317 of 870 sep 30, 2010 pin. if the trigger is generated again while the counter is o perating, the counter is cleared to 0000h and restarted. (the output of the toq00 pin is invert ed. the toq0k pin outputs a high-level regardl ess of the status (high/low) when a trigger is generated.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tq0ccrk register) count clock cycle cycle = (set value of tq0ccr0 register + 1) count clock cycle duty factor = (set value of tq0ccrk regist er)/(set value of tq0ccr0 register + 1) the compare match request signal inttq0cc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and t he 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttq0cck is generated when the count value of the 16-bit counter matches the value of the ccrk buffer register. the value set to the tq0ccrm register is transferred to th e ccrm buffer register when the count value of the 16-bit counter matches the value of the ccr0 buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal, or setting the software trigger (tq0ctl1.tq0est bit) to 1 is used as the trigger. remark k = 1 to 3, m = 0 to 3 figure 8-18. register setting for operation in external trigger pulse output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 318 of 870 sep 30, 2010 figure 8-18. register setting for operation in external trigger pulse output mode (2/3) (b) tmq0 control register 1 (tq0ctl1) 00000 tq0ctl1 generate software trigger when 1 is written 010 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0, 1, 0: external trigger pulse output mode (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output 1: enable toq00 pin output setting of output level while operation of toq00 pin is disabled 0: low level 1: high level 0: disable toq01 pin output 1: enable toq01 pin output specification of active level of toq01 pin output 0: active-high 1: active-low 0/1 0/1 note 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 toq0k pin output 16-bit counter ? when tq0olk bit = 0 toq0k pin output 16-bit counter ? when tq0olk bit = 1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 specification of active level of toq03 pin output 0: active-high 1: active-low 0: disable toq02 pin output 1: enable toq02 pin output specification of active level of toq02 pin output 0: active-high 1: active-low 0: disable toq03 pin output 1: enable toq03 pin output note clear this bit to 0 when the toq00 pin is not used in the external trigger pulse output mode.
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 319 of 870 sep 30, 2010 figure 8-18. register setting for operation in external trigger pulse output mode (3/3) (d) tmq0 i/o control register 2 (tq0ioc2) 00000 tq0ioc2 select valid edge of external trigger input 0 0/1 0/1 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) if d 0 is set to the tq0ccr0 register, d 1 to the tq0ccr1 register, d 2 to the tq0ccr2 register, and d 3 , to the tq0ccr3 register, the cycle and active le vel of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle toq01 pin pwm waveform active level width = d 1 count clock cycle toq02 pin pwm waveform active level width = d 2 count clock cycle toq03 pin pwm waveform active level width = d 3 count clock cycle remarks 1. tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the external trigger pulse output mode. 2. updating tmq0 capture/compare register 2 (tq0ccr2) and tmq0 capture/compare register 3 (tq0ccr3) is validated by writing tmq0 capture/compare register 1 (tq0ccr1).
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 320 of 870 sep 30, 2010 (1) operation flow in extern al trigger pulse output mode figure 8-19. software processing flow in ex ternal trigger pulse output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register ccr0 buffer register inttq0cc0 signal toq00 pin output (only when software trigger is used) tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 11 d 20 d 10
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 321 of 870 sep 30, 2010 figure 8-19. software processing flow in ex ternal trigger pulse output mode (2/2) start <1> count operation start flow tq0ce bit = 1 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. writing of the tq0ccr1 register must be performed when the set duty factor is only changed after writing the tq0ccr2 and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. tq0ccr1 register writing of the same value is necessary only when the set duty factor of toq02 and toq03 pin outputs is changed. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. only writing of the tq0ccr1 register must be performed when the set duty factor is only changed. when counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. counting is stopped. the tq0cks0 to tq0cks2 bits can be set at the same time when counting is enabled (tq0ce bit = 1). trigger wait status writing of the tq0ccr1 register must be performed after writing the tq0ccr0, tq0ccr2, and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer registers. tq0ccr1 register writing of the same value is necessary only when the set cycle is changed. <2> tq0ccr0 to tq0ccr3 register setting change flow <3> tq0ccr0 register setting change flow <4> tq0ccr1 to tq0ccr3 register setting change flow <5> tq0ccr2, tq0ccr3 register setting change flow <6> tq0ccr1 register setting change flow <7> count operation stop flow tq0ce bit = 0 setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register stop setting of tq0ccr1 register setting of tq0ccr0 register setting of tq0ccr1 register setting of tq0ccr0, tq0ccr2, and tq0ccr3 registers tq0ccr1 register when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. remark m = 0 to 3
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 322 of 870 sep 30, 2010 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tq0ccr1 register last. rewrite the tq0ccrk register after writing the tq0ccr 1 register after the inttq0cc0 signal is detected. ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tq0ccr0 register ccr0 buffer register inttq0cc0 signal tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output toq00 pin output (only when software trigger is used) d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 323 of 870 sep 30, 2010 in order to transfer data from the tq0ccrm register to the ccrm buffer register, the tq0ccr1 register must be written. to change both the cycle and active level width of the pw m waveform at this time, first set the cycle to the tq0ccr0 register, set the active level width to the tq0ccr2 and tq0ccr3 registers, and then set an active level to the tq0ccr1 register. to change only the cycle of the pwm waveform, first se t the cycle to the tq0ccr0 re gister, and then write the same value to the tq0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, first set an active level to the tq0ccr2 and tq0ccr3 registers and then set an active level to the tq0ccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the toq01 pin, only the tq0ccr1 register has to be set. to change only the active level width (duty factor) of the pwm waveform output by the toq02 and toq03 pins, first set an active level width to the tq0ccr2 and tq0c cr3 registers, and then write the same value to the tq0ccr1 register. after data is written to the tq0ccr1 register, the value written to the tq0ccrm regi ster is transferred to the ccrm buffer register in synchronization with clearing of the 16-bit counter, and is us ed as the value compared with the 16-bit counter. to write the tq0ccr0 to tq0ccr3 registers again afte r writing the tq0ccr1 register once, do so after the inttq0cc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because timing of transferring data from the tq0ccrm register to the ccrm buffer register conflicts with writing the tq0ccrm register. remark m = 0 to 3
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 324 of 870 sep 30, 2010 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tq0ccrk register to 0000h. if the set value of the tq0ccr0 register is ffffh, the inttq0cck signal is generated periodically. count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 l remark k = 1 to 3 to output a 100% waveform, set a value of (set value of tq0ccr0 register + 1) to the tq0ccrk register. if the set value of the tq0ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 325 of 870 sep 30, 2010 (c) conflict between trigger detection and match with ccrk buffer register if the trigger is detected immediately after the in ttq0cck signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the toq0k pin is a sserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccrk buffer register inttq0cck signal toq0k pin output external trigger input (tiq00 pin input) d k d k ? 1 0000 ffff 0000 shortened d k remark k = 1 to 3 if the trigger is detected immediatel y before the inttq0cck signal is gene rated, the inttq0cck signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. the output signal of the toq0k pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter ccrk buffer register inttq0cck signal toq0k pin output external trigger input (tiq00 pin input) d k d k ? 2d k ? 1d k 0000 ffff 0000 0001 extended remark k = 1 to 3
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 326 of 870 sep 30, 2010 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the inttq0cc0 signal is generated, the 16- bit counter is cleared to 0000h and continues counting up. therefore, the active period of the toq0k pin is extended by time from generation of the inttq0cc0 signal to trigger detection. 16-bit counter ccr0 buffer register inttq0cc0 signal toq0k pin output external trigger input (tiq00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark k = 1 to 3 if the trigger is detected immediately before the inttq0cc0 signal is generated, the inttq0cc0 signal is not generated. the 16-bit counter is cleared to 0000h, t he toq0k pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccr0 buffer register inttq0cc0 signal toq0k pin output external trigger input (tiq00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark k = 1 to 3
v850es/jg3 chapter 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 327 of 870 sep 30, 2010 (e) generation timing of compare match interrupt request signal (inttq0cck) the timing of generation of the inttq 0cck signal in the external trigger pulse output mode differs from the timing of other inttq0cck signals; the inttq0cck si gnal is generated when the count value of the 16-bit counter matches the value of the ccrk buffer register. count clock 16-bit counter ccrk buffer register toq0k pin output inttq0cck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 remark k = 1 to 3 usually, the inttq0cck signal is generated in synchronization with the next count up after the count value of the 16-bit counter matches the valu e of the ccrk buffer register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of changin g the output signal of the toq0k pin.
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 328 of 870 sep 30, 2010 8.5.4 one-shot pulse output mode (tq0md2 to tq0md0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event counter q waits for a trigger when t he tq0ctl0.tq0ce bit is set to 1. when the valid edge of an external trigger input is de tected, 16-bit timer/event counter q starts counting, and outputs a one-shot pulse from the toq01 to toq03 pins. instead of the external trigger, a software trigger can al so be generated to output the pulse. when the software trigger is used, the toq00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 8-20. configuration in one-shot pulse output mode ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin tiq00 pin transfer s r s r tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal transfer transfer s r tq0ccr3 register ccr3 buffer register match signal transfer toq02 pin inttq0cc2 signal s r tq0ccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control edge detector software trigger generation output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) output controller (rs-ff)
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 329 of 870 sep 30, 2010 figure 8-21. basic timing in one-shot pulse output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register inttq0cc0 signal tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output tq0ccr1 register inttq0cc1 signal toq01 pin output toq00 pin output (only when software trigger is used)
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 330 of 870 sep 30, 2010 when the tq0ce bit is set to 1, 16-bit timer/event counter q waits for a trigger. when the trigger is generated, the 16- bit counter is cleared from ffffh to 0000h, starts counting, and outputs a one-shot pulse from the toq0k pin. after the one-shot pulse is output, the 16-bit counter is set to ffffh, stops counting, and waits for a trigger. if a trigger is generated again while the one-shot pul se is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tq0ccrk register) count clock cycle active level width = (set value of tq0ccr0 register ? set value of tq0ccrk register + 1) count clock cycle the compare match interrupt request signal inttq0cc0 is generated when the 16-bit counter counts after its count value matches the value of the ccr0 buffer register. the compare match interrupt request signal inttq0cck is generated when the count value of the 16-bit counter matches the val ue of the ccrk buffer register. the valid edge of an external trigger input or setting the so ftware trigger (tq0ctl1.tq0est bit) to 1 is used as the trigger. remark k = 1 to 3 figure 8-22. register setting for operati on in one-shot pulse output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 0 0/1 0 0 0 tq0ctl1 generate software trigger when 1 is written 011 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0, 1, 1: one-shot pulse output mode
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 331 of 870 sep 30, 2010 figure 8-22. register setting for operati on in one-shot pulse output mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) toq0k pin output 16-bit counter ? when tq0olk bit = 0 toq0k pin output 16-bit counter ? when tq0olk bit = 1 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output 1: enable toq00 pin output setting of output level while operation of toq00 pin is disabled 0: low level 1: high level 0: disable toq01 pin output 1: enable toq01 pin output specification of active level of toq01 pin output 0: active-high 1: active-low 0/1 0/1 note 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 specification of active level of toq03 pin output 0: active-high 1: active-low 0: disable toq02 pin output 1: enable toq02 pin output specification of active level of toq02 pin output 0: active-high 1: active-low 0: disable toq03 pin output 1: enable toq03 pin output (d) tmq0 i/o control register 2 (tq0ioc2) 00000 tq0ioc2 select valid edge of external trigger input 0 0/1 0/1 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. note clear this bit to 0 when the toq00 pin is not used in the one-shot pulse output mode.
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 332 of 870 sep 30, 2010 figure 8-22. register setting for operati on in one-shot pulse output mode (3/3) (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) if d 0 is set to the tq0ccr0 register and d k to the tq0ccrk register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 0 ? d k + 1) count clock cycle output delay period = (d k ) count clock cycle caution one-shot pulses are not output even in th e one-shot pulse output mode, if the value set in the tq0ccrk register is greater th an that set in the tq0ccr0 register. remarks 1. tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the one-shot pulse output mode. 2. k = 1 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 333 of 870 sep 30, 2010 (1) operation flow in one-shot pulse output mode figure 8-23. software processing flow in one-shot pulse output mode (1/2) ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register inttq0cc0 signal toq00 pin output (only when software trigger is used) tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30 d 10 d 20 d 30 d 11 d 21 d 31 d 00 d 01 <3> <1> <2>
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 334 of 870 sep 30, 2010 figure 8-23. software processing flow in one-shot pulse output mode (2/2) tq0ce bit = 1 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). trigger wait status start <1> count operation start flow tq0ce bit = 0 count operation is stopped stop <3> count operation stop flow setting of tq0ccr0 to tq0ccr3 registers as rewriting the tq0ccrm register immediately forwards to the ccrm buffer register, rewriting immediately after the generation of the inttq0ccr0 signal is recommended. <2> tq0ccr0 to tq0ccr3 register setting change flow remark m = 0 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 335 of 870 sep 30, 2010 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tq0ccrm register to change the set value of the tq0 ccrm register to a smaller value, stop counting once, and then change the set value. if the value of the tq0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. d k0 d k1 d 01 d 01 d 00 d k1 d 01 d k0 d k0 d k1 d 00 d 00 ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register inttq0cc0 signal toq00 pin output (only when software trigger is used) tq0ccrk register inttq0cck signal toq0k pin output delay (d k0 ) active level width (d 00 ? d k0 + 1) active level width (d 01 ? d k1 + 1) active level width (d 01 ? d k1 + 1) delay (d k1 ) delay (10000h + d k1 ) when the tq0ccr0 register is rewritten from d 00 to d 01 and the tq0ccrk register from d k0 to d k1 where d 00 > d 01 and d k0 > d k1 , if the tq0ccrk register is rewritten when t he count value of the 16-bit counter is greater than d k1 and less than d k0 and if the tq0ccr0 register is rewritt en when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter counts up to ffffh and t hen counts up again from 0000h. when the count value matches d k1 , the counter generates the inttq0cck signal and asserts the toq0k pin. when the count value matches d 01 , the counter generates the in ttq0cc0 signal, deasserts the toq0k pin, and stops counting. therefore, the counter may output a pul se with a delay period or active per iod different from that of the one- shot pulse that is originally expected. remark k = 1 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 336 of 870 sep 30, 2010 (b) generation timing of compare match interrupt request signal (inttq0cck) the generation timing of the inttq0cck signal in the one-shot pulse output mode is different from other inttq0cck signals; the inttq0cck signal is generated when the count value of the 16-bit counter matches the value of the tq0ccrk register. count clock 16-bit counter tq0ccrk register toq0k pin output inttq0cck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 usually, the inttq0cck signal is generated when the 16-b it counter counts up next time after its count value matches the value of the tq0ccrk register. in the one-shot pulse output mode, however, it is gene rated one clock earlier. this is because the timing is changed to match the change timing of the toq0k pin. remark k = 1 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 337 of 870 sep 30, 2010 8.5.5 pwm output mode (tq0md 2 to tq0md0 bits = 100) in the pwm output mode, a pwm waveform is output from the toq01 to toq03 pins when the tq0ctl0.tq0ce bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the toq00 pin. figure 8-24. configuration in pwm output mode ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin transfer s r tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal transfer transfer s r tq0ccr3 register ccr3 buffer register match signal transfer toq02 pin inttq0cc2 signal s r tq0ccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control output controller (rs-ff) output controller output controller (rs-ff) output controller (rs-ff)
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 338 of 870 sep 30, 2010 figure 8-25. basic timing in pwm output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal toq00 pin output tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 3 ) active level width (d 3 ) active level width (d 3 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 )
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 339 of 870 sep 30, 2010 when the tq0ce bit is set to 1, the 16-bit counter is cl eared from ffffh to 0000h, star ts counting, and outputs pwm waveform from the toq0k pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tq0ccrk register ) count clock cycle cycle = (set value of tq0ccr0 register + 1) count clock cycle duty factor = (set value of tq0ccrk regist er)/(set value of tq0ccr0 register + 1) the pwm waveform can be changed by rewriting the tq0ccrm register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttq0cc0 is gener ated when the 16-bit counter counts next time after its count value matches the value of the ccr 0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttq0cck is generated when the count value of the 16-bit c ounter matches the value of the ccrk buffer register. remark k = 1 to 3, m = 0 to 3 figure 8-26. register setting for op eration in pwm output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 0 0 tq0ctl1 100 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 0, 0: pwm output mode 0: operate on count clock selected by tq0cks0 to tq0cks2 bits 1: count external event input signal note the setting is invalid when the tq0ctl1.tq0eee bit = 1.
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 340 of 870 sep 30, 2010 figure 8-26. register setting for op eration in pwm output mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) toq0k pin output 16-bit counter ? when tq0olk bit = 0 toq0k pin output 16-bit counter ? when tq0olk bit = 1 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output 1: enable toq00 pin output setting of output level while operation of toq00 pin is disabled 0: low level 1: high level 0: disable toq01 pin output 1: enable toq01 pin output specification of active level of toq01 pin output 0: active-high 1: active-low 0/1 0/1 note 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 specification of active level of toq03 pin output 0: active-high 1: active-low 0: disable toq02 pin output 1: enable toq02 pin output specification of active level of toq02 pin output 0: active-high 1: active-low 0: disable toq03 pin output 1: enable toq03 pin output (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input. 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. note clear this bit to 0 when the toq00 pin is not used in the pwm output mode.
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 341 of 870 sep 30, 2010 figure 8-26. register setting for op eration in pwm output mode (3/3) (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) if d 0 is set to the tq0ccr0 register and d k to the tq0ccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d k count clock cycle remarks 1. tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the pwm output mode. 2. updating the tmq0 capture/compare regist er 2 (tq0ccr2) and tmq0 capture/compare register 3 (tq0ccr3) is validated by writ ing the tmq0 capture/compare register 1 (tq0ccr1).
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 342 of 870 sep 30, 2010 (1) operation flow in pwm output mode figure 8-27. software processing flow in pwm output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register ccr0 buffer register inttq0cc0 signal toq00 pin output tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 10 d 20
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 343 of 870 sep 30, 2010 figure 8-27. software processing flow in pwm output mode (2/2) start <1> count operation start flow tq0ce bit = 1 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. only writing of the tq0ccr1 register must be performed when the set duty factor is only changed after writing the tq0ccr2 and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. tq0ccr1 register writing of the same value is necessary only when the set duty factor of toq02 and toq03 pin outputs is changed. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. only writing of the tq0ccr1 register must be performed when the set duty factor is only changed. when counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. counting is stopped. the tq0cks0 to tq0cks2 bits can be set at the same time when counting is enabled (tq0ce bit = 1). writing of the tq0ccr1 register must be performed after writing the tq0ccr0, tq0ccr2, and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer registers. tq0ccr1 writing of the same value is necessary only when the set cycle is changed. <2> tq0ccr0 to tq0ccr3 register setting change flow <3> tq0ccr0 register setting change flow <4> tq0ccr1 to tq0ccr3 register setting change flow <5> tq0ccr2, tq0ccr3 register setting change flow <6> tq0ccr1 register setting change flow <7> count operation stop flow tq0ce bit = 0 setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register stop setting of tq0ccr1 register setting of tq0ccr0 register setting of tq0ccr1 register setting of tq0ccr0, tq0ccr2, and tq0ccr3 registers tq0ccr1 register when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. remark k = 1 to 3 m = 0 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 344 of 870 sep 30, 2010 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tq0ccr1 register last. rewrite the tq0ccrk register after writing the tq0ccr 1 register after the inttq0cc1 signal is detected. ffffh 16-bit counter 0000h tq0ce bit d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tq0ccr0 register ccr0 buffer register inttq0cc0 signal tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output toq00 pin output d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 345 of 870 sep 30, 2010 to transfer data from the tq0ccrm register to the ccrm buffer register, the tq0ccr1 register must be written. to change both the cycle and active level of the pwm wavefo rm at this time, first set the cycle to the tq0ccr0 register, set the active level width to the tq0ccr2 an d tq0ccr3 registers, and then set an active level width to the tq0ccr1 register. to change only the active level width (duty factor) of pw m wave, first set the active level to the tq0ccr2 and tq0ccr3 registers, and then set an active level to the tq0ccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the toq01 pin, only the tq0ccr1 register has to be set. to change only the active level width (duty factor) of the pwm waveform output by the toq02 and toq03 pins, first set an active level width to the tq0ccr2 and tq0c cr3 registers, and then write the same value to the tq0ccr1 register. after the tq0ccr1 register is writt en, the value written to the tq0ccrm register is transferred to the ccrm buffer register in synchronization with the timing of cl earing the 16-bit counter, and is used as a value to be compared with the value of the 16-bit counter. to change only the cycle of the pwm waveform, first se t a cycle to the tq0ccr0 register, and then write the same value to the tq0ccr1 register. to write the tq0ccr0 to tq0ccr3 registers again afte r writing the tq0ccr1 register once, do so after the inttq0cc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the tq0ccrm register to the ccrm buffer register conflicts with writing the tq0ccrm register. remark m = 0 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 346 of 870 sep 30, 2010 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tq0ccrk register to 0000h. if the set value of the tq0ccr0 register is ffffh, the inttq0cck signal is generated periodically. count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3 to output a 100% waveform, set a value of (set value of tq0ccr0 register + 1) to the tq0ccrk register. if the set value of the tq0ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 347 of 870 sep 30, 2010 (c) generation timing of compare match interrupt request signal (inttq0cck) the timing of generation of the inttq0cck signal in t he pwm output mode differs from the timing of other inttq0cck signals; the inttq0cck signal is generated when the count value of the 16-bit counter matches the value of the tq0ccrk register. count clock 16-bit counter ccrk buffer register toq0k pin output inttq0cck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 remark k = 1 to 3 usually, the inttq0cck signal is generated in synchroni zation with the next counti ng up after the count value of the 16-bit counter matches the value of the tq0ccrk register. in the pwm output mode, however, it is generated one cl ock earlier. this is because the timing is changed to match the change timing of the out put signal of the toq0k pin.
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 348 of 870 sep 30, 2010 8.5.6 free-running timer mode (t q0md2 to tq0md0 bits = 101) in the free-running timer mode, 16-bit timer/event counter q starts counting when the tq0ct l0.tq0ce bit is set to 1. at this time, the tq0ccrm register can be used as a compare register or a capture register , depending on the setting of the tq0opt0.tq0ccs0 and tq0opt0.tq0ccs1 bits. remark m = 0 to 3 figure 8-28. configuration in free-running timer mode toq03 pin output toq02 pin output toq01 pin output toq00 pin output inttq0ov signal tq0ccs0, tq0ccs1 bits (capture/compare selection) inttq0cc3 signal inttq0cc2 signal inttq0cc1 signal inttq0cc0 signal tiq03 pin (capture trigger input) tq0ccr3 register (capture) tiq00 pin (external event count input/ capture trigger input) internal count clock tq0ce bit tiq01 pin (capture trigger input) tiq02 pin (capture trigger input) tq0ccr0 register (capture) tq0ccr1 register (capture) tq0ccr2 register (capture) tq0ccr3 register (compare) tq0ccr2 register (compare) tq0ccr1 register (compare) 0 1 0 1 0 1 0 1 16-bit counter tq0ccr0 register (compare) output controller output controller output controller output controller count clock selection edge detector edge detector edge detector edge detector edge detector
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 349 of 870 sep 30, 2010 when the tq0ce bit is set to 1, 16-bit timer/event counter q starts counting, and the out put signals of the toq00 to toq03 pins are inverted. when the count value of the 16-bit counter later matches the set va lue of the tq0ccrm register, a compare match interrupt request signal (inttq0ccm) is gener ated, and the output signal of the toq0m pin is inverted. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttq0ov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tq0opt0.t q0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the tq0ccrm register can be rewritten while the counter is operating. if it is re written, the new value is reflected at that time, and compared with the count value. figure 8-29. basic timing in free-r unning timer mode (compare function) d 10 d 20 d 30 d 00 d 20 d 31 d 31 d 30 d 00 d 11 d 11 d 21 d 01 d 11 d 21 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output inttq0ov signal tq0ovf bit toq00 pin output tq0ccr1 register inttq0cc1 signal tq0ce bit tq0ccr0 register inttq0cc0 signal d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 350 of 870 sep 30, 2010 when the tq0ce bit is set to 1, the 16- bit counter starts counti ng. when the valid edge input to the tiq0m pin is detected, the count value of the 16-bit counter is stored in the tq0ccrm register, and a capture interrupt request signal (inttq0ccm) is generated. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttq0ov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tq0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction b y software. figure 8-30. basic timing in free-r unning timer mode (capture function) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tiq02 pin input tq0ccr2 register inttq0cc2 signal tiq03 pin input tq0ccr3 register inttq0cc3 signal inttq0ov signal tq0ovf bit tiq01 pin input tq0ccr1 register inttq0cc1 signal tq0ce bit tiq00 pin input tq0ccr0 register inttq0cc0 signal
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 351 of 870 sep 30, 2010 figure 8-31. register setting in free-running timer mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce note the setting is invalid when the tq0ctl1.tq0eee bit = 1 (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 0 0 tq0ctl1 101 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 0, 1: free-running mode 0: operate with count clock selected by tq0cks0 to tq0cks2 bits 1: count on external event count input signal
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 352 of 870 sep 30, 2010 figure 8-31. register setting in free-running timer mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output 1: enable toq00 pin output 0: disable toq01 pin output 1: enable toq01 pin output setting of output level with operation of toq01 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 setting of output level with operation of toq03 pin disabled 0: low level 1: high level 0: disable toq02 pin output 1: enable toq02 pin output setting of output level with operation of toq02 pin disabled 0: low level 1: high level 0: disable toq03 pin output 1: enable toq03 pin output setting of output level with operation of toq00 pin disabled 0: low level 1: high level (d) tmq0 i/o control register 1 (tq0ioc1) 0/1 0/1 0/1 0/1 0/1 tq0ioc1 select valid edge of tiq00 pin input select valid edge of tiq01 pin input 0/1 0/1 0/1 tq0is2 tq0is1 tq0is0 tq0is3 tq0is6 tq0is5 tq0is4 tq0is7 select valid edge of tiq02 pin input select valid edge of tiq03 pin input
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 353 of 870 sep 30, 2010 figure 8-31. register setting in free-running timer mode (3/3) (e) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (f) tmq0 option register 0 (tq0opt0) 0/1 0/1 0/1 0/1 0 tq0opt0 overflow flag specifies if tq0ccr0 register functions as capture or compare register specifies if tq0ccr1 register functions as capture or compare register 0 0 0/1 tq0ccs0 tq0ovf tq0ccs1 tq0ccs2 tq0ccs3 specifies if tq0ccr2 register functions as capture or compare register specifies if tq0ccr3 register functions as capture or compare register (g) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. (h) tmq0 capture/compare regist ers 0 to 3 (tq0ccr0 to tq0ccr3) these registers function as capture registers or compare regi sters depending on the setting of the tq0opt0.tq0ccsm bit. when the registers function as capture registers, they store the c ount value of the 16-bit counter when the valid edge input to the tiq0m pin is detected. when the registers function as compare registers and when d m is set to the tq0ccrm register, the inttq0ccm signal is generated when the counter reaches (d m + 1), and the output signal of the toq0m pin is inverted. remark m = 0 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 354 of 870 sep 30, 2010 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 8-32. software processing flow in fr ee-running timer mode (c ompare function) (1/2) d 10 d 20 d 30 d 00 d 10 d 20 d 30 d 00 d 11 d 31 d 01 d 21 d 21 d 11 d 11 d 31 d 01 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal toq00 pin output tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output inttq0ov signal tq0ovf bit d 00 d 10 d 20 d 30 d 01 d 11 d 21 d 31 cleared to 0 by clr instruction set value changed set value changed set value changed set value changed cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2>
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 355 of 870 sep 30, 2010 figure 8-32. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tq0ce bit = 1 read tq0opt0 register (check overflow flag). register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0opt0 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). start execute instruction to clear tq0ovf bit (clr tq0ovf). <1> count operation start flow <2> overflow flag clear flow tq0ce bit = 0 counter is initialized and counting is stopped by clearing tq0ce bit to 0. stop <3> count operation stop flow tq0ovf bit = 1 no yes
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 356 of 870 sep 30, 2010 (b) when using capture/compare register as capture register figure 8-33. software processing flow in fr ee-running timer mode (c apture function) (1/2) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 0000 0000 0000 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> ffffh 16-bit counter 0000h tq0ce bit tiq02 pin input tq0ccr2 register inttq0cc2 signal tiq03 pin input tq0ccr3 register inttq0cc3 signal inttq0ov signal tq0ovf bit tiq01 pin input tq0ccr1 register inttq0cc1 signal tiq00 pin input tq0ccr0 register inttq0cc0 signal
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 357 of 870 sep 30, 2010 figure 8-33. software processing flow in fr ee-running timer mode (c apture function) (2/2) tq0ce bit = 1 read tq0opt0 register (check overflow flag). register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc1 register, tq0opt0 register initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). start execute instruction to clear tq0ovf bit (clr tq0ovf). <1> count operation start flow <2> overflow flag clear flow tq0ce bit = 0 counter is initialized and counting is stopped by clearing tq0ce bit to 0. stop <3> count operation stop flow tq0ovf bit = 1 no yes
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 358 of 870 sep 30, 2010 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter q is used as an interval timer with the tq0ccrm register used as a compare register, software processing is necessary for setting a co mparison value to generate the next interrupt request signal each time the inttq0ccm signal has been detected. d 00 d 10 d 20 d 01 d 30 d 12 d 03 d 22 d 31 d 21 d 23 d 02 d 13 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal toq00 pin output tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output interval period (d 00 + 1) interval period (10000h + d 02 ? d 01 ) interval period (d 01 ? d 00 ) interval period (d 03 ? d 02 ) interval period (d 04 ? d 03 ) d 00 d 01 d 02 d 03 d 04 d 05 interval period (d 10 + 1) interval period (10000h + d 12 ? d 11 ) interval period (d 11 ? d 10 ) interval period (d 13 ? d 12 ) d 10 d 11 d 12 d 13 d 14 interval period (d 20 + 1) interval period (10000h + d 21 ? d 20 ) interval period (10000h + d 23 ? d 22 ) interval period (d 22 ? d 21 ) interval period (d 30 + 1) interval period (10000h + d 31 ? d 30) d 20 d 21 d 22 d 23 d 31 d 30 d 32 d 04 d 11
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 359 of 870 sep 30, 2010 when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the co rresponding tq0ccrm register must be re-set in the interrupt servicing that is executed when the inttq0ccm signal is detected. the set value for re-setting the tq0ccrm register ca n be calculated by the following expression, where ?d m ? is the interval period. compare register default value: d m ? 1 value set to compare register second and subsequent time: previous set value + d m (if the calculation resu lt is greater than ffffh, subtract 10000h fr om the result and set this value to the register.) remark m = 0 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 360 of 870 sep 30, 2010 (b) pulse width measurement with capture register when pulse width measurement is performed with the tq 0ccrm register used as a capture register, software processing is necessary for reading the capture regist er each time the inttq0ccm signal has been detected and for calculating an interval. d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 32 d 13 d 03 d 22 d 33 d 23 0000 pulse interval (10000h + d 01 ? d 00 ) pulse interval (10000h + d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) d 00 d 01 d 02 d 03 pulse interval (d 00 + 1) 0000 pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (d 13 ? d 12 ) d 10 d 11 d 12 d 13 pulse interval (d 10 + 1) 0000 pulse interval (10000h + d 21 ? d 20 ) pulse interval (20000h + d 22 ? d 21 ) pulse interval (d 23 ? d 22 ) d 20 d 21 d 23 d 22 pulse interval (d 20 + 1) 0000 pulse interval (10000h + d 31 ? d 30 ) pulse interval (10000h + d 32 ? d 31 ) pulse interval (10000h + d 33 ? d 32 ) d 30 d 31 d 32 d 33 pulse interval (d 30 + 1) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tq0ce bit tiq00 pin input tq0ccr0 register inttq0cc0 signal tiq02 pin input tq0ccr2 register inttq0cc2 signal tiq03 pin input tq0ccr3 register inttq0cc3 signal inttq0ov signal tq0ovf bit tiq01 pin input tq0ccr1 register inttq0cc1 signal
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 361 of 870 sep 30, 2010 when executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calcul ated by reading the value of the tq0ccrm register in synchronization with the inttq0ccm signal, and calcul ating the difference between the read value and the previously read value. remark m = 0 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 362 of 870 sep 30, 2010 (c) processing of overflow when two or more capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when tw o or more capture registers are used ffffh 16-bit counter 0000h tq0ce bit tiq00 pin input tq0ccr0 register tiq01 pin input tq0ccr1 register inttq0ov signal tq0ovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tq0ccr0 register (setting of t he default value of t he tiq00 pin input). <2> read the tq0ccr1 register (setting of t he default value of t he tiq01 pin input). <3> read the tq0ccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tq0ccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtai n the correct pulse width. use software when using two capture registers. an example of how to use software is shown below.
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 363 of 870 sep 30, 2010 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tq0ce bit inttq0ov signal tq0ovf bit tq0ovf0 flag note tiq00 pin input tq0ccr0 register tq0ovf1 flag note tiq01 pin input tq0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tq0ovf0 and tq0ovf1 flags are set on the internal ram by software. <1> read the tq0ccr0 register (setting of t he default value of t he tiq00 pin input). <2> read the tq0ccr1 register (setting of t he default value of t he tiq01 pin input). <3> an overflow occurs. set the tq0ovf0 and tq0ovf1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tq0ccr0 register. read the tq0ovf0 flag. if the tq0o vf0 flag is 1, clear it to 0. because the tq0ovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tq0ccr1 register. read the tq0ovf1 flag. if the tq0ovf1 flag is 1, clear it to 0 (the tq0ovf0 flag is cleared in <4>, and the tq0ovf1 flag remains 1). because the tq0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 364 of 870 sep 30, 2010 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tq0ce bit inttq0ov signal tq0ovf bit tq0ovf0 flag note tiq00 pin input tq0ccr0 register tq0ovf1 flag note tiq01 pin input tq0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tq0ovf0 and tq0ovf1 flags are set on the internal ram by software. <1> read the tq0ccr0 register (setting of t he default value of t he tiq00 pin input). <2> read the tq0ccr1 register (setting of t he default value of t he tiq01 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tq0ccr0 register. read the overflow flag. if the overflow flag is 1, set only the tq0ovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tq0ccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tq0ovf1 flag. if the tq0o vf1 flag is 1, clear it to 0. because the tq0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 365 of 870 sep 30, 2010 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tq0ce bit tiq0m pin input tq0ccrm register inttq0ov signal tq0ovf bit d m0 d m1 d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when a long pulse width in the free-running timer mode. <1> read the tq0ccrm register (setting of t he default value of the tiq0m pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tq0ccrm register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d m1 ? d m0 ) (incorrect). actually, the pulse width must be (20000h + d m1 ? d m0 ) because an overflow occurs twice. if an overflow occurs twice or more when the capture trigge r interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next.
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 366 of 870 sep 30, 2010 example when capture trigger interval is long ffffh 16-bit counter 0000h tq0ce bit tiq0m pin input tq0ccrm register inttq0ov signal tq0ovf bit overflow counter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tq0ccrm register (setting of t he default value of the tiq0m pin input). <2> an overflow occurs. increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tq0ccrm register. read the overflow counter. when the overflow counter is ?n?, the pulse width can be calculated by (n 10000h + d m1 ? d m0 ). in this example, the pulse width is (20000h + d m1 ? d m0 ) because an overflow occurs twice. clear the overflow counter (0h).
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 367 of 870 sep 30, 2010 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tq0o vf bit to 0 with the clr instruction and by writing 8- bit data (bit 0 is 0) to the tq0opt0 r egister. to accurately detect an overflow, read the tq0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tq0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tq0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tq0ovf bit) overflow flag (tq0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without checking if the flag is 1, t he set information of overflow may be erased by writing 0 ((ii) in the above chart) . therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction.
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 368 of 870 sep 30, 2010 8.5.7 pulse width measurement mode (tq0md2 to tq0md0 bits = 110) in the pulse width measurement mode, 16-bit timer/event counter q starts counting wh en the tq0ctl0.tq0ce bit is set to 1. each time the valid edge input to the tiq0m pin ha s been detected, the count value of the 16-bit counter is stored in the tq0ccrm register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by readi ng the tq0ccrm register after a capture interrupt request signal (inttq0ccm) occurs. select either of the tiq00 to tiq03 pins as the capture trigger input pin. specify ?no edge detected? by using the tq0ioc1 register for the unused pins. remark m = 0 to 3 k = 1 to 3 figure 8-34. configuration in pulse width measurement mode inttq0ov signal inttq0cc0 signal inttq0cc1 signal inttq0cc2 signal inttq0cc3 signal tiq03 pin (capture trigger input) tq0ccr3 register (capture) tiq00 pin (external event count input/capture trigger input) internal count clock tq0ce bit tiq01 pin (capture trigger input) tiq02 pin (capture trigger input) tq0ccr0 register (capture) tq0ccr1 register (capture) tq0ccr2 register (capture) 16-bit counter clear edge detector edge detector edge detector edge detector edge detector count clock selection
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 369 of 870 sep 30, 2010 figure 8-35. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tq0ce bit tiq0m pin input tq0ccrm register inttq0ccm signal inttq0ov signal tq0ovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark m = 0 to 3 when the tq0ce bit is set to 1, the 16-bit counter starts counting. when the vali d edge input to the tiq0m pin is later detected, the count value of the 16-bit counter is stored in the tq0ccrm register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttq0ccm) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tiq0m pin even when the 16-bi t counter counted up to ffffh, an overflow interrupt request signal (inttq0ov) is generated at the next count clock, and the count er is cleared to 0000h and continues counting. at this time, the overflow flag (tq0opt0.tq0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tq0ovf bit set (1) count + captured value) count clock cycle remark m = 0 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 370 of 870 sep 30, 2010 figure 8-36. register setting in pu lse width measurement mode (1/2) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 00000 tq0ctl1 110 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 1, 0: pulse width measurement mode (c) tmq0 i/o control register 1 (tq0ioc1) 0/1 0/1 0/1 0/1 0/1 tq0ioc1 select valid edge of tiq00 pin input select valid edge of tiq01 pin input 0/1 0/1 0/1 tq0is2 tq0is1 tq0is0 tq0is3 tq0is6 tq0is5 tq0is4 tq0is7 select valid edge of tiq02 pin input select valid edge of tiq03 pin input (d) tmq0 option register 0 (tq0opt0) 00000 tq0opt0 overflow flag 0 0 0/1 tq0ccs0 tq0ovf tq0ccs1 tq0ccs2 tq0ccs3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 371 of 870 sep 30, 2010 figure 8-36. register setting in pu lse width measurement mode (2/2) (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) these registers store the count value of the 16-bit c ounter when the valid edge input to the tiq0m pin is detected. remarks 1. tmq0 i/o control register 0 (tq0ioc0) and tm q0 i/o control register 2 (tq0ioc2) are not used in the pulse width measurement mode. 2. m = 0 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 372 of 870 sep 30, 2010 (1) operation flow in pul se width measurement mode figure 8-37. software processing flow in pulse width measurement mode <1> <2> set tq0ctl0 register (tq0ce bit = 1) tq0ce bit = 0 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits), tq0ctl1 register, tq0ioc1 register, tq0ioc2 register, tq0opt0 register initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). the counter is initialized and counting is stopped by clearing the tq0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tq0ce bit tiq00 pin input tq0ccr0 register inttq0cc0 signal d 0 0000h 0000h d 1 d 2
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 373 of 870 sep 30, 2010 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tq0o vf bit to 0 with the clr instruction and by writing 8- bit data (bit 0 is ?0?) to the tq0opt0 register. to accurately detect an overflow, read the tq0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tq0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tq0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tq0ovf bit) overflow flag (tq0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without checking if the flag is 1, t he set information of overflow may be erased by writing 0 ((ii) in the above chart) . therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction.
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 374 of 870 sep 30, 2010 8.5.8 timer output operations the following table shows the operations and out put levels of the toq00 to toq03 pins. table 8-6. timer output control in each mode operation mode toq00 pin toq 01 pin toq02 pin toq03 pin interval timer mode square wave output external event count mode square wave output ? external trigger pulse output mode external trigger pulse output external trigger pulse output external trigger pulse output one-shot pulse output mode one-shot pulse output one-shot pulse output one-shot pulse output pwm output mode square wave output pwm output pwm output pwm output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? table 8-7. truth table of toq00 to toq03 pins under control of timer output control bits tq0ioc0.tq0olm bit tq0ioc0.tq0oem bit tq0ctl0.tq0ce bit level of toq0m pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark m = 0 to 3
v850es/jg3 chaptrer 8 16-bit timer/event counter q (tmq) r01uh0015ej0300 rev.3.00 page 375 of 870 sep 30, 2010 8.6 cautions (1) capture operation when the capture operation is used and a slow clock is selected as the count clock, ffffh , not 0000h, may be captured in the tq0ccr0, tq0ccr1, tq0ccr2, and tq0 ccr3 registers if the capture trigger is input immediately after the tq0ce bit is set to 1. (a) free-running timer mode count clock 0000h ffffh tq0ce bit tq0ccr0 register ffffh 0001h 0000h tiq00 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tq0ce bit tq0ccr0 register tiq00 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input
v850es/jg3 chapter 9 16-bit interval timer m (tmm) r01uh0015ej0300 rev.3.00 page 376 of 870 sep 30, 2010 chapter 9 16-bit interval timer m (tmm) 9.1 overview ? interval function ? 8 clocks selectable ? 16-bit counter 1 (the 16-bit counter cannot be read during timer count operation.) ? compare register 1 (the compare register cannot be written during timer counter operation.) ? compare match interrupt 1 timer m supports only the clear & start mode. the free-running timer mode is not supported.
v850es/jg3 chapter 9 16-bit interval timer m (tmm) r01uh0015ej0300 rev.3.00 page 377 of 870 sep 30, 2010 9.2 configuration tmm0 includes the following hardware. table 9-1. configuration of tmm0 item configuration timer register 16-bit counter register tmm0 compare register 0 (tm0cmp0) control register tmm0 control register 0 (tm0ctl0) figure 9-1. block diagram of tmm0 tm0ctl0 internal bus f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt controller 16-bit counter match clear inttm0eq0 tm0cmp0 tm0ce tm0cks2 tm0cks1tm0cks0 selector remark f xx : main clock frequency f r : internal oscillation clock frequency f xt : subclock frequency intwt: watch timer interrupt request signal (1) 16-bit counter this is a 16-bit counter that counts the internal clock. the 16-bit counter cannot be read or written. (2) tmm0 compare register 0 (tm0cmp0) the tm0cmp0 register is a 16-bit compare register. this register can be read or written in 16-bit units. reset sets this register to 0000h. the same value can always be written to the tm0cmp0 register by software. tm0cmp0 register rewrite is prohibit ed when the tm0ctl0.tm0ce bit = 1. tm0cmp0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff694h 14 0 13 11 9 7 5 3 15 1
v850es/jg3 chapter 9 16-bit interval timer m (tmm) r01uh0015ej0300 rev.3.00 page 378 of 870 sep 30, 2010 9.3 register (1) tmm0 control register (tm0ctl0) the tm0ctl0 register is an 8-bit regist er that controls the tmm0 operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tm0ctl0 register by software. tm0ce tmm0 operation disabled (16-bit counter reset asynchronously). operation clock application stopped. tmm0 operation enabled. operation clock application started. tmm0 operation started. tm0ce 0 1 internal clock operation enable/disable specification tm0ctl0 0 0 0 0 tm0cks2 tm0cks1 tm0cks0 654321 after reset: 00h r/w address: fffff690h the internal clock control and internal circuit reset for tmm0 are performed asynchronously with the tm0ce bit. when the tm0ce bit is cleared to 0, the internal clock of tmm0 is disabled (fixed to low level) and 16-bit counter is reset asynchronously. <7> 0 f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt tm0cks2 0 0 0 0 1 1 1 1 count clock selection tm0cks1 0 0 1 1 0 0 1 1 tm0cks0 0 1 0 1 0 1 0 1 cautions 1. set the tm0cks2 to tm 0cks0 bits when tm0ce bit = 0. when changing the value of tm0ce from 0 to 1, it is not possible to set the value of the tm0cks2 to tm0cks0 bits simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency f r : internal oscillation clock frequency f xt : subclock frequency
v850es/jg3 chapter 9 16-bit interval timer m (tmm) r01uh0015ej0300 rev.3.00 page 379 of 870 sep 30, 2010 9.4 operation caution do not set the tm0cmp0 register to ffffh. 9.4.1 interval timer mode in the interval timer mode, an interrupt request signal (i nttm0eq0) is generated at the specified interval if the tm0ctl0.tm0ce bit is set to 1. figure 9-2. configuration of interval timer 16-bit counter tm0cmp0 register tm0ce bit count clock selection clear match signal inttm0eq0 signal figure 9-3. basic timing of op eration in interval timer mode ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal d d d d d interval (d + 1) interval (d + 1) interval (d + 1) interval (d + 1) when the tm0ce bit is set to 1, the val ue of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and the counter starts counting. when the count value of the 16-bit counter matches the valu e of the tm0cmp0 register, the 16-bit counter is cleared to 0000h and a compare match interrupt request signal (inttm0eq0) is generated. the interval can be calculated by the following expression. interval = (set value of tm0cmp0 register + 1) count clock cycle
v850es/jg3 chapter 9 16-bit interval timer m (tmm) r01uh0015ej0300 rev.3.00 page 380 of 870 sep 30, 2010 figure 9-4. register setting for interval timer mode operation (a) tmm0 control register 0 (tm0ctl0) 0/1 0 0 0 0 tm0ctl0 0/1 0/1 0/1 tm0cks2 tm0cks1 tm0cks0 tm0ce 0: stop counting 1: enable counting select count clock (b) tmm0 compare register 0 (tm0cmp0) if the tm0cmp0 register is set to d, the interval is as follows. interval = (d + 1) count clock cycle
v850es/jg3 chapter 9 16-bit interval timer m (tmm) r01uh0015ej0300 rev.3.00 page 381 of 870 sep 30, 2010 (1) interval timer mode operation flow figure 9-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal d d d d <1> <2> tm0ce bit = 1 tm0ce bit = 0 register initial setting tm0ctl0 register (tm0cks0 to tm0cks2 bits) tm0cmp0 register initial setting of these registers is performed before setting the tm0ce bit to 1. setting the tm0cks0 to tm0cks2 bits is prohibited at the same time when counting has been started (tm0ce bit = 1). the counter is initialized and counting is stopped by clearing the tm0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow
v850es/jg3 chapter 9 16-bit interval timer m (tmm) r01uh0015ej0300 rev.3.00 page 382 of 870 sep 30, 2010 (2) interval timer mode operation timing caution do not set the tm0cmp0 register to ffffh. (a) operation if tm0cmp0 register is set to 0000h if the tm0cmp0 register is set to 0000h, the inttm 0eq0 signal is generated at each count clock. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tm0ce bit tm0cmp0 register inttm0eq0 signal 0000h interval time count clock cycle ffffh 0000h 0000h 0000h 0000h interval time count clock cycle (b) operation if tm0cmp0 register is set to n if the tm0cmp0 register is set to n, the 16-bit counte r counts up to n. the counter is cleared to 0000h in synchronization with the next count-up timing and the inttm0eq0 signal is generated. ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal n interval time (n + 1) count clock cycle interval time (n + 1) count clock cycle interval time (n + 1) count clock cycle n remark 0000h < n < ffffh
v850es/jg3 chapter 9 16-bit interval timer m (tmm) r01uh0015ej0300 rev.3.00 page 383 of 870 sep 30, 2010 9.4.2 cautions (1) it takes the 16-bit counter up to the following time to start counting after the tm0ctl0.tm0ce bit is set to 1, depending on the count clock selected. selected count clock maximum time before counting start f xx 2/f xx f xx /2 3/f xx f xx /4 6/f xx f xx /64 128/f xx f xx /512 1024/f xx intwt second rising edge of intwt signal f r /8 16/f r f xt 2/f xt (2) rewriting the tm0cmp0 and tm0ctl0 regist ers is prohibited while tmm0 is operating. if these registers are rewritten while the tm0c e bit is 1, the operation cannot be guaranteed. if they are rewritten by mistake, clear the tm 0ctl0.tm0ce bit to 0, and re-set the registers.
v850es/jg3 chapter 10 watch timer functions r01uh0015ej0300 rev.3.00 page 384 of 870 sep 30, 2010 chapter 10 watch timer functions 10.1 functions the watch timer has the following functions. ? watch timer: an interrupt request signal (intwt) is gener ated at intervals of 0.5 or 0.25 seconds by using the main clock or subclock. ? interval timer: an interrupt request sig nal (intwti) is generated at set intervals. the watch timer and interval timer functions can be used at the same time.
v850es/jg3 chapter 10 watch timer functions r01uh0015ej0300 rev.3.00 page 385 of 870 sep 30, 2010 10.2 configuration the block diagram of the watch timer is shown below. figure 10-1. block diagram of watch timer internal bus watch timer operation mode register (wtm) f brg f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 f x f x /8 f x /4 f x /2 f x bgcs00 bgcs01 bgce0 3-bit prescaler 8-bit counter clear match f bgcs prsm0 register prscm0 register 1/2 2 internal bus clock control selector selector selector selector selector remark f x : main clock oscillation frequency f bgcs : watch timer source clock frequency f brg : watch timer count clock frequency f xt : subclock frequency f w : watch timer clock frequency intwt: watch timer interrupt request signal intwti: interval timer interrupt request signal
v850es/jg3 chapter 10 watch timer functions r01uh0015ej0300 rev.3.00 page 386 of 870 sep 30, 2010 (1) clock control this block controls supplying and stopping the operating clock (f x ) when the watch timer operates on the main clock. (2) 3-bit prescaler this prescaler divides f x to generate f x /2, f x /4, or f x /8. (3) 8-bit counter this 8-bit counter counts the source clock (f bgcs ). (4) 11-bit prescaler this prescaler divides f w to generate a clock of f w /2 4 to f w /2 11 . (5) 5-bit counter this counter counts f w or f w /2 9 , and generates a watch timer interrupt request signal at intervals of 2 4 /f w , 2 5 /f w , 2 12 /f w , or 2 14 /f w . (6) selector the watch timer has the following five selectors. ? selector that selects one of f x , f x /2, f x /4, or f x /8 as the source clock of the watch timer ? selector that selects the main clock (f x ) or subclock (f xt ) as the clock of the watch timer ? selector that selects f w or f w /2 9 as the count clock frequency of the 5-bit counter ? selector that selects 2 4 /f w , 2 13 /f w , 2 5 /f w , or 2 14 /f w as the intwt signal generation time interval ? selector that selects 2 4 /f w to 2 11 /f w as the interval timer interrupt request signal (intwti) generation time interval (7) prscm register this is an 8-bit compare register that sets the interval time. (8) prsm register this register controls clock supply to the watch timer. (9) wtm register this is an 8-bit register that controls the operation of the watch timer/interv al timer, and sets the interrupt request signal generation interval.
v850es/jg3 chapter 10 watch timer functions r01uh0015ej0300 rev.3.00 page 387 of 870 sep 30, 2010 10.3 control registers the following registers are provided for the watch timer. ? prescaler mode register 0 (prsm0) ? prescaler compare register 0 (prscm0) ? watch timer operation mode register (wtm) (1) prescaler mode register 0 (prsm0) the prsm0 register controls the generat ion of the watch timer count clock. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 prsm0 0 0 bgce0 0 0 bgcs01 bgcs00 disabled enabled bgce0 0 1 main clock operation enable f x f x /2 f x /4 f x /8 5 mhz 200 ns 400 ns 800 ns 1.6 s 4 mhz 250 ns 500 ns 1 s 2 s bgcs01 0 0 1 1 bgcs00 0 1 0 1 selection of watch timer source clock (f bgcs ) after reset: 00h r/w address: fffff8b0h < > cautions 1. do not change the values of the bgcs00 and bgcs01 bits during watch timer operation. 2. set the prsm0 register befo re setting the bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz.
v850es/jg3 chapter 10 watch timer functions r01uh0015ej0300 rev.3.00 page 388 of 870 sep 30, 2010 (2) prescaler compare register 0 (prscm0) the prscm0 register is an 8-bit compare register. this register can be read or written in 8-bit units. reset sets this register to 00h. prscm07 prscm0 prscm06 prscm05 prscm04 prscm03 prscm02 prscm01 prscm00 after reset: 00h r/w address: fffff8b1h cautions 1. do not rewrite the prscm0 register during watc h timer operation. 2. set the prscm0 register before setting the prsm0.bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz. the calculation for f brg is shown below. f brg = f bgcs /2n remark f bgcs : watch timer source clock set by the prsm0 register n: set value of prscm0 register = 1 to 256 however, n = 256 only when prscm0 register is set to 00h.
v850es/jg3 chapter 10 watch timer functions r01uh0015ej0300 rev.3.00 page 389 of 870 sep 30, 2010 (3) watch timer operation mode register (wtm) the wtm register enables or disables t he count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. set the prsm0 register before setting the wtm register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.90 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.2 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of interval time of prescaler wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h < > < >
v850es/jg3 chapter 10 watch timer functions r01uh0015ej0300 rev.3.00 page 390 of 870 sep 30, 2010 (2/2) 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of set time of watch flag clears after operation stops starts wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stops operation (clears both prescaler and 5-bit counter) enables operation wtm0 0 1 watch timer operation enable caution rewrite the wtm2 to wtm7 bits wh ile both the wtm0 and wtm1 bits are 0. remarks 1. f w : watch timer clock frequency 2. values in parentheses apply to operation with f w = 32.768 khz
v850es/jg3 chapter 10 watch timer functions r01uh0015ej0300 rev.3.00 page 391 of 870 sep 30, 2010 10.4 operation 10.4.1 operation as watch timer the watch timer generates an interrupt request signal (intwt ) at fixed time intervals. the watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 khz) or main clock. the count operation starts wh en the wtm.wtm1 and wtm.wtm0 bits are set to 11. when the wtm0 bit is cleared to 0, the 11-bit prescaler and 5-bit counter ar e cleared and the count operation stops. the time of the watch timer can be adjus ted by clearing the wtm1 bit to 0 and th en the 5-bit counter when operating at the same time as the interval timer. at this time, an error of up to 15.6 ms may occur for the watch timer, but the interval timer is not affected. if the main clock is used as the count clock of the watc h timer, set the count clo ck using the prsm0.bgcs01 and bgcs00 bits, the 8-bit comparison value using the prscm0 register, and the count clock frequency (f brg ) of the watch timer to 32.768 khz. when the prsm0.bgce0 bit is set (1), f brg is supplied to the watch timer. f brg can be calculated by the following expression. f brg = f x /(2 m+1 n) to set f brg to 32.768 khz, perform the following calculation and set the bgcs01 and bgcs00 bits and the prscm0 register. <1> set n = f x /65,536. set m = 0. <2> when the value resulting from rounding up the first decim al place of n is even, set n before the roundup as n/2 and m as m + 1. <3> repeat <2> until n is odd or m = 3. <4> set the value resulting from rounding up the first decim al place of n to the prscm0 register and m to the bgcs01 and bgcs00 bits. example: when f x = 4.00 mhz <1> n = 4,000,000/65,536 = 61.03?, m = 0 <2>, <3> because n (round up the first decimal place) is odd, n = 61, m = 0. <4> set value of prscm0 register: 3dh (61), set value of bgcs01 and bgcs00 bits: 00 at this time, the actual f brg frequency is as follows. f brg = f x /(2 m+1 n) = 4,000,000/(2 61) = 32.787 khz remark m: division value (set value of bgcs01 and bgcs00 bits) = 0 to 3 n: set value of prscm0 register = 1 to 256 however, n = 256 only when prscm0 register is set to 00h. f x : main clock oscillation frequency
v850es/jg3 chapter 10 watch timer functions r01uh0015ej0300 rev.3.00 page 392 of 870 sep 30, 2010 10.4.2 operation as in terval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (intwti) at intervals specified by a preset count value. the interval time can be selected by the wt m4 to wtm7 bits of the wtm register. table 10-1. interval ti me of interval timer wtm7 wtm6 wtm5 wtm4 interval time 0 0 0 0 2 4 1/fw 488 s (operating at f w = f xt = 32.768 khz) 0 0 0 1 2 5 1/fw 977 s (operating at f w = f xt = 32.768 khz) 0 0 1 0 2 6 1/fw 1.95 ms (operating at f w = f xt = 32.768 khz) 0 0 1 1 2 7 1/fw 3.91 ms (operating at f w = f xt = 32.768 khz) 0 1 0 0 2 8 1/fw 7.81 ms (operating at f w = f xt = 32.768 khz) 0 1 0 1 2 9 1/fw 15.6 ms (operating at f w = f xt = 32.768 khz) 0 1 1 0 2 10 1/fw 31.3 ms (operating at f w = f xt = 32.768 khz) 0 1 1 1 2 11 1/fw 62.5 ms (operating at f w = f xt = 32.768 khz) 1 0 0 0 2 4 1/fw 488 s (operating at f w = f brg = 32.768 khz) 1 0 0 1 2 5 1/fw 977 s (operating at f w = f brg = 32.768 khz) 1 0 1 0 2 6 1/fw 1.95 ms (operating at f w = f brg = 32.768 khz) 1 0 1 1 2 7 1/fw 3.91 ms (operating at f w = f brg = 32.768 khz) 1 1 0 0 2 8 1/fw 7.81 ms (operating at f w = f brg = 32.768 khz) 1 1 0 1 2 9 1/fw 15.6 ms (operating at f w = f brg = 32.768 khz) 1 1 1 0 2 10 1/fw 31.3 ms (operating at f w = f brg = 32.768 khz) 1 1 1 1 2 11 1/fw 62.5 ms (operating at f w = f brg = 32.768 khz) remark f w : watch timer clock frequency
v850es/jg3 chapter 10 watch timer functions r01uh0015ej0300 rev.3.00 page 393 of 870 sep 30, 2010 figure 10-2. operation timing of watch timer/interval timer start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti remarks 1. when 0.5 seconds of the watch timer interrupt time is set. 2. f w : watch timer clock frequency values in parentheses apply to operation with f w = 32.768 khz. n: number of interval timer operations 10.4.3 cautions some time is required before the first watch timer interr upt request signal (intwt) is generated after operation is enabled (wtm.wtm1 and wtm.wtm0 bits = 1). figure 10-3. example of generation of watc h timer interrupt request signal (intwt) (when interrupt cycle = 0.5 s) it takes 0.515625 seconds (max.) for the first intwt signal to be generated (2 9 1/32768 = 0.015625 seconds longer (max.)). the intwt signal is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt
v850es/jg3 chapter 11 function s of watchdog timer 2 r01uh0015ej0300 rev.3.00 page 394 of 870 sep 30, 2010 chapter 11 functions of watchdog timer 2 11.1 functions watchdog timer 2 has the following functions. ? default-start watchdog timer note 1 reset mode: reset operation upon overflow of wa tchdog timer 2 (generation of wdt2res signal) non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2 signal) note 2 ? input selectable from main clock, internal os cillation clock, and subclock as the source clock notes 1. watchdog timer 2 automatically starts in the reset mode following reset release. when watchdog timer 2 is not used, either stop its operation before reset is exec uted via this function, or clear watchdog timer 2 once and stop it within the next interval time. also, write to the wdtm2 register for verificati on purposes only once, even if the default settings (reset mode, interval time: f r /2 19 ) do not need to be changed. 2. for the non-maskable interrupt servicing due to a no n-maskable interrupt request signal (intwdt2), see 19.2.2 (2) from intwdt2 signal .
v850es/jg3 chapter 11 function s of watchdog timer 2 r01uh0015ej0300 rev.3.00 page 395 of 870 sep 30, 2010 11.2 configuration the following shows the block diagram of watchdog timer 2. figure 11-1. block diag ram of watchdog timer 2 f xx /2 9 clock input controller output controller wdt2res (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 f xt wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f xx /2 18 to f xx /2 25 , f xt /2 9 to f xt /2 16 , f r /2 12 to f r /2 19 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 3 2 clear f r /2 3 remark f xx : main clock frequency f xt : subclock frequency f r : internal oscillation clock frequency intwdt2: non-maskable interrupt request signal from watchdog timer 2 wdtres2: watchdog timer 2 reset signal watchdog timer 2 includes the following hardware. table 11-1. configuration of watchdog timer 2 item configuration control registers watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte)
v850es/jg3 chapter 11 function s of watchdog timer 2 r01uh0015ej0300 rev.3.00 page 396 of 870 sep 30, 2010 11.3 registers (1) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time and operation clock of watchdog timer 2. this register can be read or written in 8-bit units. th is register can be read any number of times, but it can be written only once following reset release. reset sets this register to 67h. caution accessing the wdtm2 register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2 signal) reset mode (generation of wdt2res signal) wdm21 0 0 1 wdm20 0 1 selection of operation mode of watchdog timer 2 cautions 1. for details of the wdcs20 to w dcs24 bits, see table 11-2 watchdog timer 2 clock selection. 2. although watchdog timer 2 can be stopped just by stopping the operation of the internal oscillator, clear the wdtm2 re gister to 00h to securely st op the timer (to avoid selection of the main clock or subclock due to an erroneous write operation). 3. if the wdtm2 register is rewritten twice after reset, an overflow signal is forcibly generated and the counter is reset. 4. to intentionally generate an overflow signa l, write data to the wdtm2 register only twice, or write a value other than ?ach? to the wdte register only once. however, when watchdog timer 2 is set to stop operation, an overflow signal is not generated even if data is written to the wdtm2 register only twice, or a value other than ?ach? is written to the wdte register only once. 5. to stop the operation of watchdog timer 2, set the rcm.rstop bit to 1 (to stop the internal oscillator) and write 00h in the wdtm 2 register. if the rcm.rstop bit cannot be set to 1, set the wdcs23 bit to 1 (2 n /f xx is selected and the clock can be stopped in the idle1, idlw2, sub-idle, an d subclock operation modes).
v850es/jg3 chapter 11 function s of watchdog timer 2 r01uh0015ej0300 rev.3.00 page 397 of 870 sep 30, 2010 table 11-2. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 selected cl ock 100 khz (min.) 220 khz (typ.) 400 khz (max.) 0 0 0 0 0 2 12 /f r 41.0 ms 18.6 ms 10.2 ms 0 0 0 0 1 2 13 /f r 81.9 ms 37.2 ms 20.5 ms 0 0 0 1 0 2 14 /f r 163.8 ms 74.5 ms 41.0 ms 0 0 0 1 1 2 15 /f r 327.7 ms 148.9 ms 81.9 ms 0 0 1 0 0 2 16 /f r 655.4 ms 297.9 ms 163.8 ms 0 0 1 0 1 2 17 /f r 1,310.7 ms 595.8 ms 327.7 ms 0 0 1 1 0 2 18 /f r 2,621.4 ms 1,191.6 ms 655.4 ms 0 0 1 1 1 2 19 /f r 5,242.9 ms 2,383.1 ms 1,310.7 ms f xx = 32 mhz f xx = 20 mhz f xx = 10 mhz 0 1 0 0 0 2 18 /f xx 8.2 ms 13.1 ms 26.2 ms 0 1 0 0 1 2 19 /f xx 16.4 ms 26.2 ms 52.4 ms 0 1 0 1 0 2 20 /f xx 32.8 ms 52.4 ms 104.9 ms 0 1 0 1 1 2 21 /f xx 65.5 ms 104.9 ms 209.7 ms 0 1 1 0 0 2 22 /f xx 131.1 ms 209.7 ms 419.4 ms 0 1 1 0 1 2 23 /f xx 262.1 ms 419.4 ms 838.9 ms 0 1 1 1 0 2 24 /f xx 524.3 ms 838.9 ms 1,677.7 ms 0 1 1 1 1 2 25 /f xx 1,048.6 ms 1,677.7 ms 3,355.4 ms f xt = 32.768 khz 1 0 0 0 2 9 /f xt 15.625 ms 1 0 0 1 2 10 /f xt 31.25 ms 1 0 1 0 2 11 /f xt 62.5 ms 1 0 1 1 2 12 /f xt 125 ms 1 1 0 0 2 13 /f xt 250 ms 1 1 0 1 2 14 /f xt 500 ms 1 1 1 0 2 15 /f xt 1,000 ms 1 1 1 1 2 16 /f xt 2,000 ms (2) watchdog timer enable register (wdte) the counter of watchdog timer 2 is cleared and counting restarted by wr iting ?ch?to the wdte register. the wdte register can be read or written in 8-bit units. reset sets this register to 9ah. wdte after reset: 9ah r/w address: fffff6d1h cautions 1. when a value other than ?ach? is writ ten to the wdte register , an overflow signal is forcibly output. 2. when a 1-bit memory mani pulation instruction is execute d for the wdte register, an overflow signal is forcibly output. 3. to intentionally generate an overflow signal, write a value other than ?ach? to the wdte register only once, or write data to the wdtm2 register only twice. however, when the watchdog timer 2 is set to stop operation, an overflow signal is not generated even if data is wri tten to the wdtm2 register only twice, or a value other than ?ach? is written to the wdte register only once. 4. the read value of the wdte register is ?9ah? (which differs from written value ?ach?).
v850es/jg3 chapter 11 function s of watchdog timer 2 r01uh0015ej0300 rev.3.00 page 398 of 870 sep 30, 2010 11.4 operation watchdog timer 2 automatically starts in t he reset mode following reset release. the wdtm2 register can be written to only once following rese t using byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm2 register us ing an 8-bit memory manipulation instruction. after this, the operation of watchdog ti mer 2 cannot be stopped. the wdcs24 to wdcs20 bits of the wdtm 2 register are used to select the wa tchdog timer 2 loop detection time interval. writing ach to the wdte register clear s the counter of watchdog timer 2 and star ts the count operation again. after the count operation has started, write ach to wdte within the loop detection time interval. if the time interval expires without ach being written to the wdte register, a reset signal (wdt2res) or a non- maskable interrupt request signal (intwdt2) is generat ed, depending on the set values of the wdm21 and wdtm2.wdm20 bits. when the wdtm2.wdm21 bit is set to 1 (reset mode), if a wd t overflow occurs during oscillation stabilization after a reset or standby is released, no internal reset will occur and the cpu clock will switch to the internal oscillation clock. to not use watchdog timer 2, write 00h to the wdtm2 register. for the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 19.2.2 (2) from intwdt2 signal .
v850es/jg3 chapter 12 real-t ime output function (rto) r01uh0015ej0300 rev.3.00 page 399 of 870 sep 30, 2010 chapter 12 real-time output function (rto) 12.1 function the real-time output function transfers preset data to the rtbl0 and rtbh0 regi sters, and then transfers this data by hardware to an external device via the out put latches, upon occurrence of a timer in terrupt. the pins through which the data is output to an external device constitute a port called the real-time ou tput function (rto). because rto can output signals without jitter, it is suitable for controlling a stepper motor. in the v850es/jg3, one 6-bit real-tim e output port channel is provided. the real-time output port can be se t to the port mode or real-time output port mode in 1-bit units.
v850es/jg3 chapter 12 real-t ime output function (rto) r01uh0015ej0300 rev.3.00 page 400 of 870 sep 30, 2010 12.2 configuration the block diagram of rto is shown below. figure 12-1. block diagram of rto inttp0cc0 inttp5cc0 inttp4cc0 rtpoe0 rtpeg0 byte0 extr0 rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 4 2 2 4 rtp04, rtp05 rtp00 to rtp03 real-time output buffer register 0h (rtbh0) real-time output latch 0h selector real-time output latch 0l real-time output port control register 0 (rtpc0) transfer trigger (h) transfer trigger (l) real-time output port mode register 0 (rtpm0) internal bus real-time output buffer register 0l (rtbl0) rto includes the following hardware. table 12-1. configuration of rto item configuration registers real-time output buffer r egisters 0l, 0h (rtbl0, rtbh0) control registers real-time output port mode register 0 (rtpm0) real-time output port control register 0 (rtpc0)
v850es/jg3 chapter 12 real-t ime output function (rto) r01uh0015ej0300 rev.3.00 page 401 of 870 sep 30, 2010 (1) real-time output buffer regi sters 0l, 0h (rtbl0, rtbh0) the rtbl0 and rtbh0 registers are 4-bit registers that hold preset output data. these registers are mapped to independent addresses in the peripheral i/o register area. these registers can be read or wr itten in 8-bit or 1-bit units. reset sets these registers to 00h. if an operation mode of 4 bits 1 channel or 2 bits 1 channel is specified (rtpc0.byte0 bit = 0), data can be individually set to the rtbl0 and rt bh0 registers. the dat a of both these register s can be read at once by specifying the address of ei ther of these registers. if an operation mode of 6 bits 1 channel is specified (byte0 bit = 1), 8-bit data can be set to both the rtbl0 and rtbh0 registers by writing the data to ei ther of these registers. moreover, t he data of both these registers can be read at once by specifying the addre ss of either of these registers. table 12-2 shows the operation when the rt bl0 and rtbh0 register s are manipulated. 0 rtbl0 rtbh0 0 rtbh05 rtbh04 rtbl03 rtbl02 rtbl01 rtbl00 after reset: 00h r/w address: rtbl0 fffff6e0h, rtbh0 fffff6e2h cautions 1. when writing to bits 6 and 7 of the rtbh0 register, always write 0. 2. accessing the rtbl0 and rtbh0 regi sters is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subc lock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock table 12-2. operation during manipul ation of rtbl0 and rtbh0 registers read write note operation mode register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl0 rtbh0 rtbl0 invalid rtbl0 4 bits 1 channel, 2 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 invalid rtbl0 rtbh0 rtbl0 rtbh0 rtbl0 6 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 rtbl0 note after setting the real-time output port, set output data to the rtbl0 and rtbh0 register s by the time a real-time output trigger is generated.
v850es/jg3 chapter 12 real-t ime output function (rto) r01uh0015ej0300 rev.3.00 page 402 of 870 sep 30, 2010 12.3 registers rto is controlled using the following two registers. ? real-time output port mode register 0 (rtpm0) ? real-time output port control register 0 (rtpc0) (1) real-time output port mode register 0 (rtpm0) the rtpm0 register selects t he real-time output port mode or port mode in 1-bit units. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 rtpm0m 0 1 real-time output disabled real-time output enabled control of real-time output port (m = 0 to 5) rtpm0 0 rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 after reset: 00h r/w address: rtpm0 fffff6e4h cautions 1. by enabling the real-time output operation (rtpc0.rtpoe0 bit = 1), the bits enabled to real-time output among the rt p00 to rtp05 signa ls perform real- time output, and the bits set to port mode output 0. 2. if real-time output is disabled (rtpoe0 bit = 0), the real-time output pins (rtp00 to rtp05) all output 0, regard less of the rtpm0 register setting. 3. in order to use this register as the real-time output pins (rtp00 to rtp05), set these pins as real-time output port pins using the pmc and pfc registers.
v850es/jg3 chapter 12 real-t ime output function (rto) r01uh0015ej0300 rev.3.00 page 403 of 870 sep 30, 2010 (2) real-time output port control register 0 (rtpc0) the rtpc0 register is a register that sets the operat ion mode and output trigger of the real-time output port. the relationship between the operation mode and output trigger of t he real-time output port is as shown in tables 12-3 and 12-4. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. rtpoe0 disables operation note 1 enables operation rtpoe0 0 1 control of real-time output operation rtpc0 rtpeg0 byte0 extr0 0 0 0 0 falling edge note 2 rising edge rtpeg0 0 1 valid edge of inttpacc0 (a = 0, 4, 5) signal 4 bits 1 channel, 2 bits 1 channel 6 bits 1 channel byte0 0 1 specification of channel configuration for real-time output after reset: 00h r/w address: rtpc0 fffff6e5h < > notes 1. when the real-time output oper ation is disabled (rtpoe0 bit = 0), all the bits of the real-time output signals (rtp00 to rtp05) output ?0?. 2. the inttp0cc0 signal is output for one clock of the count clock selected by tmp0. caution set the rtpeg0, byte0, and ext r0 bits only when rtpoe0 bit = 0. table 12-3. operation modes and output triggers of real-time output port byte0 extr0 operation mode rtbh0 (rtp 04, rtp05) rtbl0 (rtp00 to rtp03) 0 inttp5cc0 inttp4cc0 0 1 4 bits 1 channel, 2 bits 1 channel inttp4cc0 inttp0cc0 0 inttp4cc0 1 1 6 bits 1 channel inttp0cc0
v850es/jg3 chapter 12 real-t ime output function (rto) r01uh0015ej0300 rev.3.00 page 404 of 870 sep 30, 2010 12.4 operation if the real-time output operatio n is enabled by setting the rtpc0.rtpoe0 bi t to 1, the data of the rtbh0 and rtbl0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the rtpc0.extr0 and rt pc0.byte0 bits). of the transferred data, only the data of the bits for which real-time output is enabled by the rtpm0 r egister is output from the rtp00 to rtp05 bits . the bits for which real-time output is disabled by the rtpm0 register output 0. if the real-time output operation is disa bled by clearing the rtpoe0 bit to 0, the rtp00 to rtp05 signals output 0 regardless of the setting of the rtpm0 register. figure 12-2. example of operation timing of rto0 (when extr0 bit = 0, byte0 bit = 0) abababab d01 d02 d03 d04 d11 d12 d13 d14 d11 d12 d13 d14 d01 d02 d03 d04 inttp5cc0 (internal) inttp4cc0 (internal) cpu operation rtbh0 rtbl0 rt output latch 0 (h) rt output latch 0 (l) a: software processing by inttp5cc0 interrupt request (rtbh0 write) b: software processing by inttp4cc0 interrupt request (rtbl0 write) remark for the operation during standby, see chapter 21 standby function .
v850es/jg3 chapter 12 real-t ime output function (rto) r01uh0015ej0300 rev.3.00 page 405 of 870 sep 30, 2010 12.5 usage (1) disable real-time output. clear the rtpc0.rtpoe0 bit to 0. (2) perform initialization as follows. ? set the alternate-function pins of port 5 set the pfc5.pfc5m bit and pfce5.pfce5m bit to 1, and then set the pmc5.pmc5m bit to 1 (m = 0 to 5). ? specify the real-time output port mode or port mode in 1-bit units. set the rtpm0 register. ? channel configuration: select the trigger and valid edge. set the rtpc0.extr0, rtpc0. byte0, and rtpc0.rtpeg0 bits. ? set the initial values to the rtbh0 and rtbl0 registers note 1 . (3) enable real-time output. set the rtpoe0 bit = 1. (4) set the next output value to the rtbh0 and rtbl0 registers by the time the selected transfer trigger is generated note 2 . (5) set the next real-time output value to the rtbh0 and rtbl0 registers via inte rrupt servicing corresponding to the selected trigger. notes 1. if the rtbh0 and rtbl0 registers ar e written when the rtpoe0 bit = 0, that value is transferred to real-time output latches 0h and 0l, respectively. 2. even if the rtbh0 and rtbl 0 registers are written wh en the rtpoe0 bit = 1, data is not transferred to real-time output latches 0h and 0l. 12.6 cautions (1) prevent the following conflicts by software. ? conflict between real-time output di sable/enable switching (rtpoe0 bit) and selected real-time output trigger. ? conflict between writing to the rt bh0 and rtbl0 registers in the re al-time output enabled status and the selected real-time output trigger. (2) before performing initialization, disable real-time output (rtpoe0 bit = 0). (3) once real-time output has been disabled (rtpoe0 bit = 0), be sure to initialize the rtbh0 and rtbl0 registers before enabling real-time output again (rtpoe0 bit = 0 1).
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 406 of 870 sep 30, 2010 chapter 13 a/d converter 13.1 overview the a/d converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 analog input signal channels (ani0 to ani11). the a/d converter has the following features. 10-bit resolution 12 channels successive approximation method operating voltage: av ref0 = 3.0 to 3.6 v analog input voltage: 0 v to av ref0 the following functions are provided as operation modes. ? continuous select mode ? continuous scan mode ? one-shot select mode ? one-shot scan mode the following functions are provided as trigger modes. ? software trigger mode ? external trigger mode (external, 1) ? timer trigger mode power-fail monitor function (conversion result compare function) 13.2 functions (1) 10-bit resolution a/d conversion an analog input channel is selected from ani0 to ani11, and an a/d conversion operation is repeated at a resolution of 10 bits. each time a/d conversion has been completed, an interrupt request signal (intad) is generated. (2) power-fail detection function this function is used to detect a drop in the battery volt age. the result of a/d co nversion (the value of the ada0crnh register) is compared with the value of the ada0pft register, and the intad signal is generated only when a specified comparison condition is satisfied (n = 0 to 11).
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 407 of 870 sep 30, 2010 13.3 configuration the block diagram of the a/d converter is shown below. figure 13-1. block diagram of a/d converter ani0 : : ani1 ani2 ani9 ani10 ani11 ada0m2 ada0m1 ada0m0 ada0s ada0pft controller voltage comparator ada0pfm ada0cr0 ada0cr1 : : ada0cr2 ada0cr10 ada0cr11 internal bus av ref0 ada0ce bit av ss intad edge detection adtrg controller sample & hold circuit ada0ets0 bit inttp2cc0 inttp2cc1 ada0ets1 bit ada0ce bit ada0tmd1 bit ada0tmd0 bit selector selector ada0pfe bit ada0pfc bit sar voltage comparator & compare voltage generation dac the a/d converter includes the following hardware. table 13-1. configuration of a/d converter item configuration analog inputs 12 channels (ani0 to ani11 pins) registers successive approximation register (sar) a/d conversion result registers 0 to 11 (ada0cr0 to ada0cr11) a/d conversion result registers 0h to 11h (adcr0h to adcr11h): only higher 8 bits can be read control registers a/d converter mode registers 0 to 2 (ada0m0 to ada0m2) a/d converter channel specification register 0 (ada0s) power fail compare mode register (ada0pfm) power fail compare threshold value register (ada0pft)
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 408 of 870 sep 30, 2010 (1) successive approximation register (sar) the sar register compares the volta ge value of the analog input signal with the output voltage (compare voltage) value of the compare voltage generation dac, and holds the comparison result st arting from the most significant bit (msb). when the comparison result has been held down to the leas t significant bit (lsb) (i.e., when a/d conversion is complete), the contents of the sar register are transferred to the ada0crn register. remark n = 0 to 11 (2) a/d conversion result register n (ada0crn), a/d conversion result register nh (ada0crnh) the ada0crn register is a 16-bit regist er that stores the a/d conversion re sult. ada0arn consist of 12 registers and the a/d conversion result is stored in the 10 higher bits of the ad0crn register corresponding to analog input. (the lower 6 bits are fixed to 0.) (3) a/d converter mode register 0 (ada0m0) this register specifies the operation mode and cont rols the conversion operation by the a/d converter. (4) a/d converter mode register 1 (ada0m1) this register sets the conversion time of the analog input signal to be converted. (5) a/d converter mode register 2 (ada0m2) this register sets the hardware trigger mode. (6) a/d converter channel specification register (ada0s) this register sets the input port that inputs the analog voltage to be converted. (7) power-fail compare m ode register (ada0pfm) this register sets the power-fail monitor mode. (8) power-fail compare threshol d value register (ada0pft) the ada0pft register sets a threshold value that is comp ared with the value of a/d conv ersion result register nh (ada0crnh). the 8-bit data set to the ada0pft register is compared with the higher 8 bits of the a/d conversion result register (ada0crnh). (9) controller the controller compares the result of the a/d conversion (the value of the ad a0crnh register) with the value of the ada0pft register when a/d conversion is completed or when the power-fail detection function is used, and generates the intad signal only when a spec ified comparison condition is satisfied. (10) sample & hold circuit the sample & hold circuit samples each of the analog i nput signals selected by the input circuit and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (11) voltage comparator the voltage comparator compares a voltage value that has been sampled and held with the output voltage value of the compare voltage generation dac.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 409 of 870 sep 30, 2010 (12) compare voltage generation dac this compare voltage generati on dac is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (13) ani0 to ani11 pins these are analog input pins for the 12 a/d converte r channels and are used to input analog signals to be converted into digital signals. pins other than the one selected as the analog input by the ada0s register can be used as input port pins. caution make sure that the voltages input to the ani0 to ani11 pins do not exceed the rated values. in particular if a voltage of av ref0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. (14) av ref0 pin this is the pin used to input the refere nce voltage of the a/d conv erter. always make the potential at this pin the same as that at the v dd pin even when the a/d converter is not used. the signals inpu t to the ani0 to ani11 pins are converted to digital signals based on the voltage applied between the av ref0 and av ss pins. (15) av ss pin this is the ground pin of the a/d converter. always make the potential at this pin the same as that at the v ss pin even when the a/d converter is not used.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 410 of 870 sep 30, 2010 13.4 registers the a/d converter is controlled by the following registers. ? a/d converter mode registers 0, 1, 2 (ada0m0, ada0m1, ada0m2) ? a/d converter channel specification register 0 (ada0s) ? power-fail compare mode register (ada0pfm) the following registers are also used. ? a/d conversion result register n (ada0crn) ? a/d conversion result register nh (ada0crnh) ? power-fail compare threshold value register (ada0pft) (1) a/d converter mode register 0 (ada0m0) the ada0m0 register is an 8-bit register that specif ies the operation mode and controls conversion operations. this register can be read or written in 8-bit or 1-bit units. however, ada0ef bit is read-only. reset sets this register to 00h. (1/2) ada0ce ada0ce 0 1 stops a/d conversion enables a/d conversion a/d conversion control ada0m0 0 <7>65432 1<0> ada0md1 ada0md0 ada0ets1 ada0ets0 ada0tmd ada0ef ada0md1 0 0 1 1 ada0md0 0 1 0 1 continuous select mode continuous scan mode one-shot select mode one-shot scan mode specification of a/d converter operation mode after reset: 00h r/w address: fffff200h ada0ets1 0 0 1 1 ada0ets0 0 1 0 1 no edge detection falling edge detection rising edge detection detection of both rising and falling edges specification of external trigger (adtrg pin) input valid edge
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 411 of 870 sep 30, 2010 (2/2) ada0tmd 0 1 software trigger mode external trigger mode/timer trigger mode trigger mode specification ada0ef 0 1 a/d conversion stopped a/d conversion in progress a/d converter status display cautions 1. accessing the ada0m0 register is prohi bited in the following st atuses. for details, see 3.4.8 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock 2. a write operation to bit 0 is ignored. 3. changing the ada0m1.ada0fr2 to ada0 m1.ada0fr0 bits is prohibited while a/d conversion is enabled (ada0ce bit = 1). 4. when writing data to the ada0m0, ada0m2 , ada0s, ada0pfm, or ada0pft register in the following modes, stop the a/d conversion by clearing the ada0ce bit to 0. after the data is written to the register, enable the a/d conversion again by setting the ada0ce bit to 1. ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode if the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written in the other modes during a/d conversion (ada0ef bit = 1), the following will be performed according to the mode. ? in software trigger mode a/d conversion is stopped and started again from the beginning. ? in hardware trigger mode a/d conversion is stopped, and th e trigger standby status is set. 5. to select the external trigger mode/timer trigger mode (ada0tmd bit = 1), set the high- speed conversion mode (ada0m1.ada0hs1 bi t = 1). do not input a trigger during stabilization time that is inserted once a fter the a/d conversion operation is enabled (ada0ce bit = 1). 6. when not using the a/d converter, stop th e operation by setting the ada0ce bit to 0 to reduce the power consumption.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 412 of 870 sep 30, 2010 (2) a/d converter mode register 1 (ada0m1) the ada0m1 register is an 8-bit regist er that specifies the conversion time. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0hs1 ada0m1 0 00 ada0fr2 ada0fr3 ada0fr1 ada0fr0 after reset: 00h r/w address: fffff201h ada0hs1 0 1 normal conversion mode high-speed conversion mode specification of normal conversion mode/high-speed mode (a/d conversion time) cautions 1. changing the ada0m1 register is prohibited while a/d conversion is enabled (ada0m0.ada0ce bit = 1). 2. to select the external trigger mode/timer trigger mode (ada0m0.ada0tmd bit = 1), set the high-speed conversion mode (ada0hs1 bit = 1). do not input a trigger during stabilization time that is inserted once af ter the a/d conversion operation is enabled (ada0ce bit = 1). 3. be sure to clear bits 6 to 4 to ?0?. remark for a/d conversion time setting examples, see tables 13-2 and 13-3 .
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 413 of 870 sep 30, 2010 table 13-2. conversion time selection in normal conversion mode (ada0hs1 bit = 0) a/d conversion time ada0fr3 to ada0fr0 bits stabilization time + conversion time + wait time f xx = 32 mhz f xx = 20 mhz f xx = 16 mhz f xx = 4 mhz trigger response time 0000 66/f xx (13/f xx + 26/f xx + 27/f xx ) setting prohibited setting prohibited setting prohibited 16.50 s 3/f xx 0001 131/f xx (26/f xx + 52/f xx + 53/f xx ) setting prohibited 6.55 s 8.19 s setting prohibited 3/f xx 0010 196/f xx (39/f xx + 78/f xx + 79/f xx ) setting prohibited 9.80 s 12.25 s setting prohibited 3/f xx 0011 259/f xx (50/f xx + 104/f xx + 105/f xx ) 8.09 s 12.95 s 16.19 s setting prohibited 3/f xx 0100 311/f xx (50/f xx + 130/f xx + 131/f xx ) 9.72 s 15.55 s 19.44 s setting prohibited 3/f xx 0101 363/f xx (50/f xx + 156/f xx + 157/f xx ) 11.34 s 18.15 s 22.69 s setting prohibited 3/f xx 0110 415/f xx (50/f xx + 182/f xx + 183/f xx ) 12.97 s 20.75 s setting prohibited setting prohibited 3/f xx 0111 467/f xx (50/f xx + 208/f xx + 209/f xx ) 14.59 s 23.35 s setting prohibited setting prohibited 3/f xx 1000 519/f xx (50/f xx + 234/f xx + 235/f xx ) 16.22 s setting prohibited setting prohibited setting prohibited 3/f xx 1001 571/f xx (50/f xx + 260/f xx + 261/f xx ) 17.84 s setting prohibited setting prohibited setting prohibited 3/f xx 1010 623/f xx (50/f xx + 286/f xx + 287/f xx ) 19.47 s setting prohibited setting prohibited setting prohibited 3/f xx 1011 675/f xx (50/f xx + 312/f xx + 313/f xx ) 21.09 s setting prohibited setting prohibited setting prohibited 3/f xx others setting prohibited remark stabilization time: a/d converter setup time (1 s or longer) conversion time: actual a/d conversion time (2.6 to 10.4 s) wait time: wait time inserted before the next conversion trigger response time: if a software trigger, external trigger, or timer trigger is generated after the stabilization time, it is inserted before the conversion time. in the normal conversion mode, the conversion is star ted after the stabilization time elapsed from the ada0m0.ada0ce bit is set to 1, and a/d conversion is performed only during the conversion time (2.6 to 10.4 s). operation is stopped after the conversion ends and the a/d conversion end interrupt request signal (intad) is generated after the wait time is elapsed. because the conversion operation is stopped during the wait time, operation current can be reduced. cautions 1. set as 2.6 s conversion time 10.4 s. 2. during a/d conversion, if the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written or trigger is input, reconversion is carried out. however, if the stabilization time end timing conflicts with th e writing to these registers, or if the stabilization time end timing conflicts with the trigger input, the stabilization time of 64 clocks is reinserted. if a conflict occurs again with the reinserte d stabilization time end timing, the stabilization time is reinserted. therefore do not set the tr igger input interval and control register write interval to 64 clocks or below.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 414 of 870 sep 30, 2010 table 13-3. conversion time selection in hi gh-speed conversion mode (ada0hs1 bit = 1) a/d conversion time ada0fr3 to ada0fr0 bits conversion time (+ stabilization time) f xx = 32 mhz f xx = 20 mhz f xx = 16 mhz f xx = 4 mhz trigger response time 0000 26/f xx (+ 13/f xx ) setting prohibited setting prohibited setting prohibited 6.5 s (+ 3.25 s) 3/f xx 0010 52/f xx (+ 26/f xx ) setting prohibited 2.6 s (+ 1.3 s) 3.25 s (+ 1.625 s) setting prohibited 3/f xx 0010 78/f xx (+ 39/f xx ) setting prohibited 3.9 s (+ 1.95 s) 4.875 s (+ 2.4375 s) setting prohibited 3/f xx 0011 104/f xx (+ 50/f xx ) 3.25 s (+ 1.5625 s) 5.2 s (+ 2.5 s) 6.5 s (+ 3.125 s) setting prohibited 3/f xx 0100 130/f xx (+ 50/f xx ) 4.0625 s (+ 1.5625 s) 6.5 s (+ 2.5 s) 8.125 s (+ 3.125 s) setting prohibited 3/f xx 0101 156/f xx (+ 50/f xx ) 4.875 s (+ 1.5625 s) 7.8 s (+ 2.5 s) 9.75 s (+ 3.125 s) setting prohibited 3/f xx 0110 182/f xx (+ 50/f xx ) 5.6875 s (+ 1.5625 s) 9.1 s (+ 2.5 s) setting prohibited setting prohibited 3/f xx 0111 208/f xx (+ 50/f xx ) 6.5 s (+ 1.5625 s) 10.4 s (+ 2.5 s) setting prohibited setting prohibited 3/f xx 1000 234/f xx (+ 50/f xx ) 7.3125 s (+ 1.5625 s) setting prohibited setting prohibited setting prohibited 3/f xx 1001 260/f xx (+ 50/f xx ) 8.125 s (+ 1.5625 s) setting prohibited setting prohibited setting prohibited 3/f xx 1010 286/f xx (+ 50/f xx ) 8.9375 s (+ 1.5625 s) setting prohibited setting prohibited setting prohibited 3/f xx 1011 312/f xx (+ 50/f xx ) 9.75 s (+ 1.5625 s) setting prohibited setting prohibited setting prohibited 3/f xx other than above setting prohibited remark conversion time: actual a/d co nversion time (2.6 to 10.4 s) stabilization time: a/d converter setup time (1 s or longer) trigger response time: if a software trigger, external trigger, or timer trigger is generated after the stabilization time, it is inserted before the conversion time. in the high-speed conversion mode, the conversion is started after the stabilizat ion time elapsed from the ada0m0.ada0ce bit is set to 1, and a/d conversion is performed only during the conversion time (2.6 to 10.4 s). the a/d conversion end interrupt request signal (intad) is generated immediately after the conversion ends. in continuous conversion mode, the stabilization time is inserted only before the first conversion, and not inserted after the second conversion (the a/d converter remains running). cautions 1. set as 2.6 s conversion time 10.4 s. 2. in the high-speed conversion mode, rewriting of the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers and trigger input ar e prohibited during the stabilization time.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 415 of 870 sep 30, 2010 (3) a/d converter mode register 2 (ada0m2) the ada0m2 register specifies the hardware trigger mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ada0m2 0 0 0 00 ada0tmd1 ada0tmd0 ada0tmd1 0 0 1 1 ada0tmd0 0 1 0 1 specification of hardware trigger mode external trigger mode (when adtrg pin valid edge detected) timer trigger mode 0 (when inttp2cc0 interrupt request generated) timer trigger mode 1 (when inttp2cc1 interrupt request generated) setting prohibited after reset: 00h r/w address: fffff203h 6543210 7 cautions 1. when writing data to the ada0m2 register in the following modes, stop the a/d conversion by clearing the ad0m0.ada0ce bit to 0. after the data is written to the register, enable the a/d conversion ag ain by setting the ada0ce bit to 1. ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode 2. be sure to clear bits 7 to 2 to ?0?.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 416 of 870 sep 30, 2010 (4) a/d converter channel specification register 0 (ada0s) the ada0s register specifies the pin that inputs the analog voltage to be converted into a digital signal. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ada0s 0 0 0 ada0s3 ada0s2 ada0s1 ada0s0 after reset: 00h r/w address: fffff202h ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 setting prohibited setting prohibited setting prohibited setting prohibited ani0 ani0, ani1 ani0 to ani2 ani0 to ani3 ani0 to ani4 ani0 to ani5 ani0 to ani6 ani0 to ani7 ani0 to ani8 ani0 to ani9 ani0 to ani10 ani0 to ani11 setting prohibited setting prohibited setting prohibited setting prohibited ada0s3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ada0s2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ada0s1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ada0s0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 select mode scan mode cautions 1. when writing data to the ada0s register in the following modes, stop the a/d conversion by clearing the ad0m0.ada0ce bit to 0. after the data is written to the register, enable the a/d conversion ag ain by setting the ada0ce bit to 1. ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode 2. be sure to clear bits 7 to 4 to ?0?.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 417 of 870 sep 30, 2010 (5) a/d conversion result regist ers n, nh (ada0crn, ada0crnh) the ada0crn and ada0crnh registers st ore the a/d conversion results. these registers are read-only, in 16-bit or 8-bit units. ho wever, specify the ada0crn register for 16-bit access and the ada0crnh register for 8-bit access. the 10 bits of t he conversion result are read from the higher 10 bits of the ada0crn register, and 0 is read from the lower 6 bits. th e higher 8 bits of the conver sion result are read from the ada0crnh register. caution accessing the ada0crn and ada0crnh register s is prohibited in the following statuses. for details, see 3.4.8 (2) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock after reset: undefined r address: ada0cr0 fffff210h, ada0cr1 fffff212h, ada0cr2 fffff214h, ada0cr3 fffff216h, ada0cr4 fffff218h, ada0cr5 fffff21ah, ada0cr6 fffff21ch, ada0cr7 fffff21eh, ada0cr8 fffff220h, ada0cr9 fffff222h, ada0cr10 fffff224h, ada0cr11 fffff226h ada0crn (n = 0 to 11) ad9 ad8 ad7 ad6 ad0000000 ad1ad2ad3ad4ad5 ad9 ada0crnh (n = 0 to 11) ad8 ad7 ad6 ad5 ad4 ad3 ad2 76 54 32 1 0 after reset: undefined r address: ada0cr0h fffff211h, ada0cr1h fffff213h, ada0cr2h fffff215h, ada0cr3h fffff217h, ada0cr4h fffff219h, ada0cr5h fffff21bh, ada0cr6h fffff21dh, ada0cr7h fffff21fh, ada0cr8h fffff221h, ada0cr9h fffff223h, ada0cr10h fffff225h, ada0cr11h fffff227h caution a write operation to the ada0m0 and ad a0s registers may cause the contents of the ada0crn register to become undefined. afte r the conversion, read the conversion result before writing to the ada0m0 and ada0s registers. correct conversion results may not be read if a sequence other than the above is used.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 418 of 870 sep 30, 2010 the relationship between the analog voltage input to the anal og input pins (ani0 to ani11) and the a/d conversion result (ada0crn register) is as follows. v in sar = int ( av ref0 1,024 + 0.5) ada0cr note = sar 64 or, av ref0 av ref0 (sar ? 0.5) 1,024 v in < (sar + 0.5) 1,024 int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref0 : av ref0 pin voltage ada0cr: value of ada0crn register note the lower 6 bits of the ada0crn register are fixed to 0. the following shows the relationship between the analo g input voltage and the a/d conversion results. figure 13-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ref0 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion results ada0crn sar ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 419 of 870 sep 30, 2010 (6) power-fail compare m ode register (ada0pfm) the ada0pfm register is an 8-bit register that sets the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0pfe power-fail compare disabled power-fail compare enabled ada0pfe 0 1 selection of power-fail compare enable/disable ada0pfm ada0pfc 00 00 0 0 generates an interrupt request signal (intad) when ada0crnh ada0pft generates an interrupt request signal (intad) when ada0crnh < ada0pft ada0pfc 0 1 selection of power-fail compare mode after reset: 00h r/w address: fffff204h <7>6543210 cautions 1. in the select mode, the 8-bit data set to the ada0pft regist er is compared with the value of the ada0crnh register specified by the ada0s register. if the result matches the condition specified by th e ada0pfc bit, the conversion result is stored in the ada0crn register and the intad signal is ge nerated. if it does not match, however, the interrupt signal is not generated. 2. in the scan mode, the 8-bit data set to the ada0pft register is compared with the contents of the ada0cr0h register. if th e result matches the c ondition specified by the ada0pfc bit, the conversion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, however, the intad signal is not generated. regardless of the comparison r esult, the scan operati on is continued and the conversion result is stored in the ada0crn register until the scan operation is completed. however, the intad signal is not generated after th e scan operation has been completed. 3. when writing data to the ada0pfm register in the following modes, stop the a/d conversion by clearing the ad0m0.ada0ce bit to 0. after the data is written to the register, enable the a/d conversion ag ain by setting the ada0ce bit to 1. ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 420 of 870 sep 30, 2010 (7) power-fail compare thres hold value register (ada0pft) the ada0pft register sets the compare value in the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0pft after reset: 00h r/w address: fffff205h 76 54 321 0 caution when writing data to the ada0pft re gister in the following modes, stop the a/d conversion by clearing the ad0m0.ada0ce bit to 0. after the data is written to the register, enable the a/d conversion ag ain by setting the ada0ce bit to 1. ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 421 of 870 sep 30, 2010 13.5 operation 13.5.1 basic operation <1> set the operation mode, trigger mode, and conversion time for executing a/d conversion by using the ada0m0, ada0m1, ada0m2, and ada0s registers. when the ada0ce bit of the ada0m0 register is set, conversion is started in the software trigger mode and the a/d converter wa its for a trigger in the external or timer trigger mode. <2> when a/d conversion is started, the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when the sample & hold circuit samples the input channel for a specific time, it ent ers the hold status, and holds the input analog voltage until a/d conversion is complete. <4> set bit 9 of the successive approximation register (sar) to set the compare voltage generation dac to (1/2) av ref0 . <5> the voltage difference between the voltage of the compare voltage genera tion dac and the analog input voltage is compared by the voltage comparator. if the analog input voltage is higher than (1/2) av ref0 , the msb of the sar register remains set. if it is lower than (1/2) av ref0 , the msb is reset. <6> next, bit 8 of the sar register is automatically set and the next comparison is started. depending on the value of bit 9, to which a result has been already set, the co mpare voltage generation dac is selected as follows. ? bit 9 = 1: (3/4) av ref0 ? bit 9 = 0: (1/4) av ref0 this compare voltage and the analog input voltage ar e compared and, depending on the result, bit 8 is manipulated as follows. analog input voltage compare voltage: bit 8 = 1 analog input voltage compare voltage: bit 8 = 0 <7> this comparison is continued to bit 0 of the sar register. <8> when comparison of the 10 bits is complete, the valid digital result is stored in the sar register, which is then transferred to and stored in the ada0crn register. afte r that, an a/d conversion end interrupt request signal (intad) is generated. <9> in one-shot select mode, conversion is stopped note . in one-shot scan mode, conversion is stopped after scanning once note . in continuous select mode, repeat steps <2> to <8 > until the ada0m0.ada0ce bit is cleared to 0. in continuous scan mode, repeat steps <2> to <8> for each channel. note in the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status is entered. remark the trigger standby status me ans the status after the stabilization time has passed.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 422 of 870 sep 30, 2010 13.5.2 conversion op eration timing figure 13-3. conversion operation timing (continuous conversion) (1) operation in normal conversion mode (ada0hs1 bit = 0) ada0m0.ada0ce bit processing state setup stabilization time conversion time wait time sampling first conversion second conversion setup sampling wait a/d conversion intad signal 2/f xx (max.) 0.5/f xx sampling time (2) operation in high-speed con version mode (ada0hs1 bit = 1) ada0m0.ada0ce bit processing state setup conversion time sampling first conversion second conversion sampling a/d conversion a/d conversion intad signal 0.5/f xx stabilization time 2/f xx (max.) sampling time ada0fr3 to ada0fr0 bits stabilization time conversion time (sampling time) wait time trigger response time 0000 13/f xx 26/f xx (8/f xx ) 27/f xx 3/f xx 0001 26/f xx 52/f xx (16/f xx ) 53/f xx 3/f xx 0010 39/f xx 78/f xx (24/f xx ) 79/f xx 3/f xx 0011 50/f xx 104/f xx (32/f xx ) 105/f xx 3/f xx 0100 50/f xx 130/f xx (40/f xx ) 131/f xx 3/f xx 0101 50/f xx 156/f xx (48/f xx ) 157/f xx 3/f xx 0110 50/f xx 182/f xx (56/f xx ) 183f xx 3/f xx 0111 50/f xx 208/f xx (64/f xx ) 209/f xx 3/f xx 1000 50/f xx 234/f xx (72/f xx ) 235/f xx 3/f xx 1001 50/f xx 260/f xx (80/f xx ) 261/f xx 3/f xx 1010 50/f xx 286/f xx (88/f xx ) 287/f xx 3/f xx 1011 50/f xx 312/f xx (96/f xx ) 313/f xx 3/f xx others setting prohibited remark the above timings are when a trigger generates within the stabilization time. if the trigger generates after the stabilization time, a trigger response time is inserted.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 423 of 870 sep 30, 2010 13.5.3 trigger mode the timing of starting the conversion operation is specified by setting a tri gger mode. the trigger mode includes a software trigger mode and hardware trigger modes. the hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. the ada0m0.ada0tmd bit is used to set the trigger mode. the hardware trigger modes are set by the ada0m2.ada0tmd1 and ada0m2.ada0tmd0 bits. (1) software trigger mode when the ada0m0.ada0ce bit is set to 1, the signal of t he analog input pin (ani0 to ani11 pin) specified by the ada0s register is converted. when conversion is complete , the result is stored in t he ada0crn register. at the same time, the a/d conversion end interr upt request signal (intad) is generated. if the operation mode specified by the ada0m0.ada0md1 and ada0m0.ada0md0 bits is the continuous select/scan mode, the next conversion is started, unless the ada0ce bit is cleared to 0 after completion of the first conversion. conversion is performed once and ends if the operation mode is the one-shot select/scan mode. when conversion is started, the ada0m0.ada0ef bit is set to 1 (indicating that conversion is in progress). if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft regi ster is written during conv ersion, the conversion is aborted and started again from the beginning. however, writing to these registers is prohibited in the normal conversion mode and one-shot select mode/one-s hot scan mode in the high-speed conversion mode. (2) external trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani11) specified by the ada0s register is started when an external trigger is input (to the adtrg pin) . which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both rising a nd falling edges) can be specified by using the ada0m0.ada0ets1 and ada0m0.ata0ets0 bits. when the ada0ce bit is set to 1, the a/d converter waits for the trigger, and starts conversion after the external trigger has been input. when conversion is completed, the result of conversion is stored in the ada0crn register, regardless of whether the continuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ada0md1 and ada0md0 bits. at the same time, the in tad signal is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (i ndicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft regi ster is written during the conversion operation, the conversion is not aborted, and the a/d converter waits for t he trigger again. however, writing to these registers is prohibited in the one-shot select mode/one-shot scan mode. caution to select the external trigger mode, set the high-speed conversion mode. do not input a trigger during stabilization time that is inserted once after the a/d conversion operation is enabled (ada0m0.ada0ce bit = 1). remark the trigger standby status me ans the status after the st abilization time has passed.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 424 of 870 sep 30, 2010 (3) timer trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani11) specified by the ada0s register is started by the compare match interrupt request signal (inttp2cc0 or inttp2cc1) of the capture/compare register connected to the timer. the inttp2cc0 or inttp2cc1 signal is selected by the ada0tmd1 and ada0tmd0 bits, and conversion is started at the rising edge of the specified compare match interrupt request signal. when the ada0ce bit is set to 1, the a/d converter waits for a trigger, and starts conversion when the compare match interrupt request signal of the timer is input. when conversion is completed, regardless of whether the c ontinuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ada0 md1 and ada0md0 bits, the result of the conversion is stored in the ada0crn register. at the same time, t he intad signal is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (i ndicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft regi ster is written during conv ersion, the conversion is stopped and the a/d converter waits for the trigger again. ho wever, writing to these registers is prohibited in the one-shot select mode/one-shot scan mode. caution to select the timer trigger mode, set the high-speed conversion mode. do not input a trigger during stabilization time that is inserted once after the a/d conversion operation is enabled (ada0m0.ada0ce bit = 1). remark the trigger standby status me ans the status after the st abilization time has passed.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 425 of 870 sep 30, 2010 13.5.4 operation mode four operation modes are available as the modes in which to set the ani0 to ani11 pins: continuous select mode, continuous scan mode, one-shot sele ct mode, and one-shot scan mode. the operation mode is selected by the ad a0m0.ada0md1 and ada0m0.ada0md0 bits. (1) continuous select mode in this mode, the voltage of one analog input pin selected by the ada0s register is continuously converted into a digital value. the conversion result is stored in t he ada0crn register corresponding to the analog input pin. in this mode, an analog input pin corresponds to an ada0crn register on a one-to-one basis. each time a/d conversion is completed, the a/d conversion end interrupt request signal (intad) is generated. after completion of conversion, the next conversion is started, unless the ada0m0.ada0ce bit is cleared to 0 (n = 0 to 11). figure 13-4. timing example of continuous se lect mode operation (ada0s register = 01h) ani1 a/d conversion data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 (ani1) data 7 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 6 (ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 (2) continuous scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values. the result of each conversion is stored in the ada0cr n register corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0s r egister is complete, the intad signal is generated, and a/d conversion is started again from the ani0 pin, un less the ada0ce bit is cleared to 0 (n = 0 to 11).
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 426 of 870 sep 30, 2010 figure 13-5. timing example of continuous s can mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 (ani1) data 7 (ani2) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 (ani1) ada0crn intad conversion start set ada0ce bit = 1 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 427 of 870 sep 30, 2010 (3) one-shot select mode in this mode, the voltage on the analog input pin specified by the ada0s register is converted into a digital value only once. the conversion result is stored in t he ada0crn register corresponding to the analog input pin. in this mode, an analog input pin and an ada0crn register correspond on a one-to-one basis. when a/d conversion has been completed once, the intad signal is generated. the a/d conversion operation is stopped after it has been completed (n = 0 to 11). figure 13-6. timing example of one-shot select mode oper ation (ada0s register = 01h) ani1 a/d conversion data 1 (ani1) data 6 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani1) data 6 (ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 conversion end conversion end (4) one-shot scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values. each conversion result is stored in the ada0crn register corresponding to the analog input pin. when conversion of the analog input pin specifi ed by the ada0s register is complete, the intad signal is generated. a/d conversion is stopped after it has been completed (n = 0 to 11).
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 428 of 870 sep 30, 2010 figure 13-7. timing example of one-shot s can mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) ada0crn intad conversion start set ada0ce bit = 1 conversion end ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 429 of 870 sep 30, 2010 13.5.5 power-fail compare mode the a/d conversion end interrupt reques t signal (intad) can be controlled as follows by the ada0pfm and ada0pft registers. ? when the ada0pfm.ada0pfe bit = 0, the intad signal is generated each time conversion is completed (normal use of the a/d converter). ? when the ada0pfe bit = 1 and when the ada0pfm.ada0pf c bit = 0, the value of the ada0crnh register is compared with the value of the ada0pft register when co nversion is completed, and the intad signal is generated only if ada0crnh ada0pft. ? when the ada0pfe bit = 1 and when the ada0pfc bit = 1, the value of the ada0crnh register is compared with the value of the ada0pft register when conversion is completed, and t he intad signal is generated only if ada0crnh < ada0pft. remark n = 0 to 11 in the power-fail compare mode, four modes are available as modes in which to se t the ani0 to ani11 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 430 of 870 sep 30, 2010 (1) continuous select mode in this mode, the result of converti ng the voltage of the analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stor ed in the ada0crn register, and the intad signal is generated. if it does not match, the conversion result is stored in the ada0crn register, and the intad signal is not generated. after completion of the first conversion, t he next conversion is started, unless the ada0m0.ada0ce bit is cleared to 0 (n = 0 to 11). figure 13-8. timing example of continuous select mode operation (when power-fail comparison is made: ada0s register = 01h) ani1 a/d conversion data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 (ani1) data 7 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 6 (ani1) ada0cr1 intad conversion start set ada0ce bit = 1 ada0pft unmatch ada0pft unmatch ada0pft match ada0pft match ada0pft match conversion start set ada0ce bit = 1 (2) continuous scan mode in this mode, the results of converti ng the voltages of the analog input pins sequentially se lected from the ani0 pin to the pin specified by the ada0s regist er are stored, and the set value of t he ada0cr0h register of channel 0 is compared with the value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in t he ada0cr0 register, and the intad signal is generated. if it does not match, the conversion resu lt is stored in the ada0cr0 register , and the intad signal is not generated. after the result of the first conversion has been stored in the ada0cr0 register, the results of sequentially converting the voltages on the analog input pins up to the pin specified by the ada0s register are continuously stored. after completion of conversion, the next conversion is started from the ani0 pin again, unless the ada0ce bit is cleared to 0.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 431 of 870 sep 30, 2010 figure 13-9. timing example of continuous scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 (ani1) data 7 (ani2) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 (ani1) ada0crn intad conversion start set ada0ce bit = 1 ada0pft match ada0pft unmatch ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 432 of 870 sep 30, 2010 (3) one-shot select mode in this mode, the result of converti ng the voltage of the analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stor ed in the ada0crn register, and the intad signal is generated. if it does not match, the conversion result is stored in the ada0crn register, and the intad signal is not generated. conversion is stoppe d after it has been completed. figure 13-10. timing example of on e-shot select mode operation (when power-fail comparison is made: ada0s register = 01h) ani1 a/d conversion data 1 (ani1) data 6 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani1) data 6 (ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 ada0pft match conversion end ada0pft unmatch conversion end (4) one-shot scan mode in this mode, the results of converti ng the voltages of the analog input pins sequentially se lected from the ani0 pin to the pin specified by the ada0s regist er are stored, and the set value of t he ada0cr0h register of channel 0 is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, the conversion result is stored in the ada0cr0 r egister, and the intad0 signal is not generated. after the result of the first conversion has been stored in the ada0cr0 register, the results of converting the signals on the analog input pins specified by the ada0s register are sequentially stored. the conversion is stopped after it has been completed.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 433 of 870 sep 30, 2010 figure 13-11. timing example of on e-shot scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) ada0crn intad conversion start set ada0ce bit = 1 conversion end ada0pft match ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 434 of 870 sep 30, 2010 13.6 cautions (1) when a/d converter is not used when the a/d converter is not used, the power consumpt ion can be reduced by clearing the ada0m0.ada0ce bit to 0. (2) input range of ani0 to ani11 pins input the voltage within the specified range to the ani0 to ani11 pi ns. if a voltage equal to or higher than av ref0 or equal to or lower than av ss (even within the range of the absolute maximu m ratings) is input to any of these pins, the conversion value of that channel is undefined, and the conversion value of the other channels may also be affected. (3) countermeasures against noise to maintain the 10-bit resolution, the ani0 to ani11 pins must be effectively protected fr om noise. the influence of noise increases as the output impeda nce of the analog input source becom es higher. to lower the noise, connecting an external capacitor as shown in figure 13-12 is recommended. figure 13-12. processing of analog input pin av ref0 v dd v ss av ss clamp with a diode with a low v f (0.3 v or less) if noise equal to or higher than av ref0 or equal to or lower than av ss may be generated. ani0 to ani11 (4) alternate i/o the analog input pins (ani0 to ani11) function alternately as port pins. when selecting one of the ani0 to ani11 pins to execute a/d conversion, do not ex ecute an instruction to read an input port or write to an output port during conversion as the conversion resolution may drop. also the conversion resolution may drop at the pins se t as output port pins during a/d conversion if the output current fluctuates due to the effect of the external circuit connected to the port pins. if a digital pulse is applied to a pin adjacent to the pin whose input signal is being co nverted, the a/d conversion value may not be as expected due to the influence of coupl ing noise. therefore, do not apply a pulse to a pin adjacent to the pin undergoing a/d conversion.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 435 of 870 sep 30, 2010 (5) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the ada0s register are changed. if the analog input pin is changed during a/d conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end in terrupt request flag may be set immediately before the ada0s register is rewritten. if the adif flag is read immedi ately after the ada0s register is rewritten, the adif flag may be set even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d conversion is stopped, clear the adif flag before resuming conversion. figure 13-13. generation timing of a/d conversion end interrupt request ada0s rewriting (anin conversion start) ada0s rewriting (anim conversion start) adif is set, but anim conversion does not end a/d conversion ada0crn intad anin anin anim anim anim anin anin anim remark n = 0 to 11 m = 0 to 11 (6) internal equivalent circuit the following shows the equivalent circuit of the analog input block. figure 13-14. internal equi valent circuit of anin pin anin c in r in r in c in 14 k 8.0 pf remarks 1. the above values are reference values. 2. n = 0 to 11
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 436 of 870 sep 30, 2010 (7) av ref0 pin (a) the av ref0 pin is used as the power supply pin of the a/d converter and also supplies power to the alternate- function ports. in an application where a backup power supply is used, be sure to supply the same voltage as v dd to the av ref0 pin as shown in figure 13-15. (b) the av ref0 pin is also used as the reference voltage pin of the a/d converter. if the source supplying power to the av ref0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the cu rrent that flows during conversion (especially, immediately after the conversion operation enable bit ada0ce has been set to 1). as a result, the conversion accuracy may drop. to avoid this, it is recommended to connect a capacitor across the av ref0 and av ss pins to suppress the reference voltage fluctuation as shown in figure 13-15. (c) if the source supplying power to the av ref0 pin has a high dc resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the a/d conversion current. figure 13-15. av ref0 pin processing example av ref0 note av ss main power supply note parasitic inductance (8) reading ada0crn register when the ada0m0 to ada0m2, ada0s, ada0pfm, or ada0pf t register is written, t he contents of the ada0crn register may be undefined. read the conversion result a fter completion of conversion and before writing to the ada0m0 to ada0m2, ada0s, ada0pfm, or ada0pft r egister. also, when an external/timer trigger is acknowledged, the contents of the ada0crn register may be undefined. read the conversion result after completion of conversion and before the next external/timer tr igger is acknowledged. the correct conversion result may not be read at a timing different from the above. (9) standby mode because the a/d converter stops oper ating in the stop mode, conversion results are invalid, so power consumption can be reduced. operatio ns are resumed after the stop mode is released, but the a/d conversion results after the stop mode is released are invalid. when using the a/d converter after the stop mode is released, before setting the stop mode or releasing the stop mode, clear the ada0m0.ada0ce bit to 0 then set the ada0ce bit to 1 after releasing the stop mode. in the idle1, idle2, or subclock operation mode, operation continues. to lower the po wer consumption, therefore, clear the ada0m0.ada0ce bit to 0. in the idle1 and idle2 modes, since the analog input voltage value cannot be retained, the a/d conversion results after the idle1 and idle2 modes are released are invalid. the results of conversions before the idle1 and idle2 modes were set are valid.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 437 of 870 sep 30, 2010 (10) high-speed conversion mode in the high-speed conversion mode, rewriting of the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers and trigger input during t he stabilization time are prohibited. (11) a/d conversion time a/d conversion time is the total time of stabilization ti me, conversion time, wait time, and trigger response time (for details of these times, refer to table 13-2 conversion time sel ection in normal conversion mode (ada0hs1 bit = 0) and table 13-3 conversion time selection in high-speed conversion mode (ada0hs1 bit = 1)). during a/d conversion in the normal conversion m ode, if the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written or a trigger is input, reconv ersion is carried out. however, if the stabilization time end timing conflicts with the writing to these registers, or if the stabilizat ion time end timing conflicts with the trigger input, the stabilization time of 64 clocks is reinserted. if a conflict occurs again with the reinserted stabilization time end timing, the stabilization time is reinserted. therefore do not set the trigger input interval and cont rol register write interval to 64 clocks or below. (12) variation of a/d conversion results the results of the a/d conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. to reduce the variation, take counteractive measures with the program such as averaging the a/d conversion results. (13) a/d conversion result hysteresis characteristics the successive comparison type a/d converter holds the analog input voltage in the internal sample & hold capacitor and then performs a/d conversion. after the a/ d conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur. ? when the same channel is used for a/d conversions, if the voltage is higher or lo wer than the previous a/d conversion, then hysteresis characteri stics may appear where the conversion re sult is affected by the previous value. thus, even if the conversion is perform ed at the same potential, the result may vary. ? when switching the analog input channe l, hysteresis characteristics may app ear where the conversion result is affected by the previous channel value. this is because one a/d converter is used for the a/d conversions. thus, even if the conversion is performed at the same potential, the result may vary.
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 438 of 870 sep 30, 2010 13.7 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that can be recognized, i.e., t he ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit). the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref0 ? 0)/100 = av ref0 /100 when the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between an actually measured value and a theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. the overall error in the characteristics ta ble does not include the quantization error. figure 13-16. overall error ideal line overall error 1 ...... 1 0 ...... 0 0a v ref0 analog input digital output
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 439 of 870 sep 30, 2010 (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog valu e is converted into a digital value. because the a/d converter converts analog input voltages in a range of 1/2 lsb into the same digital codes, a quantization error is unavoidable. this error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. figure 13-17. quantization error quantization error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this is the difference between the actually measured analog input voltage and its theoretic al value when the digital output changes from 0?000 to 0?001 (1/2 lsb). figure 13-18. zero-scale error av ref0 analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10123 100 011 010 001 000 zero-scale error
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 440 of 870 sep 30, 2010 (5) full-scale error this is the difference between the actually measured analog input voltage and its theoretic al value when the digital output changes from 1?110 to 1?111 (full scale ? 3/2 lsb). figure 13-19. full-scale error av ref0 analog input (lsb) digital output (lower 3 bits) 111 av ref0 ? 3 0 av ref0 ? 2av ref0 ? 1 100 011 010 000 full-scale error (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error i ndicates the difference between the actually measured value and its theoretical value when a specific code is output. this i ndicates the basic characteristics of the a/d conversion when the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from av ss to av ref0 . when the input voltage is increased or decreased, or when two or more channels are used, see 13.7 (2) overall error . figure 13-20. differential linearity error ideal width of 1 lsb differential linearity error 1 ...... 1 0 ...... 0 av ref0 analog input digital output
v850es/jg3 chapter 13 a/d converter r01uh0015ej0300 rev.3.00 page 441 of 870 sep 30, 2010 (7) integral linearity error this error indicates the extent to which the conversion char acteristics differ from the ideal linear relationship. it indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. figure 13-21. integral linearity error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output ideal line integral linearity error (8) conversion time this is the time required to obtain a digital output after each trigger has been generated. the conversion time in the characteristics table includes the sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 13-22. sampling time sampling time conversion time
v850es/jg3 chapter 14 d/a converter r01uh0015ej0300 rev.3.00 page 442 of 870 sep 30, 2010 chapter 14 d/a converter 14.1 functions the d/a converter has the following functions. 8-bit resolution 2 channels (da0cs0, da0cs1) r-2r ladder method settling time: 3 s max. (when av ref1 is 3.0 to 3.6 v and external load is 20 pf) analog output voltage: av ref1 m/256 (m = 0 to 255; value set to da0csn register) operation modes: normal mo de, real-time output mode remark n = 0, 1 14.2 configuration the d/a converter configur ation is shown below. figure 14-1. block diagram of d/a converter dacs0 register selector selector dacs1 register ano0 pin ano1 pin da0m.dace0 bit da0m.dace1 bit dacs0 register write da0m.damd0 bit inttp2cc0 signal dacs1 register write da0m.damd1 bit inttp3cc0 signal av ref1 pin av ss pin cautions 1. dac0 and dac1 share the av ref1 pin. 2. dac0 and dac1 share the av ss pin. the av ss pin is also shared by the a/d converter.
v850es/jg3 chapter 14 d/a converter r01uh0015ej0300 rev.3.00 page 443 of 870 sep 30, 2010 the d/a converter includes the following hardware. table 14-1. configuration of d/a converter item configuration control registers d/a converter mode register (da0m) d/a conversion value setting regi sters 0, 1 (da0cs0, da0cs1) 14.3 registers the registers that control the d/ a converter are as follows. ? d/a converter mode register (da0m) ? d/a conversion value setting registers 0, 1 (da0cs0, da0cs1) (1) d/a converter mode register (da0m) the da0m register controls the operation of the d/a converter. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 normal mode real-time output mode note da0mdn 0 1 selection of d/a converter operation mode (n = 0, 1) da0m 0 da0ce1 da0ce0 0 0 da0md1 da0md0 after reset: 00h r/w address: fffff282h disables operation enables operation da0cen 0 1 control of d/a converter operation enable/disable (n = 0, 1) < > < > note the output trigger in the real-time outpu t mode (da0mdn bit = 1) is as follows. ? when n = 0: inttp2cc0 signal (see chapter 7 16-bit timer/event counter p (tmp) ) ? when n = 1: inttp3cc0 signal (see chapter 7 16-bit timer/event counter p (tmp) )
v850es/jg3 chapter 14 d/a converter r01uh0015ej0300 rev.3.00 page 444 of 870 sep 30, 2010 (2) d/a conversion value setting registers 0, 1 (da0cs0, da0cs1) the da0cs0 and da0cs1 registers set the analog volt age value output to the ano0 and ano1 pins. these registers can be read or written in 8-bit units. reset sets these registers to 00h. da0csn7 da0csn da0csn6 da0csn5 da0csn4 da0csn3 da0csn2 da0csn1 da0csn0 after reset: 00h r/w address: da0cs0 fffff280h, da0cs1 fffff281h caution in the real-time output mode (da0m.da0mdn bit = 1), set the da0csn register before the inttp2cc0/inttp3cc0 signals are generated. d/a conversion starts when the inttp2cc0/inttp3cc0 signa ls are generated. remark n = 0, 1
v850es/jg3 chapter 14 d/a converter r01uh0015ej0300 rev.3.00 page 445 of 870 sep 30, 2010 14.4 operation 14.4.1 operation in normal mode d/a conversion is performed using a write operation to the da0csn register as the trigger. the setting method is described below. <1> set the da0m.da0mdn bit to 0 (normal mode). <2> set the analog voltage value to be output to the anon pin to the da0csn register. steps <1> and <2> above constitute the initial settings. <3> set the da0m.da0cen bit to 1 (d/a conversion enable). d/a conversion starts when this setting is performed. <4> to perform subsequent d/a conversions, write to the da0csn register. the previous d/a conversion result is held un til the next d/a conversion is performed. remarks 1. for the alternate-function pin settings, see table 4-15 using port pin as alternate-function pin . 2. n = 0, 1 14.4.2 operation in real-time output mode d/a conversion is performed using the interrupt request signals (inttp2cc0 and inttp3cc0) of tmp2 and tmp3 as triggers. the setting method is described below. <1> set the da0m.da0mdn bit to 1 (real-time output mode). <2> set the analog voltage value to be output to the anon pin to the da0csn register. <3> set the da0m.da0cen bit to 1 (d/a conversion enable). steps <1> to <3> above consti tute the initial settings. <4> operate tmp2 and tmp3. <5> d/a conversion starts when the inttp2cc0 and inttp3cc0 signals are generated. <6> after that, the value set in da0csn register is out put every time the inttp2cc0 and inttp3cc0 signals are generated. remarks 1. the output values of the ano0 and ano1 pins up to <5> above are undefined. 2. for the output values of the ano0 and ano1 pins in the halt, idle1, idle2, and stop modes, see chapter 21 standby function . 3. for the alternate-function pin settings, see table 4-15 using port pin as alternate-function pin .
v850es/jg3 chapter 14 d/a converter r01uh0015ej0300 rev.3.00 page 446 of 870 sep 30, 2010 14.4.3 cautions observe the following cautions when using the d/a converter of the v850es/jg3. (1) do not change the set value of the da0csn register while the trigger signal is being issued in the real-time output mode. (2) before changing the operation mode, be sure to clear the da0m.da0cen bit to 0. (3) when using one of the p10/an00 and p11/an01 pins as an i/ o port and the other as a d/a output pin, do so in an application where the port i/o level do es not change during d/a output. (4) make sure that av ref0 = v dd = av ref1 = 3.0 to 3.6 v. if this range is exceeded, the operation is not guaranteed. (5) apply power to av ref1 at the same timing as av ref0 . (6) no current can be output from the anon pin (n = 0, 1) because the output impedance of the d/a converter is high. when connecting a resistor of 2 m or less, insert a jfet input operati onal amplifier between the resistor and the anon pin. figure 14-2. external pin connection example av ref1 v dd output 10 f 0.1 f 10 f 0.1 f av ref0 anon av ss ? + jfet input operational amplifier (7) because the d/a converter stops operation in the stop mode, the ano0 and ano1 pins go into a high-impedance state, and the power consumption can be reduced. in the idle1, idle2, or subclock operation mode, ho wever, the operation continues. to lower the power consumption, therefore, clear the da0m.da0cen bit to 0.
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 447 of 870 sep 30, 2010 chapter 15 asynchronous ser ial interface a (uarta) 15.1 mode switching of uarta and other serial interfaces 15.1.1 csib4 and uarta0 mode switching in the v850es/jg3, csib4 and uarta0 are alternate functions of the same pin and therefore cannot be used simultaneously. set uarta0 in advance, using the pmc3 and pfc3 registers, before use. caution the transmit/receive operation of csib4 a nd uarta0 is not guarantee d if these functions are switched during transmission or reception. be su re to disable the one that is not used. figure 15-1. csib4 and uarta0 mode switch settings pmc3 after reset: 0000h r/w address: fffff446h, fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, fffff467h 0 0 0 0 0 0 pfc39 pfc38 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfce3l after reset: 00h r/w address: fffff706h 0 0 0 0 0 pfce32 0 0 port i/o mode ascka0 mode sckb4 mode port i/o mode uarta0 mode csib4 mode pmc32 0 1 1 pmc3n 0 1 1 operation mode operation mode pfce32 0 0 pfc32 0 1 pfc3n 0 1 remarks 1. n = 0, 1 2. = don?t care
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 448 of 870 sep 30, 2010 15.1.2 uarta2 and i 2 c00 mode switching in the v850es/jg3, uarta2 and i 2 c00 are alternate functions of the sa me pin and therefore cannot be used simultaneously. set uarta2 in advance, using the pmc3 and pfc3 registers, before use. caution the transmit/receive operation of uarta2 and i 2 c00 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 15-2. uarta2 and i 2 c00 mode switch settings pmc3 after reset: 0000h r/w address: fffff446h, fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, fffff467h 0 0 0 0 0 0 pfc39 pfc38 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 port i/o mode uarta2 mode i 2 c00 mode pmc3n 0 1 1 operation mode pfc3n 0 1 remarks 1. n = 8, 9 2. = don?t care
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 449 of 870 sep 30, 2010 15.1.3 uarta1 and i 2 c02 mode switching in the v850es/jg3, uarta1 and i 2 c02 are alternate functions of the sa me pin and therefore cannot be used simultaneously. set uarta1 in advance, using the pmc9, pfc9, and pmce9 registers, before use. caution the transmit/receive operation of uarta1 and i 2 c02 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 15-3. uarta1 and i 2 c02 mode switch settings pmc9 after reset: 0000h r/w address: fffff452h, fffff453h pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 pfc9 after reset: 0000h r/w address: fffff472h, fffff473h pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 0 0 0 0 0 0 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 pfce9 after reset: 0000h r/w address: fffff712h, fffff713h uarta1 mode i 2 c02 mode pmc9n 1 1 operation mode pfce9n 1 1 pfc9n 0 1 remark n = 0, 1
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 450 of 870 sep 30, 2010 15.2 features transfer rate: 300 bps to 625 kbps (using internal system clock of 32 mhz and dedicated baud rate generator) full-duplex communication: internal uartan receive data register (uanrx) internal uartan transmit data register (uantx) 2-pin configuration: txdan: transmit data output pin rxdan: receive data input pin reception error output function ? parity error ? framing error ? overrun error interrupt sources: 2 ? reception complete interrupt (intuanr): this interrup t occurs upon transfer of receive data from the receive shift register to receive data regist er after serial transfer completion, in the reception enabled status. ? transmission enable interrupt (intuant): this inte rrupt occurs upon transfer of transmit data from the transmit data register to the transmit shift register in the transmission enabled status. character length: 7, 8 bits parity function: odd, even, 0, none transmission stop bit: 1, 2 bits on-chip dedicated baud rate generator msb-/lsb-first transfer selectable transmit/receive data inverted input/output possible sbf (sync break field) transmission/reception in the lin (local interconnect network) communication format possible ? 13 to 20 bits selectable for sbf transmission ? recognition of 11 bits or more possible for sbf reception ? sbf reception flag provided remark n = 0 to 2
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 451 of 870 sep 30, 2010 15.3 configuration the block diagram of the uartan is shown below. figure 15-4. block diagram of asynchronous serial interface an internal bus internal bus uanopt0 uanctl0 uanstr uanctl1 uanctl2 receive shift register uanrx filter selector uantx transmit shift register transmission controller reception controller selector baud rate generator baud rate generator intuanr intuant txdan rxdan f xx to f xx /2 10 ascka0 note reception unit transmission unit clock selector note uarta0 only remarks 1. n = 0 to 2 2. for the configuration of the baud rate generator, see figure 15-16 . uartan includes the following hardware. table 15-1. configuration of uartan item configuration registers uartan control register 0 (uanctl0) uartan control register 1 (uanctl1) uartan control register 2 (uanctl2) uartan option control register 0 (uanopt0) uartan status register (uanstr) uartan receive shift register uartan receive data register (uanrx) uartan transmit shift register uartan transmit data register (uantx)
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 452 of 870 sep 30, 2010 (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register used to specify the uartan operation. (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register used to select the input clock for the uartan. (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register us ed to control the baud rate for the uartan. (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit register used to control serial transfer for the uartan. (5) uartan status register (uanstr) the uanstrn register consists of flags indicating the error contents when a reception error occurs. each one of the reception error flags is set (to 1) upon occurrence of a reception error. (6) uartan receive shift register this is a shift register used to convert the serial data input to the rxdan pin into parallel data. upon reception of 1 byte of data and detection of the stop bit, the rece ive data is transferred to the uanrx register. this register cannot be manipulated directly. (7) uartan receive data register (uanrx) the uanrx register is an 8-bit register that holds receive data. when 7 charac ters are received, 0 is stored in the highest bit (when data is received lsb first). in the reception enabled status, receive data is transferre d from the uartan receive shift register to the uanrx register in synchronization with the completion of shift-in processing of 1 frame. transfer to the uanrx register also causes the reception complete interrupt request signal (intuanr) to be output. (8) uartan transmit shift register the transmit shift register is a shift register used to co nvert the parallel data transferred from the uantx register into serial data. when 1 byte of data is transferred from the uantx register, the shift register data is output from the txdan pin. this register cannot be manipulated directly. (9) uartan transmit data register (uantx) the uantx register is an 8-bit transmit data buffer. trans mission starts when transmit data is written to the uantx register. when data can be written to the uantx register (when data of one frame is transferred from the uantx register to the uartan transmit shift register), the transmission enable interrupt request signal (intuant) is generated.
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 453 of 870 sep 30, 2010 15.4 registers (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register that c ontrols the uartan serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 10h. (1/2) uanpwr disable uartan operation (uartan reset asynchronously) enable uartan operation uanpwr 0 1 uartan operation control uanctl0 (n = 0 to 2) uantxe uanrxe uandir uanps1 uanps0 uancl uansl <6> <5> <4> 3 2 1 after reset: 10h r/w address: ua0ctl0 fffffa00h, ua1ctl0 fffffa10h, ua2ctl0 fffffa20h the uartan operation is controlled by the uanpwr bit. the txdan pin output is fixed to high level by clearing the uanpwr bit to 0 (fixed to low level if uanopt0.uantdl bit = 1). disable transmission operation enable transmission operation uantxe 0 1 transmission operation enable ? to start transmission, set the uanpwr bit to 1 and then set the uantxe bit to 1. to stop, transmission clear the uantxe bit to 0 and then uanpwr bit to 0. ? to initialize the transmission unit, clear the uantxe bit to 0, wait for two cycles of the base clock, and then set the uantxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 15.7 (1) (a) base clock ). disable reception operation enable reception operation uanrxe 0 1 reception operation enable ? to start reception, set the uanpwr bit to 1 and then set the uanrxe bit to 1. to stop reception, clear the uanrxe bit to 0 and then uanpwr bit to 0. ? to initialize the reception unit, clear the uanrxe bit to 0, wait for two periods of the base clock, and then set the uanrxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 15.7 (1) (a) base clock ). <7> 0
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 454 of 870 sep 30, 2010 (2/2) 7 bits 8 bits uancl 0 1 specification of data character length of 1 frame of transmit/receive data ? this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. ? when transmission and reception are performed in the lin format, set the uancl bit to 1. 1 bit 2 bits uansl 0 1 specification of length of stop bit for transmit data this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. ? this register is rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. ? if ?reception with 0 parity? is selected during reception, a parity check is not performed. therefore, the uanstr.uanpe bit is not set. ? when transmission and reception are performed in the lin format, clear the uanps1 and uanps0 bits to 00. no parity output 0 parity output odd parity output even parity output reception with no parity reception with 0 parity odd parity check even parity check uanps1 0 0 1 1 parity selection during transmission parity selection during reception uanps0 0 1 0 1 msb-first transfer lsb-first transfer uandir 0 1 transfer direction selection ? this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. ? when transmission and reception are performed in the lin format, set the uandir bit to 1. remark for details of parity, see 15.6.9 parity types and operations .
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 455 of 870 sep 30, 2010 (2) uartan control register 1 (uanctl1) for details, see 15.7 (2) uartan control register 1 (uanctl1) . (3) uartan control register 2 (uanctl2) for details, see 15.7 (3) uartan control register 2 (uanctl2) . (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit regist er that controls the serial transfer operation of the uartan register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 14h. (1/2) uansrf when the uanctl0.uanpwr bit = uanctl0.uanrxe bit = 0 are set. also upon normal end of sbf reception. during sbf reception uansrf 0 1 sbf reception flag uanopt0 (n = 0 to 2) uansrt uanstt uansls2 uansls1 uansls0 uantdl uanrdl 654321 after reset: 14h r/w address: ua0opt0 fffffa03h, ua1opt0 fffffa13h, ua2opt0 fffffa23h sbf reception trigger uansrt 0 1 sbf reception trigger ? sbf (sync break field) reception is judged during lin communication. ? the uansrf bit is held at 1 when an sbf reception error occurs, and then sbf reception is started again. ? uansrf bit is a read-only bit. ? this is the sbf reception trigger bit during lin communication, and when read, ?0? is always read. for sbf reception, set the uansrt bit (to 1) to enable sbf reception. ? set the uansrt bit after setting the uanpwr bit = uanrxe bit = 1. ? this is the sbf transmission trigger bit during lin communication, and when read, ?0? is always read. ? set the uanstt bit after setting the uanpwr bit = uantxe bit = 1. sbf transmission trigger uanstt 0 1 sbf transmission trigger <7> 0 ? ? caution do not set the uansrt and uanstt bits (to 1) during sbf reception (uansrf bit = 1).
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 456 of 870 sep 30, 2010 (2/2) uansls2 1 1 1 0 0 0 0 1 uansls1 0 1 1 0 0 1 1 0 uansls0 1 0 1 0 1 0 1 0 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output sbf transmit length selection ? the output level of the txdan pin can be inverted using the uantdl bit. ? this register can be set when the uanpwr bit = 0 or when the uantxe bit = 0. this register can be set when the uanpwr bit = 0 or when the uantxe bit = 0. normal output of transfer data inverted output of transfer data uantdl 0 1 transmit data level bit ? the input level of the rxdan pin can be inverted using the uanrdl bit. ? this register can be set when the uanpwr bit = 0 or the uanrxe bit = 0. normal input of transfer data inverted input of transfer data uanrdl 0 1 receive data level bit (5) uartan status register (uanstr) the uanstr register is an 8-bit register that displays t he uartan transfer status and reception error contents. this register can be read or written in 8-bit or 1-bit units , but the uantsf bit is a read-only bit, while the uanpe, uanfe, and uanove bits can both be read and written. howeve r, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained). the initialization conditions are shown below. register/bit initialization conditions uanstr register ? reset ? uanctl0.uanpwr = 0 uantsf bit ? uanctl0.uantxe = 0 uanpe, uanfe, uanove bits ? 0 write ? uanctl0.uanrxe = 0
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 457 of 870 sep 30, 2010 uantsf ? when the uanpwr bit = 0 or the uantxe bit = 0 has been set. ? when, following transfer completion, there was no next data transfer from uantx register write to uantx register uantsf 0 1 transfer status flag uanstr (n = 0 to 2) 0 0 0 0 uanpe uanfe uanove 6 5 4 3 <2> <1> after reset: 00h r/w address: ua0str fffffa04h, ua1str fffffa14h, ua2str fffffa24h the uantsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the uantsf bit = 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the uantsf bit = 1. ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. ? when 0 has been written when parity of data and parity bit do not match during reception. uanpe 0 1 parity error flag ? the operation of the uanpe bit is controlled by the settings of the uanctl0.uanps1 and uanctl0.uanps0 bits. ? the uanpe bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained. ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set ? when 0 has been written when no stop bit is detected during reception uanfe 0 1 framing error flag ? only the first bit of the receive data stop bits is checked, regardless of the value of the uanctl0.uansl bit. ? the uanfe bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained . ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. ? when 0 has been written when receive data has been set to the uanrx register and the next receive operation is completed before that receive data has been read uanove 0 1 overrun error flag ? when an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. ? the uanove bit can be both read and written, but it can only be cleared by writing 0 to it. when 1 is written to this bit, the value is retained . <7> <0>
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 458 of 870 sep 30, 2010 (6) uartan receive data register (uanrx) the uanrx register is an 8-bit buffer r egister that stores paralle l data converted by the receive shift register. the data stored in the receive shift register is transferre d to the uanrx register upon completion of reception of 1 byte of data. during lsb-first reception when the data length has been spec ified as 7 bits, the receive data is transferred to bits 6 to 0 of the uanrx register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the uanrx register and the lsb always becomes 0. when an overrun error (uanove) occurs, the receive data at this time is not transferred to the uanrx register and is discarded. this register is read-only, in 8-bit units. in addition to reset input, the uanrx register can be set to ffh by clearing the uanctl0.uanpwr bit to 0. uanrx (n = 0 to 2) 654321 after reset: ffh r address: ua0rx fffffa06h, ua1rx fffffa16h, ua2rx fffffa26h 7 0 (7) uartan transmit data register (uantx) the uantx register is an 8-bit register used to set transmit data. this register can be read or written in 8-bit units. reset sets this register to ffh. uantx (n = 0 to 2) 654321 after reset: ffh r/w address: ua0tx fffffa07h, ua1tx fffffa17h, ua2tx fffffa27h 7 0
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 459 of 870 sep 30, 2010 15.5 interrupt request signals the following two interrupt request signals are generated from uartan. ? reception complete interrupt request signal (intuanr) ? transmission enable interrupt request signal (intuant) the default priority for these two interrupt request signals is reception complete interrupt request signal then transmission enable interrupt request signal. table 15-2. interrupts and their default priorities interrupt priority reception complete high transmission enable low (1) reception complete interrupt request signal (intuanr) a reception complete interrupt request signal is output when data is shifted into the receive shift register and transferred to the uanrx register in the reception enabled status. a reception complete interrupt request signal is also out put when a reception error occurs. therefore, when a reception complete interrupt request signal is acknowle dged and the data is read, read the uanstr register and check that the reception result is not an error. no reception complete interrupt request signal is generated in the reception disabled status. (2) transmission enable interr upt request signal (intuant) if transmit data is transferred from the uantx register to the uartan transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated.
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 460 of 870 sep 30, 2010 15.6 operation 15.6.1 data format full-duplex serial data reception and transmission is performed. as shown in figure 15-5, one data frame of transmit/receive dat a consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit length within 1 data frame, parity selection, s pecification of the stop bit length, and specification of msb/lsb-first transfer ar e performed using the uanctl0 register. moreover, control of uart output/inverted output for the txdan bit is performed using the uanopt0.uantdl bit. ? start bit ..................1 bit ? character bits ........7 bits/8 bits ? parity bit ................even parity/odd parity/0 parity/no parity ? stop bit ..................1 bit/2 bits
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 461 of 870 sep 30, 2010 figure 15-5. uarta transmit/receive data format (a) 8-bit data length, lsb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit (b) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h, txdan inversion 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (d) 7-bit data length, lsb first, odd pa rity, 2 stop bits, transfer data: 36h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 parity bit stop bit stop bit (e) 8-bit data length, lsb first, no pa rity, 1 stop bit, transfer data: 87h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 462 of 870 sep 30, 2010 15.6.2 sbf transmission/reception format the v850es/jg3 has an sbf (sync break field) transmission/ reception control function to enable use of the lin function. remark lin stands for local interconnect network and is a lo w-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to control the switches, act uators, and sensors, and thes e are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method a nd is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame wit h baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possible when the baud rate error in the slave is 15% or less. figures 15-6 and 15-7 outline the transmissi on and reception manipulations of lin. figure 15-6. lin transmissi on manipulation outline lin bus wake-up signal frame sync break field sync field identifier field data field data field check sum field intuant interrupt txdan (output) note 3 8 bits note 1 note 2 13 bits sbf transmission note 4 55h transmission data transmission data transmission data transmission data transmission notes 1. the interval between each field is controlled by software. 2. sbf output is performed by har dware. the output width is the bit length set by the uanopt0.uansbl2 to uanopt0.uansbl0 bits. if even finer output width adjustments are required, such adjustments can be performed us ing the uanctln.uanbrs7 to uanctln.uanbrs0 bits. 3. 80h transfer in the 8-bit mode is substituted for the wakeup signal frame. 4. a transmission enable interrupt request signal (int uant) is output at the st art of each transmission. the intuant signal is also output at the start of each sbf transmission.
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 463 of 870 sep 30, 2010 figure 15-7. lin recepti on manipulation outline reception interrupt (intuanr) edge detection capture timer disable disable enable rxdan (input) enable note 2 13 bits sbf reception note 3 note 4 note 1 sf reception id reception data transmission data transmission note 5 data transmission lin bus wake-up signal frame sync break field sync field identifier field data field data field check sum field notes 1. the wakeup signal is sent by the pin edge detec tor, uartan is enabled, and the sbf reception mode is set. 2. the receive operation is performed until detection of the stop bit. upon detection of sbf reception of 11 or more bits, normal sbf reception end is judged, and an interrupt signal is output. upon detection of sbf reception of less than 11 bits, an sbf reception error is judged, no interrupt signal is output, and the mode returns to the sbf reception mode. 3. if sbf reception ends normally, an interrupt request signal is output. the timer is enabled by an sbf reception complete interrupt. moreover, error detection for the uanstr.uanove, uanstr.uanpe, and uanstr.uanfe bits is suppressed and uart communication error detection processing and uartan receive shift register and data transfer of the uanrx register are not performed. the uartan receive shift register holds the initial value, ffh. 4. the rxdan pin is connected to ti (capture input) of the timer, the tran sfer rate is calculated, and the baud rate error is calculated. the value of the uanctl2 register obtained by correcting the baud rate error after dropping uarta enable is set again, causing the status to become the reception status. 5. check-sum field distinctions are made by softwar e. uartan is initialized following csf reception, and the processing for setting the sbf reception mode again is performed by software.
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 464 of 870 sep 30, 2010 15.6.3 sbf transmission when the uanctl0.uanpwr bit = uanctl0.uantxe bit = 1, the transmission enabled status is entered, and sbf transmission is started by setting (to 1) the sbf transmission trigger (uanopt0.uanstt bit). thereafter, a low level the width of bi ts 13 to 20 specified by the uanopt0. uansls2 to uanopt0.uansls0 bits is output. a transmission enable interrupt request signal (intua nt) is generated upon sbf transmission start. following the end of sbf transmission, the uanstt bit is automatically cleared. thereafter, t he uart transmission mode is restored. transmission is suspended until the data to be transmitted next is written to the uantx register, or until the sbf transmission trigger (uanstt bit) is set. figure 15-8. sbf transmission intuant interrupt txdan 12345678910111213 stop bit setting of uanstt bit
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 465 of 870 sep 30, 2010 15.6.4 sbf reception the reception enabled status is achieved by setting the uanctl0.uanpwr bit to 1 and then setting the uanctl0.uanrxe bit to 1. the sbf reception wait status is set by setting the sbf reception trigger (uanopt0.uanstr bit) to 1. in the sbf reception wait status, similarly to the uart re ception wait status, the rxdan pin is monitored and start bit detection is performed. following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate. when a stop bit is received, if the sbf width is 11 or more bits, normal processing is judged and a reception complete interrupt request signal (intuanr) is out put. the uanopt0.uansrf bi t is automatically cleared and sbf reception ends. error detection for the uanstr.uanove, uanstr.uanpe, and uanstr.uanfe bits is suppressed and uart communication error detection processing is not performed. mo reover, data transfer of the uartan reception shift register and uanrx register is not performed and ffh, the initial value, is held. if the sbf width is 10 or fewer bits, reception is terminated as error processing without outputting an interrup t, and the sbf reception mode is returned to. the uansrf bit is not cleared at this time. cautions 1. if sbf is tran smitted during a data recepti on, a framing error occurs. 2. do not set the sbf reception trigger bit (uansrt) and sbf transmission trigger bit (uanstt) to 1 during an sbf reception (uansrf = 1). figure 15-9. sbf reception (1/2) (a) normal sbf reception (detection of stop bit in more than 10.5 bits) uansrf rxdan 123456 11.5 7 8 9 10 11 intuanr interrupt
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 466 of 870 sep 30, 2010 figure 15-9. sbf reception (2/2) (b) sbf reception error (detection of stop bit in 10.5 or fewer bits) uansrf rxdan 123456 10.5 78910 intuanr interrupt
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 467 of 870 sep 30, 2010 15.6.5 uart transmission a high level is output to the txdan pin by setting the uanctl0.uanpwr bit to 1. next, the transmission enabled status is set by setting the ua nctl0.uantxe bit to 1, and transmission is started by writing transmit data to the uantx regi ster. the start bit, parity bit, and stop bit are automatically added. since the cts (transmit enable signal) input pin is not prov ided in uartan, use a port to check that reception is enabled at the transmit destination. the data in the uantx register is trans ferred to the uartan transmit shift r egister upon the start of the transmit operation. a transmission enable interrupt request signal (intuant) is generated upon completion of transmission of the data of the uantx register to the uartan transmit shift register, and thereafter the contents of the ua rtan transmit shift register are output to the txdan pin. write of the next transmit data to the uantx register is enabled after the intuant signal is generated. figure 15-10. uart transmission start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuant txdan remark lsb first
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 468 of 870 sep 30, 2010 15.6.6 continuous transmission procedure uartan can write the next transmit data to the uantx register when the uartan tr ansmit shift register starts the shift operation. the transmit timing of the uartan transmit shift register can be judged from the transmission enable interrupt request signal (intuant). an efficient communication rate is realized by writing the data to be transmitted next to the uantx register during transfer. caution when initializing transmissi ons during the execution of contin uous transmissions, make sure that the uanstr.uantsf bit is 0, then perform the initializat ion. transmit data that is initialized when the uantsf bit is 1 cannot be guaranteed. figure 15-11. continuous transmission processing flow start register settings uantx write yes yes no no occurrence of transmission interrupt? required number of writes performed? end
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 469 of 870 sep 30, 2010 figure 15-12. continuous transmission operation timing (a) transmission start start data (1) data (1) txdan uantx transmission shift register intuant uantsf data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start (b) transmission end start data (n ? 1) data (n ? 1) data (n ? 1) data (n) ff data (n) txdan uantx transmission shift register intuant uantsf uanpwr or uantxe bit parity stop stop start data (n) parity parity stop
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 470 of 870 sep 30, 2010 15.6.7 uart reception the reception wait status is set by setting the uanctl0. uanpwr bit to 1 and then setting the uanctl0.uanrxe bit to 1. in the reception wait status, the rxdan pin is monitored and start bit detection is performed. start bit detection is performed using a two-step detection routine. first the rising edge of the rxdan pin is detected and sampling is start ed at the falling edge. the start bit is recognized if the rxdan pin is low level at the st art bit sampling point. after a start bit has been recognized, the receive operation starts, and serial data is saved to the uartan receive shift register according to the set baud rate. when the reception complete interrupt request signal (intuanr) is output upon reception of the stop bit, the data of the uartan receive shift register is written to the uanrx regist er. however, if an overrun error (uanstr.uanove bit) occurs, the receive data at this time is not writt en to the uanrx register and is discarded. even if a parity error (uanstr.uanpe bit) or a framing e rror (uanstr.uanfe bit) occurs during reception, reception continues until the reception position of the first stop bit, and intuanr is output following reception completion. figure 15-13. uart reception start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuanr rxdan uanrx cautions 1. be sure to read the ua nrx register even when a reception erro r occurs. if the uanrx register is not read, an overrun error occurs during reception of the next data, and recep tion errors continue occurring indefinitely. 2. the operation during reception is performed assuming that ther e is only one stop bit. a second stop bit is ignored. 3. when reception is completed, read the uanr x register after the reception complete interrupt request signal (intuanr) has been generated, and clear the uanpwr or uanrxe bit to 0. if the uanpwr or uanrxe bit is cleared to 0 before the intuanr signal is generated, the read value of the uanrx register cannot be guaranteed. 4. if receive completion processing (intuanr signa l generation) of uartan and the uanpwr bit = 0 or uanrxe bit = 0 conflict, the intuanr signal may be generated in spite of these being no data stored in the uanrx register. to complete reception without waiting intuanr signal generati on, be sure to clear (0) the interrupt request flag (uanrif) of the uanric register, after setting (1) the interrupt mask flag (uanrmk) of the interrupt control register (uan ric) and then set (1) the uanpwr bit = 0 or uanrxe bit = 0.
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 471 of 870 sep 30, 2010 15.6.8 reception errors errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. data reception result error flags are set in the uanstr register and a rec eption complete interrupt request signal (intuanr) is output when an error occurs. it is possible to ascertain which error occurred during reception by reading the contents of the uanstr register. clear the reception error flag by writing 0 to it after reading it. ? receive data read flow start no intuanr signal generated? error occurs? end yes no yes error processing read uanrx register read uanstr register caution when an intuanr signal is generated, the ua nstr register must be read to check for errors. ? reception error causes error flag reception error cause uanpe parity error received parity bit does not match the setting uanfe framing error stop bit not detected uanove overrun error reception of next data completed before data was read from receive buffer
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 472 of 870 sep 30, 2010 when reception errors occur, perform the followin g procedures depending upon the kind of error. ? parity error if false data is received due to problems such as noise in the reception line, discard the received data and retransmit. ? framing error a baud rate error may have occurred between the reception side and transmission side or the start bit may have been erroneously detected. since this is a fatal error for the communication format, check the operation stop in the transmission side, perform initialization processing ea ch other, and then start the communication again. ? overrun error since the next reception is completed before reading receiv e data, 1 frame of data is di scarded. if this data was needed, do a retransmission. caution if a receive error interrupt occurs during cont inuous reception, read the contents of the uanstr register must be read before the next recepti on is completed, then pe rform error processing.
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 473 of 870 sep 30, 2010 15.6.9 parity types and operations caution when using the lin function, fix the uanps1 a nd uanps0 bits of the uanctl0 register to 00. the parity bit is used to detect bit errors in the communication data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect odd-count bit errors. in the case of 0 parity and no parity, errors cannot be detected. (a) even parity (i) during transmission the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 1 ? even number of bits whose value is ?1? among transmit data: 0 (ii) during reception the number of bits whose value is ?1 ? among the reception data, including t he parity bit, is counted, and if it is an odd number, a parity error is output. (b) odd parity (i) during transmission opposite to even parity, the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so that it is an odd number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 0 ? even number of bits whose value is ?1? among transmit data: 1 (ii) during reception the number of bits whose value is ?1? among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, parity bit check is not performed. therefore, no parity e rror occurs, regardless of whether the parity bit is 0 or 1. (d) no parity no parity bit is added to the transmit data. reception is performed assuming that ther e is no parity bit. no parity error occurs since there is no parity bit.
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 474 of 870 sep 30, 2010 15.6.10 receive data noise filter this filter samples the rxdan pin using the base clock of the prescaler output. when the same sampling value is read twice, the match dete ctor output changes and the rxdan signal is sampled as the input data. therefore, data not exceed ing 1 clock width is judged to be noise and is not delivered to the internal circuit (see figure 15-15 ). see 15.7 (1) (a) base clock regarding the base clock. moreover, since the circuit is as shown in figure 15-14, t he processing that goes on within the receive operation is delayed by 3 clocks in relation to the external signal status. figure 15-14. noise filter circuit match detector in base clock (f uclk ) rxdan qin ld_en q internal signal c internal signal b in q internal signal a figure 15-15. timing of rxdan signal judged as noise internal signal b base clock rxdan (input) internal signal c mismatch (judged as noise) internal signal a mismatch (judged as noise) match match
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 475 of 870 sep 30, 2010 15.7 dedicated baud rate generator the dedicated baud rate generator consists of a source cl ock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with uartan. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmission and another one for reception. (1) baud rate generator configuration figure 15-16. configuration of baud rate generator f uclk selector uanpwr 8-bit counter match detector baud rate uanctl2: uanbrs7 to uanbrs0 1/2 uanpwr, uantxen bits (or uanrxe bit) uanctl1: uancks3 to uancks0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 ascka0 note note only uarta0 is valid; setting uarta1 and uarta2 is prohibited. remarks 1. n = 0 to 2 2. f xx : main clock frequency f uclk : base clock frequency (a) base clock when the uanctl0.uanpwr bit is 1, the clock sele cted by the uanctl1.uancks3 to uanctl1.uancks0 bits is supplied to the 8-bit counter. this clock is called the base clock (f uclk ). (b) serial clock generation a serial clock can be generated by setting the uanctl1 register and the uanctl2 register (n = 0 to 2). the base clock is selected by uanctl1. uancks3 to uanctl1.uancks0 bits. the frequency division value for the 8-bit count er can be set using the uanctl2.uanbrs7 to uanctl2.uanbrs0 bits.
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 476 of 870 sep 30, 2010 (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register that selects the uartan base clock. this register can be read or written in 8-bit units. reset sets this register to 00h. caution clear the uanctl0.uanpwr bit to 0 before rewriting the uanctl1 register. 0 uanctl1 (n = 0 to 2) 0 0 0 uancks3 uancks2 uancks1 uancks0 654321 after reset: 00h r/w address: ua0ctl1 fffffa01h, ua1ctl1 fffffa11h, ua2ctl1 fffffa21h 7 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 external clock note (ascka0 pin) setting prohibited uancks2 0 0 0 0 1 1 1 1 0 0 0 0 uancks3 0 0 0 0 0 0 0 0 1 1 1 1 base clock (f uclk ) selection uancks1 0 0 1 1 0 0 1 1 0 0 1 1 uancks0 0 1 0 1 0 1 0 1 0 1 0 1 other than above note only uarta0 is valid; setting uarta1 and uarta2 is prohibited. remark f xx : main clock frequency
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 477 of 870 sep 30, 2010 (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of uartan. this register can be read or written in 8-bit units. reset sets this register to ffh. caution clear the uanctl0.uanpwr bit to 0 or clear the uantxe and uanrxe bits to 00 before rewriting the uanctl2 register. uanbrs7 uanctl2 (n = 0 to 2) uanbrs6 uanbrs5 uanbrs4 uanbrs3 uanbrs2 uanbrs1 uanbrs0 654321 after reset ffh r/w address: ua0ctl2 fffffa02h, ua1ctl2 fffffa12h, ua2ctl2 fffffa22h 7 0 uan brs7 0 0 0 0 : 1 1 1 1 uan brs6 0 0 0 0 : 1 1 1 1 uan brs5 0 0 0 0 : 1 1 1 1 uan brs4 0 0 0 0 : 1 1 1 1 uan brs3 0 0 0 0 : 1 1 1 1 uan brs2 0 1 1 1 : 1 1 1 1 uan brs1 0 0 1 : 0 0 1 1 uan brs0 0 1 0 : 0 1 0 1 default (k) 4 5 6 : 252 253 254 255 serial clock f uclk /4 f uclk /5 f uclk /6 : f uclk /252 f uclk /253 f uclk /254 f uclk /255 setting prohibited remark f uclk : clock frequency selected by the uanctl1.uancks3 to uanctl1.uancks0 bits
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 478 of 870 sep 30, 2010 (4) baud rate the baud rate is obtained by the following equation. baud rate = [bps] when using the internal clock, the equation will be as follows (when using the ascka0 pin as clock at uarta0, calculate using the above equation). baud rate = [bps] remark f uclk = frequency of base clock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits f xx : main clock frequency m = value set using the uanctl1.uancks3 to uanctl1.uancks0 bits (m = 0 to 10) k = value set using the uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (k = 4 to 255) the baud rate error is obtained by the following equation. error (%) = ? 1 100 [%] = ? 1 100 [%] when using the internal clock, the equation will be as follows (when using the ascka0 pin as clock at uarta0, calculate the baud rate error using the above equation). error (%) = ? 1 100 [%] cautions 1. the baud rate erro r during transmission must be wit hin the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in (5) allowable baud rate range dur ing reception. f uclk 2 k actual baud rate (baud rate with error) target baud rate (correct baud rate) f xx 2 m+1 k f uclk 2 k target baud rate f xx 2 m+1 k target baud rate
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 479 of 870 sep 30, 2010 to set the baud rate, perform the following calculation for setting the uanctl1 and uanctl2 registers (when using internal clock). <1> set k to fxx/(2 target baud rate) and m to 0. <2> if k is 256 or greater (k 256), reduce k to half (k/2) and increment m by 1 (m + 1). <3> repeat step <2> until k becomes less than 256 (k < 256). <4> round off the first decimal point of k to the nearest whole number. if k becomes 256 after round-off, perform step <2> again to set k to 128. <5> set the value of m to uanctl1 register and the value of k to the uanctl2 register. example: when f xx = 32 mhz and target baud rate = 153,600 bps <1> k = 32,000,000/(2 153,600) = 104.16?, m = 0 <2>, <3> k = 104.16? < 256, m = 0 <4> set value of uanctl2 register: k = 104 = 68h, set value of uanctl1 register: m = 0 actual baud rate = 32,000,000/(2 104) = 153,846 [bps] baud rate error = {32,000,000/(2 104 153,600) ? 1} 100 = 0.160 [%] the representative examples of baud rate settings are shown below. table 15-3. baud rate generator setting data baud rate f xx = 32 mhz f xx = 20 mhz f xx = 10 mhz (bps) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) 300 08h d0h 0.16 08h 82h 0.16 07h 82h 0.16 600 07h d0h 0.16 07h 82h 0.16 06h 82h 0.16 1,200 06h d0h 0.16 06h 82h 0.16 05h 82h 0.16 2,400 05h d0h 0.16 05h 82h 0.16 04h 82h 0.16 4,800 04h d0h 0.16 04h 82h 0.16 03h 82h 0.16 9,600 03h d0h 0.16 03h 82h 0.16 02h 82h 0.16 19,200 02h d0h 0.16 02h 82h 0.16 01h 82h 0.16 31,250 02h 80h 0.00 01h a0h 0.00 00h a0h 0.00 38,400 01h d0h 0.16 01h 82h 0.16 00h 82h 0.16 76,800 00h d0h 0.16 00h 82h 0.16 00h 41h 0.16 153,600 00h 68h 0.16 00h 41h 0.16 00h 21h ? 1.36 312,500 00h 33h 0.39 00h 20h 0.00 00h 10h 0.00 625,000 00h 1ah ? 1.54 00h 10h 0.00 00h 08h 0.00 remark f xx : main clock frequency err: baud rate error (%)
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 480 of 870 sep 30, 2010 (5) allowable baud rate range during reception the baud rate error range at the destination that is allowable during reception is shown below. caution the baud rate error durin g reception must be set within the allowable error range using the following equation. figure 15-17. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartan transfer rate start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0 to 2 as shown in figure 15-17, the receive data latch timi ng is determined by the counter set using the uanctl2 register following start bit detection. t he transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, t he following is the theoretical result. fl = (brate) ? 1 brate: uartan baud rate (n = 0 to 2) k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 2) fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: flmin = 11 fl ? fl = fl k ? 2 2k 21k + 2 2k
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 481 of 870 sep 30, 2010 therefore, the maximum baud rate that can be re ceived by the destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, obtaining the following maximum allowable transfer rate yields the following. flmax = 11 fl ? fl = fl flmax = fl 11 therefore, the minimum baud rate that can be received by the destination is as follows. brmin = (flmax/11) ? 1 = brate obtaining the allowable baud rate error for uartan and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. table 15-4. maximum/minimum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.32% ? 2.43% 8 +3.52% ? 3.61% 20 +4.26% ? 4.30% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.72% remarks 1. the reception accuracy depends on the bi t count in 1 frame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 2) 10 11 k + 2 2 k 21k ? 2 2 k 21k ? 2 20 k 22k 21k + 2 20k 21k ? 2
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 482 of 870 sep 30, 2010 (6) baud rate during cont inuous transmission during continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. however, timing initialization is performed via st art bit detection by the receiving side, so this has no influence on the transfer result. figure 15-18. transfer rate during continuous transfer start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of 2nd byte start bit bit 0 assuming 1 bit data length: fl; stop bit length: flstp; and base clock frequency: f uclk , we obtain the following equation. flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + (2/f uclk )
v850es/jg3 chapter 15 asynchronous serial interface a (uarta) r01uh0015ej0300 rev.3.00 page 483 of 870 sep 30, 2010 15.8 cautions (1) when the clock supply to uartan is stopped (for exampl e, in idle1, idle2, or st op mode), the operation stops with each register retaining the value it had immediat ely before the clock supply was stopped. the txdan pin output also holds and outputs the valu e it had immediately before the clock supply was stopped. however, the operation is not guaranteed after the clock supply is resum ed. therefore, after the clock supply is resumed, the circuits should be initialized by setting the uanctl0. uanpwr, uanctl0.uanrxen, and uanctl0.uantxen bits to 000. (2) the rxda1 and kr7 pins must not be us ed at the same time. to use the rxda 1 pin, do not use the kr7 pin. to use the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear pfce91 bit to 0). (3) in uartan, the interrupt caused by a communication error does not occur. when performing the transfer of transmit data and receive data using dma transfer, error processing cannot be performed even if errors (parity, overrun, framing) occur during transfer. either read the uanstr register after dma transfer has been completed to make sure that there are no errors, or read the ua nstr register during communication to check for errors. (4) start up the uartan in the following sequence. <1> set the uanctl0.uanpwr bit to 1. <2> set the ports. <3> set the uanctl0.uantxe bit to 1, uanctl0.uanrxe bit to 1. (5) stop the uartan in the following sequence. <1> set the uanctl0.uantxe bit to 0, uanctl0.uanrxe bit to 0. <2> set the ports and set the uanctl0.uanpwr bit to 0 (it is not a problem if port setting is not changed). (6) in transmit mode (uanctl0.uanpwr bit = 1 and uanctl0. uantxe bit = 1), do not overwrite the same value to the uantx register by software because transmission starts by writing to this register. to transmit the same value continuously, overwrite the same value. (7) in continuous transmission, the communication rate from the stop bit to the next start bit is extended 2 base clocks more than usual. however, the reception side initializes the timing by detecting the start bit, so the reception result is not affected.
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 484 of 870 sep 30, 2010 chapter 16 3-wire variable-length serial i/o (csib) 16.1 mode switching of csib and other serial interfaces 16.1.1 csib4 and uarta0 mode switching in the v850es/jg3, csib4 and uarta0 are alternate functions of the same pin and therefore cannot be used simultaneously. set csib4, in advance, using the pmc3 and pfc3 registers, before use. caution the transmit/receive operation of csib4 a nd uarta0 is not guarantee d if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 16-1. csib4 and uarta0 mode switch settings pmc3 after reset: 0000h r/w address: fffff446h, fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, fffff467h 0 0 0 0 0 0 pfc39 pfc38 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfce3l after reset: 00h r/w address: fffff706h 0 0 0 0 0 pfce32 0 0 port i/o mode ascka0 mode sckb4 mode port i/o mode uarta0 mode csib4 mode pmc32 0 1 1 pmc3n 0 1 1 operation mode operation mode pfce32 0 0 pfc32 0 1 pfc3n 0 1 remarks 1. n = 0, 1 2. = don?t care
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 485 of 870 sep 30, 2010 16.1.2 csib0 and i 2 c01 mode switching in the v850es/jg3, csib0 and i 2 c01 are alternate functions of the same pin and therefore cannot be used simultaneously. set csib0 in advance, using the pmc4 and pfc4 registers, before use. caution the transmit/receive operation of csib0 and i 2 c01 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 16-2. csib0 and i 2 c01 mode switch settings port i/o mode csib0 mode i 2 c01 mode pmc4n 0 1 1 operation mode pfc4n 0 1 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 after reset: 00h r/w address: fffff448h pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 remarks 1. n = 0, 1 2. = don?t care 16.2 features transfer rate: 8 mbps (f xx = 32 mhz, using internal clock) master mode and slave mode selectable 8-bit to 16-bit transfer, 3-wire serial interface interrupt request signals (intcbnt, intcbnr) 2 serial clock and data phase switchable transfer data length selectable in 1-bit units between 8 and 16 bits transfer data msb-first/lsb-first switchable 3-wire transfer sobn: serial data output sibn: serial data input sckbn: serial clock i/o transmission mode, reception mode, and transmission/reception mode specifiable remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 486 of 870 sep 30, 2010 16.3 configuration the following shows the block diagram of csibn. figure 16-3. block diagram of csibn internal bus cbnctl2 cbnctl0 cbnstr controller intcbnr f cclk sobn intcbnt cbntx so latch phase control shift register cbnrx cbnctl1 phase control sibn f brgm f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 sckbn selector remarks f cclk : communication clock n = 0 to 4 f xx : main clock frequency m = 1 (n = 0, 1) f brgm : brgm count clock m = 2 (n = 2, 3) m = 3 (n = 4) csibn includes the following hardware. table 16-1. configuration of csibn item configuration registers csibn receive data register (cbnrx) csibn transmit data register (cbntx) control registers csibn control register 0 (cbnctl0) csibn control register 1 (cbnctl1) csibn control register 2 (cbnctl2) csibn status register (cbnstr)
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 487 of 870 sep 30, 2010 (1) csibn receive data register (cbnrx) the cbnrx register is a 16-bit buffer register that holds receive data. this register is read-only, in 16-bit units. the receive operation is started by reading the cbnrx register in the reception enabled status. if the transfer data length is 8 bits, the lower 8 bits of th is register are read-only in 8-bit units as the cbnrxl register. reset sets this register to 0000h. in addition to reset input, the cbnrx register can be initia lized by clearing (to 0) the cbnpwr bit of the cbnctl0 register. after reset: 0000h r address: cb0rx fffffd04h, cb1rx fffffd14h, cb2rx fffffd24h, cb3rx fffffd34h, cb4rx fffffd44h cbnrx (n = 0 to 4) (2) csibn transmit data register (cbntx) the cbntx register is a 16-bit buffer regist er used to write the csibn transfer data. this register can be read or written in 16-bit units. the transmit operation is started by writing data to t he cbntx register in the transmission enabled status. if the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the cbntxl register. reset sets this register to 0000h. after reset 0000h r/w address: cb0tx fffffd06h, cb1tx fffffd16h, cb2tx fffffd26h, cb3tx fffffd36h, cb4tx fffffd46h cbntx (n = 0 to 4) remark the communication start conditions are shown below. transmission mode (cbntxe bit = 1, cbnrxe bit = 0): write to cbntx register transmission/reception mode (cbntxe bit = 1, cb nrxe bit = 1): write to cbntx register reception mode (cbntxe bit = 0, cbnrxe bit = 1): read from cbnrx register
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 488 of 870 sep 30, 2010 16.4 registers the following registers are used to control csibn. ? csibn control register 0 (cbnctl0) ? csibn control register 1 (cbnctl1) ? csibn control register 2 (cbnctl2) ? csibn status register (cbnstr) (1) csibn control register 0 (cbnctl0) cbnctl0 is a register that controls the csibn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. (1/3) cbnpwr disable csibn operation and reset the cbnstr register enable csibn operation cbnpwr 0 1 specification of csibn operation disable/enable cbnctl0 (n = 0 to 4) cbntxe note cbnrxe note cbndir note 00 cbntms note cbnsce after reset: 01h r/w address: cb0ctl0 fffffd00h, cb1ctl0 fffffd10h, cb2ctl0 fffffd20h, cb3ctl0 fffffd30h, cb4ctl0 fffffd40h ? the cbnpwr bit controls the csibn operation and resets the internal circuit. disable transmit operation enable transmit operation cbntxe note 0 1 specification of transmit operation disable/enable ? the sobn output is low level when the cbntxe bit is 0. ? when the cbnrxe bit is cleared to 0, no reception complete interrupt is output even when the prescribed data is transferred in order to disable the receive operation, and the receive data (cbnrx register) is not updated. disable receive operation enable receive operation cbnrxe note 0 1 specification of receive operation disable/enable < > < > < > < > < > note these bits can only be rewritten when the cbnpwr bit = 0. however, cbnpwr bit = 1 can also be set at the same time as rewriting these bits. caution to forcibly suspend transm ission/reception, clear the cbnpwr bit to 0 instead of the cbnrxe and cbntxe bits. at this time, the clock output is stopped.
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 489 of 870 sep 30, 2010 (2/3) single transfer mode continuous transfer mode cbntms note 0 1 transfer mode specification [in single transfer mode] the reception complete interrupt request signal (intcbnr) is generated. even if transmission is enabled (cbntxe bit = 1), the transmission enable interrupt request signal (intcbnt) is not generated. if the next transmit data is written during communication (cbnstr.cbntsf bit = 1), it is ignored and the next communication is not started. also, if reception-only communication is set (cbntxe bit = 0, cbnrxe bit = 1), the next communication is not started even if the receive data is read during communication (cbnstr. cbbtsf bit = 1). [in continuous transfer mode] the continuous transmission is enabled by writing the next transmit data during communication (cbnstr.cbntsf bit = 1). writing the next transmission data is enabled after a transmission enable interrupt (intcbnt) occurrence. if reception-only communication is set (cbntxe bit = 0, cbnrxe bit = 1) in the continuous transfer mode, the next reception is started continuously after a reception complete interrupt (intcbnr) regardless of the read operation of the cbnrx register. therefore, read immediately the receive data from the cbnrx register. if this read operation is delayed, an overrun error (cbnove bit = 1) occurs. cbndir note 0 1 specification of transfer direction mode (msb/lsb) msb-first transfer lsb-first transfer note these bits can only be rewritten when the cbnpwr bit = 0. however, cbnpwr bit = 1 can also be set at the same time as rewriting these bits.
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 490 of 870 sep 30, 2010 (3/3) communication start trigger invalid communication start trigger valid cbnsce 0 1 specification of start transfer disable/enable ? in master mode this bit enables or disables the communication start trigger. (a) in single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode the setting of the cbnsce bit has no influence on communication operation. (b) in single reception mode clear the cbnsce bit to 0 before reading the last receive data because reception is started by reading the receive data (cbnrx register) to disable the reception startup note 1 . (c) in continuous reception mode clear the cbnsce bit to 0 one communication clock before reception of the last data is completed to disable the reception startup after the last data is received note 2 . ? in slave mode this bit enables or disables the communication start trigger. set the cbnsce bit to 1. [usage of cbnsce bit] ? in single reception mode <1>when reception of the last data is completed by intcbnr interrupt servicing, clear the cbnsce bit to 0 before reading the cbnrx register. <2>after confirming the cbnstr.cbntsf bit = 0, clear the cbnrxe bit to 0 to disable reception. to continue reception, set the cbnsce bit to 1 to start up the next reception by dummy-reading the cbnrx register. ? in continuous reception mode <1>clear the cbnsce bit to 0 during the reception of the last data by intcbnr interrupt servicing. <2>read the cbnrx register. <3>read the last reception data by reading the cbnrx register after acknowledging the cbntir interrupt. <4>after confirming the cbnstr.cbntsf bit = 0, clear the cbnrxe bit to 0 to disable reception. to continue reception, set the cbnsce bit to 1 to wait for the next reception by dummy-reading the cbnrx register. notes 1. if the cbnsce bit is read while it is 1, the next communication operation is started. 2. the cbnsce bit is not cleared to 0 one communication clock before the completion of the last data reception, the next communication operation is automatically started. caution be sure to clear bits 3 and 2 to ?0?.
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 491 of 870 sep 30, 2010 (2) csibn control register 1 (cbnctl1) cbnctl1 is an 8-bit register that controls the csibn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution the cbnctl1 register can be rewritte n only when the cbnc tl0.cbnpwr bit = 0. 0 cbnckp 0 0 1 1 specification of data transmission/ reception timing in relation to sckbn cbnctl1 (n = 0 to 4) 0 cbndap 0 1 0 1 0 cbnckp cbndap cbncks2 cbncks1 cbncks0 after reset 00h r/w address: cb0ctl1 fffffd01h, cb1ctl1 fffffd11h, cb2ctl1 fffffd21h, cb3ctl1 fffffd31h, cb4ctl1 fffffd41h cbncks2 0 0 0 0 1 1 1 1 cbncks1 0 0 1 1 0 0 1 1 cbncks0 0 1 0 1 0 1 0 1 communication clock (f cclk ) note f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f brgm external clock (sckbn) master mode master mode master mode master mode master mode master mode master mode slave mode mode d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) communication type 1 communication type 2 communication type 3 communication type 4 note set the communication clock (f cclk ) to 8 mhz or lower. remark when n = 0 or 1, m = 1 when n = 2 or 3, m = 2 when n = 4, m = 3 for details of f brgm , see 16.8 baud rate generator .
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 492 of 870 sep 30, 2010 (3) csibn control register 2 (cbnctl2) cbnctl2 is an 8-bit register that controls the number of csibn serial transfer bits. this register can be read or written in 8-bit units. reset sets this register to 00h. caution the cbnctl2 register can be rewritten on ly when the cbnctl0.cbnpw r bit = 0 or when both the cbntxe and cbnrxe bits = 0. after reset: 00h r/w address: cb0ctl2 fffffd02h, cb1ctl2 fffffd12h, cb2ctl2 fffffd22h, cb3ctl2 fffffd32h, cb4ctl2 fffffd42h 0 cbnctl2 (n = 0 to 4) 0 0 0 cbncl3 cbncl2 cbncl1 cbncl0 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits 16 bits cbncl3 0 0 0 0 0 0 0 0 1 cbncl2 0 0 0 0 1 1 1 1 cbncl1 0 0 1 1 0 0 1 1 cbncl0 0 1 0 1 0 1 0 1 serial register bit length remarks 1. if the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the lsb of the cbntx and cbnrx registers. 2. : don?t care
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 493 of 870 sep 30, 2010 (a) transfer data length change function the csibn transfer data length can be set in 1-bit uni ts between 8 and 16 bits using the cbnctl2.cbncl3 to cbnctl2.cbncl0 bits. when the transfer bit length is set to a value other than 16 bits, set the data to the cbntx or cbnrx register starting from the lsb, regardless of w hether the transfer start bit is the m sb or lsb. any data can be set for the higher bits that are not us ed, but the receive data becomes 0 following serial transfer. (i) transfer bit length = 10 bits, msb first 15 10 9 0 sobn sibn insertion of 0 (ii) transfer bit length = 12 bits, lsb first 0 sobn 11 12 15 sibn insertion of 0
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 494 of 870 sep 30, 2010 (4) csibn status register (cbnstr) cbnstr is an 8-bit register t hat displays the csibn status. this register can be read or written in 8-bit or 1-bit units, but the cbntsf flag is read-only. reset sets this register to 00h. in addition to reset input, the cbnstr register can be initialized by clearing (0) the cbnctl0.cbnpwr bit. cbntsf communication stopped communicating cbntsf 0 1 communication status flag cbnstr (n = 0 to 4) 00 0 00 0 cbnove after reset 00h r/w address: cb0str fffffd03h, cb1str fffffd13h, cb2str fffffd23h, cb3str fffffd33h, cb4str fffffd43h ? during transmission, this register is set when data is prepared in the cbntx register, and during reception, it is set when a dummy read of the cbnrx register is performed. when transfer ends, this flag is cleared to 0 at the last edge of the clock. no overrun overrun cbnove 0 1 overrun error flag ? an overrun error occurs when the next reception completes without reading the value of the receive buffer by cpu, upon completion of the receive operation. the cbnove flag displays the overrun error occurrence status in this case. ? the cbnove bit is valid also in the single transfer mode. therefore, when only using transmission, note the following. ? do not check the cbnove flag. ? read this bit even if reading the reception data is not required. ? the cbnove flag is cleared by writing 0 to it. it cannot be set even by writing 1 to it. < > < >
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 495 of 870 sep 30, 2010 16.5 interrupt request signals csibn can generate the following two types of interrupt request signals. ? reception complete interrupt request signal (intcbnr) ? transmission enable interrupt request signal (intcbnt) of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower. table 16-2. interrupts and their default priority interrupt priority reception complete high transmission enable low (1) reception complete interrupt request signal (intcbnr) when receive data is transferred to the cbnrx register whil e reception is enabled, the reception complete interrupt request signal is generated. this interrupt request signal can also be generated if an overrun error occurs. when the reception complete interrupt request signal is acknowledged and the data is read, read the cbnstr register to check that the result of reception is not an error. in the single transfer mode, the intcbnr interrupt requ est signal is generated upon completion of transmission, even when only transmission is executed. (2) transmission enable interr upt request signal (intcbnt) in the continuous transmission or continuous transmissio n/reception mode, transmit data is transferred from the cbntx register and, as soon as writ ing to cbntx has been enabled, the transmission enable interrupt request signal is generated. in the single transmission and single transmission/receptio n modes, the intcbnt interrupt is not generated.
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 496 of 870 sep 30, 2010 16.6 operation 16.6.1 single transfer mode (mast er mode, transmission mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bi ts = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start no (1), (2), (3) (4) (5) (6) (8) no (7) intcbnr interrupt generated? transmission completed? end yes yes cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register c1h write cbntx register start transmission cbnctl0 00h remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 497 of 870 sep 30, 2010 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) sobn pin intcbnr signal (1) write 00h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c1h to the cbnctl0 register, and select t he transmission mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writ ing the transmit data to the cbntx register, and transmission is started. (5) when transmission is started, output the serial clock to the sc kbn pin, and output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transmission of the transfer data length se t with the cbnctl2 register is completed, stop the serial clock output and transmit data output, generate the reception completion interrupt request signal (intcbnr) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue transmission, start the next transmission by writing the transmit dat a to the cbntx register again after the intcbnr signal is generated. (8) to end transmission, write the cbnctl0.cb npwr bit = 0 and the cbnctl0.cbntxe bit = 0. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 498 of 870 sep 30, 2010 16.6.2 single transfer mode (master mode, reception mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bi ts = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start no intcbnr interrupt generated? reception completed? end yes yes no (7) cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnctl0 register 00h read cbnrx register read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register a1h start reception (1), (2), (3) (4) (5) (6) (8) (9) (10) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 499 of 870 sep 30, 2010 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (10) (8) (9) sibn pin sibn pin capture timing intcbnr signal (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a1h to the cbnctl0 register, and select t he reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by per forming a dummy read of the cbnrx register, and reception is started. (5) when reception is started, out put the serial clock to the sckbn pi n, and capture the receive data of the sibn pin in synchronization with the serial clock. (6) when reception of the transfer data length set with the cbnctl2 regist er is completed, stop the serial clock output and data capturing, gener ate the reception completion interrupt request signal (intcbnr) at the last edge of the serial clo ck, and clear the cbntsf bit to 0. (7) to continue reception, read the cbnrx register with the cbnctl0.cbnsce bit = 1 remained after the intcbnr signal is generated. (8) to read the cbnrx register without starting the next reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) to end reception, write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 500 of 870 sep 30, 2010 16.6.3 single transfer mode (master mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bi ts = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (7), (9) (5) (6) (10) no (8) transmission/reception completed? end yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register e1h write cbntx register read cbnrx register start transmission/reception cbnctl0 00h no intcbnr interrupt generated? yes yes remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 501 of 870 sep 30, 2010 (2) operation timing sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (8) (7) (10) (9) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 sobn pin sibn pin capture timing intcbnr signal (1) write 00h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e1h to the cbnctl0 register, and select the transmission/reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writ ing the transmit data to the cbntx register, and transmission/reception is started. (5) when transmission/reception is st arted, output the serial clock to the sckbn pin, output the transmit data to the sobn pin in synchronization with the seri al clock, and capture the re ceive data of the sibn pin. (6) when transmission/reception of t he transfer data length set with the cbnctl2 register is completed, stop the serial clock output, transmit data outpu t, and data capturing, generate the reception completion interrupt request signal (intcbnr) at t he last edge of the serial clock, and clear the cbntsf bit to 0. (7) read the cbnrx register. (8) to continue transmission/reception, write t he transmit data to the cbntx register again. (9) read the cbnrx register. (10) to end transmission/reception, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bit = 0. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 502 of 870 sep 30, 2010 16.6.4 single transfer mode (s lave mode, transmission mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start no (1), (2), (3) (4) (5) (4) (6) (8) no (7) intcbnr interrupt generated? transmission completed? end yes yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register c1h write cbntx register start transmission cbnctl0 00h no yes sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 503 of 870 sep 30, 2010 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) sobn pin intcbnr signal (1) write 07h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c1h to the cbnctl0 register, and select t he transmission mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transmission of the transfer data length se t with the cbnctl2 register is completed, stop the serial clock input and transmit data output, generate the reception completion interrupt request signal (intcbnr) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue transmission, write the transmit data to the cbntx register again after the intcbnr signal is generated, and wait for a serial clock input. (8) to end transmission, write the cbnctl0.cb npwr bit = 0 and the cbnctl0.cbntxe bit = 0. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 504 of 870 sep 30, 2010 16.6.5 single transfer mode (slave mode, reception mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start reception completed? end yes no (7) cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnctl0 register 00h read cbnrx register read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register a1h start reception no intcbnr interrupt generated? yes no yes (1), (2), (3) (4) (5) (4) (6) (6) (8) (9) (10) sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 505 of 870 sep 30, 2010 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (10) (8) (9) sibn pin sibn pin capture timing intcbnr signal (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a1h to the cbnctl0 register, and select t he reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by perf orming a dummy read of the cbnrx register, and the device waits for a serial clock input. (5) when a serial clock is input, capture the receive data of the sibn pin in syn chronization with the serial clock. (6) when reception of the transfer data length set with the cbnctl2 regist er is completed, stop the serial clock input and data capturing, generate the reception completion interrupt request signal (intcbnr) at the last edge of the serial clo ck, and clear the cbntsf bit to 0. (7) to continue reception, read the cbnrx register with the cbnctl0.cbnsce bit = 1 remained after the intcbnr signal is generated, and wait for a serial clock input. (8) to end reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) to end reception, write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 506 of 870 sep 30, 2010 16.6.6 single transfer mode (slave mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (7), (9) (5) (4) (6) (10) no (8) transmission/reception completed? end yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register e1h write cbntx register read cbnrx register start transmission/reception cbnctl0 00h no intcbnr interrupt generated? yes no yes sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 507 of 870 sep 30, 2010 (2) operation timing sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (8) (7) (10) (9) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sobn pin sibn pin capture timing intcbnr signal (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e1h to the cbnctl0 register, and select the transmission/reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit dat a to the sobn pin in synchronization with the serial clock, and capture the receiv e data of the sibn pin. (6) when transmission/reception of the transfer data length set with the cbnctl2 register is completed, stop the serial clock input, transmit data output, and data capturing, generate the reception completion interrupt request signal (intcbnr) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) read the cbnrx register. (8) to continue transmission/reception, write the trans mit data to the cbntx regist er again, and wait for a serial clock input. (9) read the cbnrx register. (10) to end transmission/reception, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bit = 0. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 508 of 870 sep 30, 2010 16.6.7 continuous transfer mode (master mode, transmission mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bi ts = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4), (8) (5) (11) no (7) transmission completed? end yes cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register c3h write cbntx register start transmission cbnctl0 00h no (6), (9) intcbnt interrupt generated? yes no (10) yes cbntsf bit = 0? (cbnstr register) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 509 of 870 sep 30, 2010 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (11) (10) sobn pin intcbnt signal intcbnr signal l bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c3h to the cbnctl0 register, and select the transmission mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is se t to 1 by writing the transmit data to the cbntx register, and transmission is started. (5) when transmission is started, output the serial clock to the sc kbn pin, and output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transfer of the transmit data from the cbnt x register to the shift register is completed and writing to the cbntx register is enabled, the transmission enable inte rrupt request signal (intcbnt) is generated. (7) to continue transmission, write the transmit data to the cbntx register again after the intcbnt signal is generated. (8) when a new transmit data is written to the cbntx register before communicat ion completion, the next communication is started following communication completion. (9) the transfer of the transmit data from the cbntx register to the shift register is completed and the intcbnt signal is generated. to end continuous transmission with the current transmission, do not write to the cbntx register. (10) when the next transmit data is not written to t he cbntx register before tr ansfer completion, stop the serial clock output to the sckbn pin after transf er completion, and clear the cbntsf bit to 0. (11) to release the transmission enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbntxe bit = 0 after che cking that the cbntsf bit = 0. caution in continuous transm ission mode, the reception completi on interrupt request signal (intcbnr) is not generated. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 510 of 870 sep 30, 2010 16.6.8 continuous transfer mode (master mode, reception mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bi ts = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000)
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 511 of 870 sep 30, 2010 (1) operation flow start no intcbnr interrupt generated? cbnove bit = 1? (cbnstr) end yes no yes cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnove bit = 0 (cbnstr) read cbnrx register is data being received last data? yes cbnsce bit = 0 (cbnctl0) read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register a3h start reception (1), (2), (3) (4) (5) (6) (8) (9) (12) (13) (13) no read cbnrx register (9) (7) read cbnrx register no yes cbnctl0 register 00h no yes cbntsf bit = 0? (cbnstr) (9) (10) (11) (8) intcbnr interrupt generated? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in ( 2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 512 of 870 sep 30, 2010 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (4) (3) (5) (6) (7) (8) (9) (11) (13) (10) sibn pin intcbnr signal cbnsce bit sobn pin l sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a3h to the cbnctl0 register, and select t he reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by per forming a dummy read of the cbnrx register, and reception is started. (5) when reception is started, output the serial clock to the sckbn pin, and capture the receive data of the sibn pin in synchronization with the serial clock. (6) when reception is completed, the reception co mpletion interrupt request signal (intcbnr) is generated, and reading of the cbnrx register is enabled. (7) when the cbnctl0.cbnsce bit = 1 upon communication completion, the next communication is started following communication completion. (8) to end continuous reception with the curr ent reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) when reception is completed, the intcbnr signa l is generated, and reading of the cbnrx register is enabled. when the cbnsce bit = 0 is set before communication completion, stop the serial clock output to the sckbn pin, and clear the cbntsf bit to 0, to end the receive operation. (11) read the cbnrx register. (12) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (13) to release the reception enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0 after che cking that the cbntsf bit = 0. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 513 of 870 sep 30, 2010 16.6.9 continuous transfer mode (mast er mode, transmissi on/reception mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /2 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bi ts = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000)
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 514 of 870 sep 30, 2010 (1) operation flow start end yes no is receive data last data? yes (12) no write cbntx register cbnove bit = 0 (cbnstr) read cbnrx register read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register e3h no (9) yes (1), (2), (3) (4) (5) (7) (11) (7) (6), (11) (8) (13) (13) (14) (15) (15) (10) no yes intcbnt interrupt generated? no yes cbntsf bit = 0? (cbnstr) write cbntx register yes no is data being transmitted last data? start transmission/reception cbnctl0 register 00h cbnove bit = 1? (cbnstr) intcbnr interrupt generated? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 515 of 870 sep 30, 2010 (2) operation timing (1/2) sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (15) (12) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sobn pin intcbnt signal intcbnr signal sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e3h to the cbnctl0 register, and select the transmission/reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is se t to 1 by writing the transmit data to the cbntx register, and transmission/reception is started. (5) when transmission/reception is st arted, output the serial clock to the sckbn pin, output the transmit data to the sobn pin in synchronization with the seri al clock, and capture the receive data of the sibn pin. (6) when transfer of the transmit data from the cbntx register to the shift register is completed and writing to the cbntx register is enabled, the transmission enable inte rrupt request signal (intcbnt) is generated. (7) to continue transmission/reception, write the tr ansmit data to the cbntx register again after the intcbnt signal is generated. (8) when one transmission/reception is completed, the reception completion interrupt request signal (intcbnr) is generated, and reading of the cbnrx register is enabled. (9) when a new transmit data is written to the cbntx register before communicat ion completion, the next communication is started following communication completion. (10) read the cbnrx register. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 516 of 870 sep 30, 2010 (2/2) (11) the transfer of the transmit data from the cbntx register to the shift register is completed and the intcbnt signal is generated. to end cont inuous transmission/reception with the current transmission/reception, do not wr ite to the cbntx register. (12) when the next transmit data is not written to t he cbntx register before tr ansfer completion, stop the serial clock output to the sckbn pin after transf er completion, and clear the cbntsf bit to 0. (13) when the reception error interrupt request si gnal (intcbnr) is generated, read the cbnrx register. (14) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (15) to release the transmission/reception enable status, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bi t = 0 after checking that the cbntsf bit = 0. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 517 of 870 sep 30, 2010 16.6.10 continuous transfer mode (slave mode, transmission mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (4) (5), (8) (11) no (7) transmission completed? end yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register c3h write cbntx register start transmission cbnctl0 00h no (10) yes cbntsf bit = 0? (cbnstr register) no (6), (9) intcbnt interrupt generated? yes no (9) yes sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 518 of 870 sep 30, 2010 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (11) (10) sobn pin intcbnt signal bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c3h to the cbnctl0 register, and select the transmission mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit data from the sobn pin in synchronization with the serial clock. (6) when transfer of the transmit data from the cbnt x register to the shift register is completed and writing to the cbntx register is enabled, the transmission enable inte rrupt request signal (intcbnt) is generated. (7) to continue transmission, write the transmit data to the cbntx register again after the intcbnt signal is generated. (8) when a serial clock is input following completion of the transmission of the transfer data length set with the cbnctl2 register, continu ous transmission is started. (9) when transfer of the transmit data from the cbnt x register to the shift register is completed and writing to the cbntx register is enabled, the in tcbnt signal is generated. to end continuous transmission with the current transmission, do not write to the cbntx register. (10) when the clock of the transfer dat a length set with the cbnctl2 register is input without writing to the cbntx register, clear the cbntsf bit to 0 to end transmission. (11) to release the transmission enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbntxe bit = 0 after che cking that the cbntsf bit = 0. caution in continuous transmis sion mode, the reception completi on interrupt request signal (intcbnr) is not generated. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 519 of 870 sep 30, 2010 16.6.11 continuous transfer m ode (slave mode, reception mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000)
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 520 of 870 sep 30, 2010 (1) operation flow start no intcbnr interrupt generated? cbnove bit = 1? (cbnstr) end no yes yes cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnove bit = 0 (cbnstr) read cbnrx register is data being received last data? yes cbnsce bit = 0 (cbnctl0) read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register a3h reception start (1), (2), (3) (4) (5) (4) (6) (8) (9) (12) (13) (13) no read cbnrx register (9) (7) read cbnrx register no yes cbnctl0 register 00h intcbnr interrupt generated? (9) (10) (11) (8) no yes cbntsf bit = 0? (cbnstr) no yes sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 521 of 870 sep 30, 2010 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckbn pin cbntsf bit (1) (2) (4) (3) (5) (6) (7) (8) (9) (11) (13) (10) sibn pin intcbnr signal cbnsce bit sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a3h to the cbnctl0 register, and select t he reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by perf orming a dummy read of the cbnrx register, and the device waits for a serial clock input. (5) when a serial clock is input, capture the receive dat a of the sibn pin in synchronization with the serial clock. (6) when reception is completed, the reception co mpletion interrupt request signal (intcbnr) is generated, and reading of the cbnrx register is enabled. (7) when a serial clock is input in the cbnctl0.cbns ce bit = 1 status, continuous reception is started. (8) to end continuous reception with the curr ent reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) when reception is completed, the intcbnr signa l is generated, and reading of the cbnrx register is enabled. when the cbnsce bit = 0 is set before communication completion, clear the cbntsf bit to 0 to end the receive operation. (11) read the cbnrx register. (12) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (13) to release the reception enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0 after che cking that the cbntsf bit = 0. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 522 of 870 sep 30, 2010 16.6.12 continuous transfer mode (s lave mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0) , communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckbn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000)
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 523 of 870 sep 30, 2010 (1) operation flow start end yes no is receive data last data? yes no write cbntx register cbnove bit = 0 (cbnstr) read cbnrx register read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register e3h no yes (1), (2), (3) (4) (5) (7) (11) (9) (7) (8) (13) (12) (13) (14) (15) (15) (10) no yes cbntsf bit = 0? (cbnstr) write cbntx register yes no is data being transmitted last data? start transmission/reception cbnctl0 register 00h cbnove bit = 1? (cbnstr) intcbnr interrupt generated? (6), (11) no yes intcbnt interrupt generated? (4) no yes sckbn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 524 of 870 sep 30, 2010 (2) operation timing (1/2) sckbn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (15) (12) sibn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sobn pin intcbnt signal intcbnr signal sibn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = external clock (sckbn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e3h to the cbnctl0 register, and select t he transmission/reception mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing t he transmit data to the cbntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit dat a to the sobn pin in synchronization with the serial clock, and capture the receiv e data of the sibn pin. (6) when transfer of the transmit data fr om the cbntx register to the shift re gister is completed and writing to the cbntx register is enabled, the transmission enabl e interrupt request signal (intcbnt) is generated. (7) to continue transmission, write the transmit data to the cbntx register again after the intcbnt signal is generated. (8) when reception of the transfer data length set with the cbnctl2 register is completed, the reception completion interrupt request signal (intcbnr) is gener ated, and reading of the cbnr x register is enabled. (9) when a serial clock is input continuously, continuous transmission/re ception is started. (10) read the cbnrx register. (11) when transfer of the transmit data fr om the cbntx register to the shift re gister is completed and writing to the cbntx register is enabled, the intcbnt signal is generated. to end continuous transmission/reception with the current transmission/re ception, do not write to the cbntx register. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 525 of 870 sep 30, 2010 (2/2) (12) when the clock of the transfer data length set with the cbnctl2 regist er is input without writing to the cbntx register, the intcbnr signal is gener ated. clear the cbntsf bit to 0 to end transmission/reception. (13) when the intcbnr signal is generated, read the cbnrx register. (14) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (15) to release the transmission/reception enable status, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bi t = 0 after checking that the cbntsf bit = 0. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 526 of 870 sep 30, 2010 16.6.13 reception error when transfer is performed with reception enabled (cbnct l0.cbnrxe bit = 1) in the continuous transfer mode, the reception completion interrupt request signal (intcbnr) is gen erated again when the next receive operation is completed before the cbnrx register is read after the intcbnr signal is generated, and the overrun error flag (cbnstr.cbnove) is set to 1. even if an overrun error has occurred, the previous receive dat a is lost since the cbnrx regi ster is updated. even if a reception error has occurred, the intcbnr signal is genera ted again upon the next reception completion if the cbnrx register is not read. to avoid an overrun error, complete reading the cbnrx regi ster until one half clock before sampling the last bit of the next receive data from the intcbnr signal generation. (1) operation timing sckbn pin cbnrx register read signal (1) (2) (4) 01h 02h 05h 0ah 15h 2ah 55h aah 00h 01h 02h 05h 0ah 15h 2ah 55h shift register aah 55h cbnrx register sibn pin intcbnr signal cbnove bit sibn pin capture timing (3) (1) start continuous transfer. (2) completion of the first transfer (3) the cbnrx register cannot be read until one hal f clock before the completion of the second transfer. (4) an overrun error occurs, and the reception completion interrupt request signal (intcbnr) is generated, and then the overrun error flag (cbnst r.cbnove) is set to 1. the receive data is overwritten. remark n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 527 of 870 sep 30, 2010 16.6.14 clock timing (1/2) (i) communication type 1 ( cbnckp and cbndap bits = 00) d6 d5 d4 d3 d2 d1 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit d0 d7 (ii) communication type 3 (cbnckp and cbndap bits = 10) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit notes 1. the intcbnt interrupt is set when the data written to the cbntx register is transferred to the data shift register in the continuous transmission or contin uous transmission/reception mode. in the single transmission or single transmission/reception mode, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request signal is generated upon end of communication. 2. the intcbnr interrupt occurs if reception is corre ctly ended and receive data is ready in the cbnrx register while reception is enabled. in the si ngle mode, the intcbnr interrupt request signal is generated even in the transmission mode, upon end of communication. caution in single transfer mode, writing to the cbntx register with the cbntsf bit set to 1 is ignored. this has no influence on the operation during transfer. for example, if the next data is written to the cbntx register when dma is started by generating the intcbnr signal, the written data is not transferred because the cbntsf bit is set to 1. use the continuous transfer mode, not the si ngle transfer mode, for such applications.
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 528 of 870 sep 30, 2010 (2/2) (iii) communication type 2 (cbnckp and cbndap bits = 01) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit (iv) communication type 4 (cbnckp and cbndap bits = 11) d6 d5 d4 d3 d2 d1 d0 d7 sckbn pin sibn capture reg-r/w sobn pin intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf bit notes 1. the intcbnt interrupt is set when the data written to the cbntx register is transferred to the data shift register in the continuous transmission or contin uous transmission/reception modes. in the single transmission or single transmission/reception modes, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request signal is generated upon end of communication. 2. the intcbnr interrupt occurs if reception is corre ctly ended and receive data is ready in the cbnrx register while reception is enabled. in the si ngle mode, the intcbnr interrupt request signal is generated even in the transmission mode, upon end of communication. caution in single transfer mode, writing to the cb ntx register with the cbntsf bit set to 1 is ignored. this has no influence on the operation during transfer. for example, if the next data is written to the cbntx register when dma is started by generating the intcbnr signal, the written data is not transferred because the cbntsf bit is set to 1. use the continuous transfer mode, not the si ngle transfer mode, for such applications.
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 529 of 870 sep 30, 2010 16.7 output pins (1) sckbn pin when csibn operation is disabled (cbnctl0.cbnpwr bit = 0), the sckbn pin output status is as follows. cbnckp cbncks2 cbncks1 cbncks0 sckbn pin output 1 1 1 high impedance 0 other than above fixed to high level 1 1 1 high impedance 1 other than above fixed to low level remarks 1. the output level of the sckbn pin changes if any of the cbnctl1.cbnckp and cbncks2 to cbncks0 bits is rewritten. 2. n = 0 to 4 (2) sobn pin when csibn operation is disabled (cbnpwr bit = 0), the sobn pin output status is as follows. cbntxe cbndap cbndir sobn pin output 0 fixed to low level 0 sobn latch value (low level) 0 cbntx0 value (msb) 1 1 1 cbntx0 value (lsb) remarks 1. the sobn pin output chan ges when any one of the cbnctl0.cbntxe, cbnctl0.cbnd ir bits, and cbnctl1.cbndap bit is rewritten. 2. : don?t care 3. n = 0 to 4
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 530 of 870 sep 30, 2010 16.8 baud rate generator the brg1 to brg3 and csib0 to csib4 baud rate generators are connected as shown in the following block diagram. csib0 csib1 csib2 csib3 csib4 brg1 brg2 brg3 f x f x f x f brg1 f brg2 f brg3 (1) prescaler mode registers 1 to 3 (prsm1 to prsm3) the prsm1 to prsm3 registers control generation of the baud rate signal for csib. these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. 0 prsmm (m = 1 to 3) 0 0 bgcem 0 0 bgcsm1 bgcsm0 disabled enabled bgcem 0 1 baud rate output f xx f xx /2 f xx /4 f xx /8 setting value (k) 0 1 2 3 bgcsm1 0 0 1 1 bgcsm0 0 1 0 1 input clock selection (f bgcsm ) after reset: 00h r/w address: prsm1 fffff320h, prsm2 fffff324h, prsm3 fffff328h < > cautions 1. do not rewrite the prsmm register during operation. 2. set the prsmm register befo re setting the bgcem bit to 1. 3. be sure to clear bits 7 to 5, 3, and 2 to ?0?.
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 531 of 870 sep 30, 2010 (2) prescaler compare registers 1 to 3 (prscm1 to prscm3) the prscm1 to prscm3 registers are 8-bit compare registers. these registers can be read or written in 8-bit units. reset sets these registers to 00h. prscmm7 prscmm (m = 1 to 3) prscmm6 prscmm5 prscmm4 prscmm3 prscmm2 prscmm1 prscmm0 after reset: 00h r/w address: prscm1 fffff321h, prscm2 fffff325h, prscm3 fffff329h cautions 1. do not rewrite the pr scmm register during operation. 2. set the prscmm register before setting the prsmm.bgcem bit to 1. 16.8.1 baud rate generation the transmission/reception clock is generated by dividing t he main clock. the baud rate generated from the main clock is obtained by the following equation. f brgm = caution set f brgm to 8 mhz or lower. remark f brgm : brgm count clock f xx : main clock oscillation frequency k: prsmm register setting value = 0 to 3 n: prscmm register setting value = 1 to 256 however, n = 256 only when prscmm register is set to 00h. m = 1 to 3 f xx 2 k+1 n
v850es/jg3 chapter 16 3-wire var iable-length seria l i/o (csib) r01uh0015ej0300 rev.3.00 page 532 of 870 sep 30, 2010 16.9 cautions (1) when transferring transmit data and receive data using dma transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. check that the no overrun error has occurred by reading the cbnstr.cbnove bit after dma transfer has been completed. (2) in regards to registers that are forbidden from being rewritten during operations (cbnctl0.cbnpwr bit is 1), if rewriting has been carried out by mistake during oper ations, set the cbnctl0.cbnpwr bit to 0 once, then initialize csibn. registers to which rewriting during op eration are prohibited are shown below. ? cbnctl0 register: cbntxe, cbnrxe, cbndir, cbntms bits ? cbnctl1 register: cbnckp, cbndap, cbncks2 to cbncks0 bits ? cbnctl2 register: cbncl3 to cbncl0 bits (3) in communication type 2 and 4 (cbnctl1.cbndap bit = 1), the cbnstr.cbntsf bit is cleared half a sckbn clock after occurrence of a reception complete interrupt (intcbnr). in the single transfer mode, writing the next transmit dat a is ignored during communication (cbntsf bit = 1), and the next communication is not star ted. also if reception-only co mmunication (cbnctl0.cbntxe bit = 0, cbnctl0.cbnrxe bit = 1) is set, the next communication is not started even if the receive data is read during communication (cbntsf bit = 1). therefore, when using the single transfer mode with co mmunication type 2 or 4 (cbndap bit = 1), pay particular attention to the following. ? to start the next transmission, confirm that cbntsf bit = 0 and then write the tr ansmit data to the cbntx register. ? to perform the next reception cont inuously when reception-only communication (cbntxe bit = 0, cbnrxe bit = 1) is set, confirm that cbntsf bit = 0 and then read the cbnrx register. or, use the continuous transfer mode inst ead of the single transfer mode. us e of the continuous transfer mode is recommended especially for using dma. remark n = 0 to 4
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 533 of 870 sep 30, 2010 chapter 17 i 2 c bus to use the i 2 c bus function, use the p38/ sda00, p39/scl00, p40/sda01, p41/scl01, p90/sda02, and p91/scl02 pins as the serial transmit/receive data i/o pins (sda00 to sda02) and serial clock i/o pins (scl00 to scl02), respectively, and set them to n-ch open-drain output . 17.1 mode switching of i 2 c bus and other serial interfaces 17.1.1 uarta2 and i 2 c00 mode switching in the v850es/jg3, uarta2 and i 2 c00 are alternate functions of the same pin and therefore cannot be used simultaneously. set i 2 c00 in advance, using the pmc3 and pfc3 registers, before use. caution the transmit/receive operation of uarta2 and i 2 c00 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-1. uarta2 and i 2 c00 mode switch settings pmc3 after reset: 0000h r/w address: fffff446h, fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, fffff467h 0 0 0 0 0 0 pfc39 pfc38 0 0 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 port i/o mode uarta2 mode i 2 c00 mode pmc3n 0 1 1 operation mode pfc3n 0 1 remarks 1. n = 8, 9 2. = don?t care
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 534 of 870 sep 30, 2010 17.1.2 csib0 and i 2 c01 mode switching in the v850es/jg3, csib0 and i 2 c01 are alternate functions of the same pin and therefore cannot be used simultaneously. set i 2 c01 in advance, using the pmc4 and pfc4 registers, before use. caution the transmit/receive operation of csib0 and i 2 c01 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-2. csib0 and i 2 c01 mode switch settings port i/o mode csib0 mode i 2 c01 mode pmc4n 0 1 1 operation mode pfc4n 0 1 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 after reset: 00h r/w address: fffff448h pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 remarks 1. n = 0, 1 2. = don?t care
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 535 of 870 sep 30, 2010 17.1.3 uarta1 and i 2 c02 mode switching in the v850es/jg3, uarta1 and i 2 c02 are alternate functions of the same pin and therefore cannot be used simultaneously. set i 2 c02 in advance, using the pmc9, pfc9 , and pmce9 registers, before use. caution the transmit/receive operation of uarta1 and i 2 c02 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-3. uarta1 and i 2 c02 mode switch settings pmc9 after reset: 0000h r/w address: fffff452h, fffff453h pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 pfc9 after reset: 0000h r/w address: fffff472h, fffff473h pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 0 0 0 0 0 0 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 pfce9 after reset: 0000h r/w address: fffff712h, fffff713h uarta1 mode i 2 c02 mode pmc9n 1 1 operation mode pfce9n 1 1 pfc9n 0 1 remark n = 0, 1
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 536 of 870 sep 30, 2010 17.2 features i 2 c00 to i 2 c02 have the following two modes. ? operation stopped mode ? i 2 c (inter ic) bus mode (multimasters supported) (1) operation stopped mode in this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) i 2 c bus mode (multimaster support) this mode is used for 8-bit data transfers with several devic es via two lines: a serial clock pin (scl0n) and a serial data bus pin (sda0n). this mode complies with the i 2 c bus format and the master device can generate ?start condition?, ?address?, ?transfer direction specification?, ?dat a?, and ?stop condition? data to the slav e device via the serial data bus. the slave device automatically det ects the received statuses and data by hardware. this function can simplify the part of an application program that controls the i 2 c bus. since scl0n and sda0n pins are us ed for n-ch open-drain outputs, i 2 c0n requires pull-up resistors for the serial clock line and the serial data bus line. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 537 of 870 sep 30, 2010 17.3 configuration the block diagram of the i 2 c0n is shown below. figure 17-4. block diagram of i 2 c0n internal bus iic status register n (iicsn) iic control register n (iiccn) so latch iicen dq cln1, cln0 trcn dfcn dfcn sda0n scl0n output control intiicn iic shift register n (iicn) iiccn.sttn, sptn iicsn.mstsn, excn, coin iicsn.mstsn, excn, coin lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn internal bus cldn dadn smcn dfcn cln1 cln0 clxn iic clock select register n (iiccln) stcfn iicbsyn stcenn iicrsvn iic flag register n (iicfn) iic function expansion register n (iicxn) fxx iic division clock select register m (ocksm) fxx to fxx/5 ocksthm ocksenm ocksm1 ocksm0 clear slave address register n (svan) match signal set noise eliminator iic shift register n (iicn) data retention time correction circuit n-ch open-drain output ack detector ack generator start condition detector stop condition detector serial clock counter serial clock controller noise eliminator n-ch open-drain output start condition generator stop condition generator wakeup controller interrupt request signal generator serial clock wait controller bus status detector prescaler prescaler remark n = 0 to 2 m = 0, 1
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 538 of 870 sep 30, 2010 a serial bus configuration example is shown below. figure 17-5. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 539 of 870 sep 30, 2010 i 2 c0n includes the following hardware (n = 0 to 2). table 17-1. configuration of i 2 c0n item configuration registers iic shift register n (iicn) slave address register n (svan) control registers iic control register n (iiccn) iic status register n (iicsn) iic flag register n (iicfn) iic clock select register n (iiccln) iic function expansion register n (iicxn) iic division clock select registers 0, 1 (ocks0, ocks1) (1) iic shift register n (iicn) the iicn register converts 8-bit serial data into 8- bit parallel data and vice versa, and can be used for both transmission and reception (n = 0 to 2). write and read operations to the iicn r egister are used to control the act ual transmit and receive operations. this register can be read or written in 8-bit units. reset sets this register to 00h. (2) slave address register n (svan) the svan register sets local addresses when in slave mode (n = 0 to 2). this register can be read or written in 8-bit units. reset sets this register to 00h. (3) so latch the so latch is used to retain the output level of the sda0n pin (n = 0 to 2). (4) wakeup controller this circuit generates an interrupt reques t signal (intiicn) when the address rece ived by this register matches the address value set to the svan register or when an extension code is received (n = 0 to 2). (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks t hat are input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 540 of 870 sep 30, 2010 (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiicn). an i 2 c interrupt is generated followi ng either of two triggers. ? falling edge of eighth or ninth clock of the serial clock (set by iiccn.wtimn bit) ? interrupt occurrence due to stop conditi on detection (set by iiccn.spien bit) remark n = 0 to 2 (8) serial clock controller in master mode, this circuit generates the clock output via the scl0n pin from the sampling clock (n = 0 to 2). (9) serial clock wait controller this circuit controls the wait timing. (10) ack generator, stop condition detector, start condition detector, and ack detector these circuits are used to gener ate and detect various statuses. (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the scl0n pin. (12) start condition generator a start condition is generated when the iiccn.sttn bit is set. however, in the communication reservat ion disabled status (iicfn.iicrsvn bi t = 1), this request is ignored and the iicfn.stcfn bit is set to 1 if the bus is not released (iicfn.iicbsyn bit = 1). (13) stop condition generator a stop condition is generated when the iiccn.sptn bit is set. (14) bus status detector whether the bus is released or not is ascertai ned by detecting a start c ondition and stop condition. however, the bus status c annot be detected immediately a fter operation, so set the bus status detector to the initial status by using the iicfn.stcenn bit.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 541 of 870 sep 30, 2010 17.4 registers i 2 c00 to i 2 c02 are controlled by t he following registers. ? iic control registers 0 to 2 (iicc0 to iicc2) ? iic status registers 0 to 2 (iics0 to iics2) ? iic flag registers 0 to 2 (iicf0 to iicf2) ? iic clock select registers 0 to 2 (iiccl0 to iiccl2) ? iic function expansion registers 0 to 2 (iicx0 to iicx2) ? iic division clock select r egisters 0, 1 (ocks0, ocks1) the following registers are also used. ? iic shift registers 0 to 2 (iic0 to iic2) ? slave address registers 0 to 2 (sva0 to sva2) remark for the alternate-function pin settings, see table 4-15 using port pin as alternate-function pin . (1) iic control registers 0 to 2 (iicc0 to iicc2) the iiccn register enables/stops i 2 c0n operations, sets the wait timing, and sets other i 2 c operations (n = 0 to 2). this register can be read or written in 8-bit or 1-bit units. however, set the spien, wtimn, and acken bits when the iicen bit is 0 or during the wait per iod. when setting the iicen bit from ?0? to ?1?, these bits can also be set at the same time. reset sets this register to 00h.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 542 of 870 sep 30, 2010 (1/4) after reset: 00h r/w address: iicc0 fffffd82h, iicc1 fffffd92h, iicc2 fffffda2h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn (n = 0 to 2) iicen specification of i 2 cn operation enable/disable 0 operation stopped. iicsn register reset note 1 . internal operation stopped. 1 operation enabled. be sure to set this bit to 1 when the scl0n and sda0n lines are high level. condition for clearing (iicen bit = 0) condition for setting (iicen bit = 1) ? cleared by instruction ? after reset ? set by instruction lreln note 2 exit from communications 0 normal operation 1 this exits from the current communication oper ation and sets standby mode. this setting is automatically cleared after being ex ecuted. its uses include cases in which a locally irrelevant extension code has been received. the scl0n and sda0n lines are set to high impedance. the sttn and sptn bits and the mstsn, excn, coin , trcn, ackdn, and stdn bits of the iicsn register are cleared. the standby mode following exit from communications rema ins in effect until the following communication entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match occurs or an extension code is received after the start condition. condition for clearing (lreln bit = 0) condition for setting (lreln bit = 1) ? automatically cleared after execution ? after reset ? set by instruction wreln note 2 wait state cancellation control 0 wait state not canceled 1 wait state canceled. this setting is automat ically cleared after wait state is canceled. condition for clearing (wreln bit = 0) condition for setting (wreln bit = 1) ? automatically cleared after execution ? after reset ? set by instruction notes 1. the iicsn register, iicfn.stcfn and iicfn.iicbsyn bits, and iiccln.cldn and iiccln.dadn bits are reset. 2. this flag?s signal is invalid when the iicen bit = 0. caution if the i 2 cn operation is enabled (iicen bit = 1) when the scl0n line is high level and the sda0n line is low level, the start condition is detected immediately. to avoid this, after enabling the i 2 cn operation, immediately set the lr eln bit to 1 with a bit manipulation instruction. remark the lreln and wreln bits are 0 when read after the data has been set.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 543 of 870 sep 30, 2010 (2/4) spien note enable/disable generation of interrupt request when stop condition is detected 0 disabled 1 enabled condition for clearing (spien bit = 0) condition for setting (spien bit = 1) ? cleared by instruction ? after reset ? set by instruction wtimn note control of wait state and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and the wait state is set. slave mode: after input of eight clocks, the clock is set to low level and the wait state is set for the master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and the wait state is set. slave mode: after input of nine clocks, the clock is set to low level and the wait state is set for the master device. during address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. this bit setting becomes valid when the address transfer is complet ed. in master mode, a wait state is inserted at the falling edge of the ninth clock during address transfer. for a slave device that has rece ived a local address, a wait state is inserted at the falling edge of the ninth clock a fter ack is generated. when t he slave device has received an extension code, however, a wait state is inserted at the falling edge of the eighth clock. condition for clearing (wtimn bit = 0) condition for setting (wtimn bit = 1) ? cleared by instruction ? after reset ? set by instruction acken note acknowledgment control 0 acknowledgment disabled. 1 acknowledgment enabled. during t he ninth clock period, the sda0n line is set to low level. the acken bit setting is invalid for address reception by the slave device. in this case, ack is generated when the addresses match. however, the acken bit setting is valid for reception of the extension code. set the acken bit in the system that receives the extension code. condition for clearing (acken bit = 0) condition for setting (acken bit = 1) ? cleared by instruction ? after reset ? set by instruction note this flag?s signal is invalid when the iicen bit = 0. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 544 of 870 sep 30, 2010 (3/4) sttn start condition trigger 0 start condition is not generated. 1 when bus is released (in stop mode): a start condition is generated (for st arting as master). the sda0n line is changed from high level to low level while the scl0n line is high level and then the start condition is generated. next, after the rated amount of time has elapsed, the scl0n line is changed to low level. during communication with a third party: if the communication reservation functi on is enabled (iicfn.iicrsvn bit = 0) ? this trigger functions as a star t condition reserve flag. when set to 1, it releases the bus and then automatically generates a start condition. if the communication reservation f unction is disabled (iicrsvn = 1) ? the iicfn.stcfn bit is set to 1 to clear the info rmation set (1) to the sttn bit. this trigger does not generate a start condition. in the wait state (when master device): a restart condition is generated afte r the wait state is released. cautions concerning set timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acken bit has been set to 0 and the slave has been notified of final reception. for master transmission: a start condition cannot be generat ed normally during the ack period. set to 1 during the wait period that follows output of the ninth clock. for slave: even when the communication reservati on function is disabled (iicrsvn bit = 1), the communication reservation status is entered. ? setting to 1 at the same time as the sptn bit is prohibited. ? when the sttn bit is set to 1, setting the sttn bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (sttn bit = 0) condition for setting (sttn bit = 1) ? when the sttn bit is set to 1 in the communication reservation disabled status ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when the lreln bit = 1 (communication save) ? when the iicen bit = 0 (operation stop) ? after reset ? set by instruction remarks 1. the sttn bit is 0 if it is read immediately after data setting. 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 545 of 870 sep 30, 2010 (4/4) sptn stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda0n line goes to low level, either set the scl0n line to high level or wait until the scl0n pin goes to high level. next, after the rated am ount of time has elapsed, the sda0n line is changed from low level to high level and a stop condition is generated. cautions concerning set timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acken bit has been set to 0 and during the wait period after the slave has been notified of final reception. for master transmission: a stop condition cannot be generat ed normally during the ack reception period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the sttn bit. ? the sptn bit can be set to 1 only when in master mode note . ? when the wtimn bit has been set to 0, if the sptn bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. the wtimn bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the sptn bit should be set to 1 during the wait peri od that follows output of the ninth clock. ? when the sptn bit is set to 1, setting the sptn bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (sptn bit = 0) condition for setting (sptn bit = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when the lreln bit = 1 (communication save) ? when the iicen bit = 0 (operation stop) ? after reset ? set by instruction note set the sptn bit to 1 only in master mode. however, when the iicrsvn bit is 0, the sptn bit must be set to 1 and a stop condition generated befor e the first stop condition is detec ted following the switch to the operation enabled status. for details, see 17.15 cautions . caution when the trcn bit = 1, the wreln bit is set to 1 during the ninth clock and the wait state is canceled, after which the t rcn bit is cleared to 0 and the sda0n line is set to high impedance. remarks 1. the sptn bit is 0 if it is r ead immediately after data setting. 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 546 of 870 sep 30, 2010 (2) iic status registers 0 to 2 (iics0 to iics2) the iicsn register indica tes the status of the i 2 c0n (n = 0 to 2). this register is read-only, in 8-bit or 1-bit units. ho wever, the iicsn register c an only be read when the iiccn.sttn bit is 1 or during the wait period. reset sets this register to 00h. caution accessing the iicsn register is prohibited in the following stat uses. for details, see 3.4.8 (2) accessing specific on-chip pe ripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock (1/3) after reset: 00h r address: iics0 fffffd86h, iics1 fffffd96h, iics2 fffffda6h <7> <6> <5> <4> <3> <2> <1> <0> iicsn mstsn aldn excn coin trcn ackdn stdn spdn (n = 0 to 2) mstsn master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (mstsn bit = 0) condition for setting (mstsn bit = 1) ? when a stop condition is detected ? when the aldn bit = 1 (arbitration loss) ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a start condition is generated aldn arbitration loss detection 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. the mstsn bit is cleared to 0. condition for clearing (aldn bit = 0) condition for setting (aldn bit = 1) ? automatically cleared after the iicsn register is read note ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the arbitration result is a ?loss?. excn detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (excn bit = 0) condition for setting (excn bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the higher four bits of the received address data are either ?0000? or ?1111? (set at the rising edge of the eighth clock). note the aldn bit is also cleared when a bit manipulat ion instruction is execut ed for another bit in the iicsn register.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 547 of 870 sep 30, 2010 (2/3) coin matching address detection 0 addresses do not match. 1 addresses match. condition for clearing (coin bit = 0) condition for setting (coin bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the received address matches the local address (svan register) (set at the rising edge of the eighth clock). trcn transmit/receive status detection 0 receive status (other than transmit status ). the sda0n line is set to high impedance. 1 transmit status. the value in t he so latch is enabled for output to the sda0n line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trcn bit = 0) condition for setting (trcn bit = 1) ? when a stop condition is detected ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? cleared by iiccn.wreln bit = 1 note ? when the aldn bit changes from 0 to 1 (arbitration loss) ? after reset master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated ? when ?0? is output to the first byte?s lsb (transfer direction specification bit) slave ? when ?1? is input by the first byte?s lsb (transfer direction specification bit) ackdn ack detection 0 ack was not detected. 1 ack was detected. condition for clearing (ackdn bit = 0) condition for setting (ackdn bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? after the sda0n bit is set to low level at the rising edge of the scl0n pin?s ninth clock note the trcn bit is cleared to 0 and sda0n line bec omes high impedance when the wreln bit is set to 1 and the wait state is canceled to 0 at the ninth clock by trcn bit = 1. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 548 of 870 sep 30, 2010 (3/3) stdn start condition detection 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (stdn bit = 0) condition for setting (stdn bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a start condition is detected spdn stop condition detection 0 stop condition was not detected. 1 stop condition was detected. the master devic e?s communication is terminated and the bus is released. condition for clearing (spdn bit = 0) condition for setting (spdn bit = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a stop condition is detected remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 549 of 870 sep 30, 2010 (3) iic flag registers 0 to 2 (iicf0 to iicf2) the iicfn register sets the i 2 c0n operation mode and indicates the i 2 c bus status. this register can be read or written in 8-bit or 1-bit units. however, the stcfn and iicbsyn bits are read-only. iicrsvn enables/disables the communi cation reservation function (see 17.14 communication reservation ). the initial value of the iicbsyn bit is set by using the stcenn bit (see 17.15 cautions ). the iicrsvn and stcenn bits can be written only when operation of i 2 c0n is disabled (iiccn.iicen bit = 0). after operation is enabled, iicfn can be read (n = 0 to 2). reset sets this register to 00h.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 550 of 870 sep 30, 2010 after reset: 00h r/w note address: iicf0 fffffd8ah, iicf1 fffffd9ah, iicf2 fffffdaah <7> <6> 5 4 3 2 <1> <0> iicfn stcfn iicbsyn 0 0 0 0 stcenn iicrsvn (n = 0 to 2) stcfn sttn bit clear 0 start condition issued 1 start condition cannot be issued, sttn bit cleared condition for clearing (stcfn bit = 0) condition for setting (stcfn bit = 1) ? cleared by iiccn.sttn bit = 1 ? when the iiccn.iicen bit = 0 ? after reset ? when start condition is not issued and sttn flag is cleared to 0 during communi cation reservation is disabled (iicrsvn bit = 1). iicbsyn i 2 c0n bus status 0 bus released status (default communi cation status when stcenn bit = 1) 1 bus communication status (default comm unication status when stcenn bit = 0) condition for clearing (iicbsyn bit = 0) condition for setting (iicbsyn bit = 1) ? when stop condition is detected ? when the iicen bit = 0 ? after reset ? when start condition is detected ? by setting the iicen bit when the stcenn bit = 0 stcenn initial start enable trigger 0 start conditions cannot be generated until a stop condition is detected following operation enable (iicen bit = 1). 1 start conditions can be generated even if a stop condition is not detected following operation enable (iicen bit = 1). condition for clearing (stcenn bit = 0) condition for setting (stcenn bit = 1) ? when start condition is detected ? after reset ? setting by instruction iicrsvn communication reserv ation function disable bit 0 communication reservation enabled 1 communication reservation disabled condition for clearing (iicrsvn bit = 0) condition for setting (iicrsvn bit = 1) ? clearing by instruction ? after reset ? setting by instruction note bits 6 and 7 are read-only bits. cautions 1. write the stcenn bit only wh en operation is stopped (iicen bit = 0). 2. when the stcenn bit = 1, the bus rel eased status (iicbsyn bit = 0) is recognized regardless of the actual bus st atus immediately after the i 2 cn bus operation is enabled. therefore, to issue the first start conditi on (sttn bit = 1), it is necessary to confirm that the bus has been re leased, so as to not disturb other communications. 3. write the iicrsvn bit only when operation is stopped (iicen bit = 0).
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 551 of 870 sep 30, 2010 (4) iic clock select registers 0 to 2 (iiccl0 to iiccl2) the iiccln register sets the transfer clock for the i 2 c0n. this register can be read or written in 8-bit or 1-bit units. however, the cldn and dadn bits are read-only. set the iiccln register when the iiccn.iicen bit = 0. the smcn, cln1, and cln0 bits are set by the combi nation of the iicxn.clxn bi t and the ocksthm, ocksm1, and ocksm0 bits of the ocksm register (see 17.4 (6) i 2 c0n transfer clock setting method ) (n = 0 to 2, m = 0, 1). reset sets this register to 00h. after reset: 00h r/w note address: iiccl0 fffffd84h, iiccl1 fffffd94h, iiccl2 fffffda4h 7 6 <5> <4> 3 2 1 0 iiccln 0 0 cldn dadn smcn dfcn cln1 cln0 (n = 0 to 2) cldn detection of scl0n pin level (valid only when iiccn.iicen bit = 1) 0 the scl0n pin was detected at low level. 1 the scl0n pin was detected at high level. condition for clearing (cldn bit = 0) condition for setting (cldn bit = 1) ? when the scl0n pin is at low level ? when the iicen bit = 0 (operation stop) ? after reset ? when the scl0n pin is at high level dadn detection of sda0n pin level (valid only when iicen bit = 1) 0 the sda0n pin was detected at low level. 1 the sda0n pin was detected at high level. condition for clearing (dadn bit = 0) condition for setting (dadn bit = 1) ? when the sda0n pin is at low level ? when the iicen bit = 0 (operation stop) ? after reset ? when the sda0n pin is at high level smcn operation mode switching 0 operation in standard mode. 1 operation in high-speed mode. dfcn digital filter operation control 0 digital filter off. 1 digital filter on. the digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of the dfcn bit setting (on/off). the digital filter is used to e liminate noise in high-speed mode. note bits 4 and 5 are read-only bits. caution be sure to clear bits 7 and 6 to ?0?. remark when the iiccn.iicen bit = 0, 0 is r ead when reading the cldn and dadn bits.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 552 of 870 sep 30, 2010 (5) iic function expansion register s 0 to 2 (iicx0 to iicx2) the iicxn register sets i 2 c0n function expansion (valid only in the high-speed mode). this register can be read or written in 8-bit or 1-bit units. setting of the clxn bit is performed in combination with the smcn, cln1, and cln0 bits of the iiccln register and the ocksthm, ocksm1, and ocksm0 bits of the ocksm register (see 17.4 (6) i 2 c0n transfer clock setting method ) (m = 0, 1). set the iicxn register when the iiccn.iicen bit = 0. reset sets this register to 00h. iicxn (n = 0 to 2) after reset: 00h r/w address: iicx0 fffffd85h, iicx1 fffffd95h, iicx2 fffffda5h 0 0 0 0 0 0 0 clxn < > (6) i 2 c0n transfer clock setting method the i 2 c0n transfer clock frequency (f scl ) is calculated using the following expression (n = 0 to 2). f scl = 1/(m t + t r + t f ) m = 12, 18, 24, 36, 44, 48, 54, 60, 66, 72, 86, 88, 96, 132, 172, 176, 198, 220, 258, 344 (see table 17-2 clock settings ). t: 1/f xx t r : scl0n pin rise time t f : scl0n pin fall time for example, the i 2 c0n transfer clock frequency (f scl ) when f xx = 19.2 mhz, m = 198, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(198 52 ns + 200 ns + 50 ns) ? 94.7 khz m t + t r + t f m/2 t t f t r m/2 t scl0n scl0n inversion scl0n inversion scl0n inversion the clock to be selected can be set by the combination of the smcn, cln1, and cln0 bits of the iiccln register, the clxn bit of the iicxn register, and the ocksthm, oc ksm1, and ocksm0 bits of the ocksm register (n = 0 to 2, m = 0, 1).
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 553 of 870 sep 30, 2010 table 17-2. clock settings (1/2) iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 selection clock transfer clock settable main clock frequency (f xx ) range operating mode f xx (when ocks0 = 18h set) f xx /44 2.00 mhz f xx 4.19 mhz f xx /2 (when ocks0 = 10h set) f xx /88 4.00 mhz f xx 8.38 mhz f xx /3 (when ocks0 = 11h set) f xx /132 6.00 mhz f xx 12.57 mhz f xx /4 (when ocks0 = 12h set) f xx /176 8.00 mhz f xx 16.76 mhz 0 0 0 0 f xx /5 (when ocks0 = 13h set) f xx /220 10.00 mhz f xx 20.95 mhz f xx (when ocks0 = 18h set) f xx /86 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks0 = 10h set) f xx /172 8.38 mhz f xx 16.76 mhz f xx /3 (when ocks0 = 11h set) f xx /258 12.57 mhz f xx 25.14 mhz f xx /4 (when ocks0 = 12h set) f xx /344 16.76 mhz f xx 32.00 mhz 0 0 0 1 f xx /5 (when ocks0 = 13h set) f xx /430 20.95 mhz f xx 32.00 mhz 0 0 1 0 f xx note f xx /86 4.19 mhz f xx 8.38 mhz f xx (when ocks0 = 18h set) f xx /66 6.40 mhz f xx /2 (when ocks0 = 10h set) f xx /132 12.80 mhz f xx /3 (when ocks0 = 11h set) f xx /198 19.20 mhz f xx /4 (when ocks0 = 12h set) f xx /264 25.60 mhz 0 0 1 1 f xx /5 (when ocks0 = 13h set) f xx /330 32.00 mhz standard mode (smc0 bit = 0) f xx (when ocks0 = 18h set) f xx /24 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks0 = 10h set) f xx /48 8.00 mhz f xx 16.76 mhz f xx /3 (when ocks0 = 11h set) f xx /72 12.00 mhz f xx 25.14 mhz 0 1 0 f xx /4 (when ocks0 = 12h set) f xx /96 16.00 mhz f xx 32.00 mhz 0 1 1 0 f xx note f xx /24 4.00 mhz f xx 8.38 mhz f xx (when ocks0 = 18h set) f xx /18 6.40 mhz f xx /2 (when ocks0 = 10h set) f xx /36 12.80 mhz f xx /3 (when ocks0 = 11h set) f xx /54 19.20 mhz f xx /4 (when ocks0 = 12h set) f xx /72 25.60 mhz 0 1 1 1 f xx /5 (when ocks0 = 13h set) f xx /90 32.00 mhz f xx (when ocks0 = 18h set) f xx /12 4.00 mhz f xx 4.19 mhz f xx /2 (when ocks0 = 10h set) f xx /24 8.00 mhz f xx 8.38 mhz f xx /3 (when ocks0 = 11h set) f xx /36 12.00 mhz f xx 12.57 mhz f xx /4 (when ocks0 = 12h set) f xx /48 16.00 mhz f xx 16.67 mhz 1 1 0 f xx /5 (when ocks0 = 13h set) f xx /60 20.00 mhz f xx 20.95 mhz 1 1 1 0 f xx note f xx /12 4.00 mhz f xx 4.19 mhz high-speed mode (smc0 bit = 1) other than above setting prohibited ? ? ? note since the selection clock is f xx regardless of the value set to the ocks0 register, clear the ocks0 register to 00h (i 2 c division clock stopped status). remark : don?t care
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 554 of 870 sep 30, 2010 table 17-2. clock settings (2/2) iicxm iicclm bit 0 bit 3 bit 1 bit 0 clxm smcm clm1 clm0 selection clock transfer clock settable main clock frequency (f xx ) range operating mode f xx (when ocks1 = 18h set) f xx /44 2.00 mhz f xx 4.19 mhz f xx /2 (when ocks1 = 10h set) f xx /88 4.00 mhz f xx 8.38 mhz f xx /3 (when ocks1 = 11h set) f xx /132 6.00 mhz f xx 12.57 mhz f xx /4 (when ocks1 = 12h set) f xx /176 8.00 mhz f xx 16.76 mhz 0 0 0 0 f xx /5 (when ocks1 = 13h set) f xx /220 10.00 mhz f xx 20.95 mhz f xx (when ocks1 = 18h set) f xx /86 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks1 = 10h set) f xx /172 8.38 mhz f xx 16.76 mhz f xx /3 (when ocks1 = 11h set) f xx /258 12.57 mhz f xx 25.14 mhz f xx /4 (when ocks1 = 12h set) f xx /344 16.76 mhz f xx 32.00 mhz 0 0 0 1 f xx /5 (when ocks1 = 13h set) f xx /430 20.95 mhz f xx 32.00 mhz 0 0 1 0 f xx note f xx /86 4.19 mhz f xx 8.38 mhz f xx (when ocks1 = 18h set) f xx /66 6.40 mhz f xx /2 (when ocks1 = 10h set) f xx /132 12.80 mhz f xx /3 (when ocks1 = 11h set) f xx /198 19.20 mhz f xx /4 (when ocks1 = 12h set) f xx /264 25.60 mhz 0 0 1 1 f xx /5 (when ocks1 = 13h set) f xx /330 32.00 mhz standard mode (smcm bit = 0) f xx (when ocks1 = 18h set) f xx /24 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks1 = 10h set) f xx /48 8.00 mhz f xx 16.76 mhz f xx /3 (when ocks1 = 11h set) f xx /72 12.00 mhz f xx 25.14 mhz 0 1 0 f xx /4 (when ocks1 = 12h set) f xx /96 16.00 mhz f xx 32.00 mhz 0 1 1 0 f xx note f xx /24 4.00 mhz f xx 8.38 mhz f xx (when ocks1 = 18h set) f xx /18 6.40 mhz f xx /2 (when ocks1 = 10h set) f xx /36 12.80 mhz f xx /3 (when ocks1 = 11h set) f xx /54 19.20 mhz f xx /4 (when ocks1 = 12h set) f xx /72 25.60 mhz 0 1 1 1 f xx /5 (when ocks1 = 13h set) f xx /90 32.00 mhz f xx (when ocks1 = 18h set) f xx /12 4.00 mhz f xx 4.19 mhz f xx /2 (when ocks1 = 10h set) f xx /24 8.00 mhz f xx 8.38 mhz f xx /3 (when ocks1 = 11h set) f xx /36 12.00 mhz f xx 12.57 mhz f xx /4 (when ocks1 = 12h set) f xx /48 16.00 mhz f xx 16.67 mhz 1 1 0 f xx /5 (when ocks1 = 13h set) f xx /60 20.00 mhz f xx 20.95 mhz 1 1 1 0 f xx note f xx /12 4.00 mhz f xx 4.19 mhz high-speed mode (smcm bit = 1) other than above setting prohibited ? ? ? note since the selection clock is f xx regardless of the value set to the ocks1 register, clear the ocks1 register to 00h (i 2 c division clock stopped status). remarks 1. m = 1, 2 2. : don?t care
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 555 of 870 sep 30, 2010 (7) iic division clock select regi sters 0, 1 (ocks0, ocks1) the ocksm register controls the i 2 c0n division clock (n = 0 to 2, m = 0, 1). this register controls the i 2 c00 division clock via the ocks0 register and the i 2 c01 and i 2 c02 division clocks via the ocks1 register. this register can be read or written in 8-bit units. reset sets this register to 00h. 0 ocksm (m = 0, 1) 00 ocksenm ocksthm 0 ocksm1 ocksm0 after reset: 00h r/w address: ocks0 fffff340h, ocks1 fffff344h disable i 2 c division clock operation enable i 2 c division clock operation ocksenm 0 1 operation setting of i 2 c division clock ocksm1 0 0 1 1 0 other than above ocksm0 0 1 0 1 0 selection of i 2 c division clock f xx /2 f xx /3 f xx /4 f xx /5 f xx setting prohibited ocksthm 0 0 0 0 1 (8) iic shift registers 0 to 2 (iic0 to iic2) the iicn register is used for serial transmission/recepti on (shift operations) synchronized with the serial clock. this register can be read or written in 8-bit units, but data should not be wri tten to the iicn register during a data transfer. access (read/write) the iicn register onl y during the wait period. accessing th is register in communication states other than the wait period is prohibited. however, for t he master device, the iicn regi ster can be written once only after the transmission trigger bit (iiccn.sttn bit) has been set to 1. a wait state is released by wr iting the iicn register during the wait period, and data transfe r is started (n = 0 to 2). reset sets this register to 00h. after reset: 00h r/w address: iic0 fffffd80h, iic1 fffffd90h, iic2 fffffda0h 7 6 5 4 3 2 1 0 iicn (n = 0 to 2)
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 556 of 870 sep 30, 2010 (9) slave address registers 0 to 2 (sva0 to sva2) the svan register holds the i 2 c bus?s slave addresses (n = 0 to 2). this register can be read or written in 8- bit units, but bit 0 should be fixed to 0. however, rewriting this register is prohibited when the iicsn.stdn bit = 1 (start condition detection). reset sets this register to 00h. after reset: 00h r/w address: sva0 fffffd83h, sva1 fffffd93h, sva2 fffffda3h 7 6 5 4 3 2 1 0 svan 0 (n = 0 to 2)
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 557 of 870 sep 30, 2010 17.5 i 2 c bus mode functions 17.5.1 pin configuration the serial clock pin (scl0n) and serial data bus pin (sda0n) are configured as follows (n = 0 to 2). scl0n .................th is pin is used for serial clock input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. sda0n ................th is pin is used for serial data input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. since outputs from the serial clock line and the serial dat a bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 17-6. pin configuration diagram v dd scl0n sda0n scl0n sda0n v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 558 of 870 sep 30, 2010 17.6 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ?start condition?, ?address?, ?tr ansfer direction specification? , ?data?, and ?stop condition? generated on the i 2 c bus?s serial data bus is shown below. figure 17-7. i 2 c bus serial data transfer timing 1 to 7 8 9 1 to 8 9 1 to 8 9 scl0n sda0n r/w start condition address ack data data stop condition ack ack the master device generates the start condition, slave address, and stop condition. ack can be generated by either t he master or slave device (normally, it is generated by the device t hat receives 8-bit data). the serial clock (scl0n) is continuously output by the master devic e. however, in the sl ave device, the scl0n pin?s low-level period can be extended and a wait state can be inserted (n = 0 to 2). 17.6.1 start condition a start condition is met when the scl0n pin is high level and t he sda0n pin changes from high level to low level. the start condition for the scl0n and sda0n pins is a signal that t he master device outputs to the slave device when starting a serial transfer. the slave device can defect the start condition (n = 0 to 2). figure 17-8. start condition h scl0n sda0n a start condition is output when the iiccn.sttn bit is set (1) after a stop condition has been detected (iicsn.spdn bit = 1). when a start condition is detected, the iicsn.stdn bit is set (1) (n = 0 to 2). caution when the iiccn.iicen bit of the v850es/jg3 is set to 1 while communications with other devices are in progress, the start condition may be detected de pending on the status of the communication line. be sure to set the iiccn.iicen bit to 1 wh en the scl0n and sda0n lines are high level.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 559 of 870 sep 30, 2010 17.6.2 addresses the 7 bits of data that follow the st art condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. therefore, each slave de vice connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the sv an register. if the address data matches the values of the svan register, the slave device is selected and communicates with the master de vice until the master device generates a start condition or stop condition (n = 0 to 2). figure 17-9. address address scl0n 1 sda0n intiicn note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (int iicn) is generated if a local addre ss or extension code is received during slave device operation. remark n = 0 to 2 the slave address and the eighth bit, which specif ies the transfer direction as described in 17.6.3 transfer direction specification below, are written together to iic shift register n (iicn) and then output. receiv ed addresses are written to the iicn register (n = 0 to 2). the slave address is assigned to the hi gher 7 bits of the iicn register.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 560 of 870 sep 30, 2010 17.6.3 transfer dir ection specification in addition to the 7-bit address data, the master device sends 1 bit that specif ies the transfer direction. when this transfer direction specification bit has a va lue of 0, it indicates that the master device is transmitting data to a slave devi ce. when the transfer direction specification bit has a value of 1, it indica tes that the master device is receiving data from a slave device. figure 17-10. transfer direction specification scl0n 1 sda0n intiicn 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the intiicn signal is generated if a local address or extension code is re ceived during slave device operation. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 561 of 870 sep 30, 2010 17.6.4 ack ack is used to confirm the serial data stat us of the transmitting and receiving devices. the receiving device returns ack for every 8 bits of data it receives. the transmitting device normally receives ack after transmi tting 8 bits of data. when ack is returned from the receiving device, the reception is judged as normal and processing continues. the detection of ack is confirmed with the iicsn.ackdn bit. when the master device is the receiving device, after receiving the final data, it does not return ack and generates the stop condition. when the slave device is the receiving device and does not retu rn ack, the master device generates either a stop condition or a restart c ondition, and then stops the cu rrent transmission. failure to return ack may be caused by the following factors. (a) reception was not performed normally. (b) the final data was received. (c) the receiving device (slave) does not exist for the specified address. when the receiving device sets the sda0n line to low level during the ninth clock, ack is generated (normal reception). when the iiccn.acken bit is set to 1, automatic ack gener ation is enabled. transmission of the eighth bit following the 7 address data bits causes the iicsn.trcn bit to be set. norma lly, set the acken bit to 1 for reception (trcn bit = 0). when the slave device is receiving (when trcn bit = 0), if the slave device cannot rece ive data or does not need to receive any more data, clear the acken bit to 0 to indi cate to the master that no more data can be received. similarly, when the master device is receiving (when t rcn bit = 0) and the subsequent data is not needed, clear the acken bit to 0 to prevent ack from being generated. this not ifies the slave device (transmi tting device) of the end of the data transmission (transmission stopped). figure 17-11. ack scl0n 1 sda0n 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack remark n = 0 to 2 when the local address is received, ack is automatically generated r egardless of the value of the acken bit. no ack is generated if the received address is not a local address (nack). when receiving the extension code, set the acken bit to 1 in advance to generate ack. the ack generation method during data rec eption is based on the wait timing setti ng, as described by the following. ? when 8-clock wait is selected (iiccn.wtimn bit = 0): ack is generated at the falling edge of the scl0n pin?s eighth clock if the acken bit is set to 1 before the wait state cancellation. ? when 9-clock wait is selected (iiccn.wtimn bit = 1): ack is generated if the acken bit is set to 1 in advance. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 562 of 870 sep 30, 2010 17.6.5 stop condition when the scl0n pin is high level, changing the sda0n pin from low level to high level generates a stop condition (n = 0 to 2). a stop condition is generated when serial transfer from the ma ster device to the slave device has been completed. when used as the slave device, t he start condition can be detected. figure 17-12. stop condition h scl0n sda0n remark n = 0 to 2 a stop condition is generated when the iiccn. sptn bit is set to 1. when the stop condition is detect ed, the iicsn.spdn bit is set to 1 and the interrupt request signal (intiicn) is generated when the iiccn.spien bit is set to 1 (n = 0 to 2).
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 563 of 870 sep 30, 2010 17.6.6 wait state a wait state is used to notify the comm unication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0n pin to low level notifies the communication par tner of the wait state. when the wait state has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2). figure 17-13. wait state (1/2) (a) when master device has a nine-clock wa it and slave device has an eight-clock wait (master: transmission, slave: recep tion, and iiccn.acken bit = 1) scl0n 6 sda0n 78 9 123 scl0n iicn 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iicn scl0n acken master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iicn data write (cancel wait state) slave wait after output of eighth clock. ffh is written to iicn register or iiccn.wreln bit is set to 1. transfer lines wait state from slave wait state from master remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 564 of 870 sep 30, 2010 figure 17-13. wait state (2/2) (b) when master and slave d evices both have a nine-clock wait (master: transmission, slave: reception, and acken bit = 1) scl0n 6 sda0n 789 123 scl0n iicn 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iicn scl0n acken master master and slave both wait after output of ninth clock. iicn data write (cancel wait state) slave ffh is written to iicn register or wreln bit is set to 1. generated according to previously set acken bit value transfer lines wait state from master/ slave wait state from slave remark n = 0 to 2 a wait state may be automatically generated depending on the setting of the iiccn.wtimn bit (n = 0 to 2). normally, when the iiccn.wreln bit is set to 1 or when ffh is written to the iicn register on the receiving side, the wait state is canceled and the transmi tting side writes data to the iicn regi ster to cancel the wait state. the master device can also cancel the wait state via either of the following methods. ? by setting the iiccn.sttn bit to 1 ? by setting the iiccn.sptn bit to 1
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 565 of 870 sep 30, 2010 17.6.7 wait state cancellation method in the case of i 2 c0n, wait state can be canceled normally in the following ways (n = 0 to 2). ? by writing data to the iicn register ? by setting the iiccn.wreln bit to 1 (wait state cancellation) ? by setting the iiccn.sttn bit to 1 (start condition generation) ? by setting the iiccn.sptn bit to 1 (stop condition generation) if any of these wait state canc ellation actions is performed, i 2 c0n will cancel wait state and restart communication. when canceling wait state and s ending data (including address), writ e data to the iicn register. to receive data after canceling wait state, or to complete data transmission, set the wreln bit to 1. to generate a restart condition after canceli ng wait state, set the sttn bit to 1. to generate a stop condition after canceling wait state, set the sptn bit to 1. execute cancellation only once for each wait state. for example, if data is written to the iic n register following wait state cancellati on by setting the wreln bit to 1, conflict between the sda0n line change timing and iicn r egister write timing may result in the data output to the sda0n line may be incorrect. even in other operations, if communication is stopped halfway , clearing the iiccn.iicen bit to 0 will stop communication, enabling wait state to be cancelled. if the i 2 c bus dead-locks due to noise, etc., setting the iiccn.lre ln bit to 1 causes the communication operation to be exited, enabling wait st ate to be cancelled.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 566 of 870 sep 30, 2010 17.7 i 2 c interrupt request signals (intiicn) the following shows the value of the iic sn register at the intiicn interrupt request signal generation timing and at the intiicn signal timing (n = 0 to 2). 17.7.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when iiccn.wtimn bit = 0 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b s 3: iicsn register = 1000x000b (wtimn bit = 1) s 4: iicsn register = 1000xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x100b s 3: iicsn register = 1000xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 567 of 870 sep 30, 2010 (2) start ~ address ~ data ~ star t ~ address ~ data ~ stop (restart) <1> when wtimn bit = 0 sttn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 7 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b (wtimn bit = 0) s 4: iicsn register = 1000x110b (wtimn bit = 0) s 5: iicsn register = 1000x000b (wtimn bit = 1) s 6: iicsn register = 1000xx00b 7: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 sttn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b s 3: iicsn register = 1000x110b s 4: iicsn register = 1000xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 568 of 870 sep 30, 2010 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtimn bit = 0 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1010x110b s 2: iicsn register = 1010x000b s 3: iicsn register = 1010x000b (wtimn bit = 1) s 4: iicsn register = 1010xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1010x110b s 2: iicsn register = 1010x100b s 3: iicsn register = 1010xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 569 of 870 sep 30, 2010 17.7.2 slave device operation (when recei ving slave address data (address match)) (1) start ~ address ~ data ~ data ~ stop <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x100b s 3: iicsn register = 0001xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 570 of 870 sep 30, 2010 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 571 of 870 sep 30, 2010 (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtimn bit = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 6 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x110b s 5: iicsn register = 0010xx00b 6: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 572 of 870 sep 30, 2010 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 573 of 870 sep 30, 2010 17.7.3 slave device operation (w hen receiving extension code) (1) start ~ code ~ data ~ data ~ stop <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010x100b s 4: iicsn register = 0010xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 574 of 870 sep 30, 2010 (2) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 6 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 0001x110b s 5: iicsn register = 0001xx00b 6: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 575 of 870 sep 30, 2010 (3) start ~ code ~ data ~ st art ~ code ~ data ~ stop <1> when wtimn bit = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 7 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 0010x010b s 5: iicsn register = 0010x110b s 6: iicsn register = 0010xx00b 7: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 576 of 870 sep 30, 2010 (4) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 00000x10b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 577 of 870 sep 30, 2010 17.7.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 1: iicsn register = 00000001b remarks 1. : generated only when spien bit = 1 2. n = 0 to 2 17.7.5 arbitration loss operation (opera tion as slave after arbitration loss) (1) when arbitration loss occurs duri ng transmission of slave address data <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0101x110b (example: when iicsn .aldn bit is read during interrupt servicing) s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0101x110b (example: when aldn bit is read during in terrupt servicing) s 2: iicsn register = 0001x100b s 3: iicsn register = 0001xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 578 of 870 sep 30, 2010 (2) when arbitration loss occurs dur ing transmission of extension code <1> when wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0110x010b (example: when al dn bit is read during interrupt servicing) s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0110x010b (example: when al dn bit is read during interrupt servicing) s 2: iicsn register = 0010x110b s 3: iicsn register = 0010x100b s 4: iicsn register = 0010xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 579 of 870 sep 30, 2010 17.7.6 operation when arbitrat ion loss occurs (no communicat ion after arbitration loss) (1) when arbitration loss occurs dur ing transmission of slave address data st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 2 s 1: iicsn register = 01000110b (example: when iicsn.a ldn bit is read during interrupt servicing) 2: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 2. n = 0 to 2 (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 2 s 1: iicsn register = 0110x010b (example: when al dn bit is read during interrupt servicing) iiccn.lreln bit is set to 1 by software 2: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 580 of 870 sep 30, 2010 (3) when arbitration loss o ccurs during data transfer <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 10001110b s 2: iicsn register = 01000000b (example: when aldn bit is read during in terrupt servicing) 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 10001110b s 2: iicsn register = 01000100b (example: when aldn bit is read during in terrupt servicing) 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 581 of 870 sep 30, 2010 (4) when arbitration loss occurs due to restart condition duri ng data transfer <1> not extension code (example: address mismatch) st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 01000110b (example: when aldn bit is read during in terrupt servicing) 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0 to 2 <2> extension code st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 0110x010b (example: when al dn bit is read during interrupt servicing) iiccn.lreln bit is set to 1 by software 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 582 of 870 sep 30, 2010 (5) when arbitration loss occurs due to stop condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp s 1 2 s 1: iicsn register = 1000x110b 2: iicsn register = 01000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 583 of 870 sep 30, 2010 (6) when arbitration loss occurs due to low level of sda0n pin when attempting to generate a restart condition <1> when wtimn bit = 0 iiccn.sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b (wtimn bit = 0) s 4: iicsn register = 01000000b (example: when aldn bit is read during in terrupt servicing) 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 iiccn.sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b s 3: iicsn register = 01000100b (example: when aldn bit is read during in terrupt servicing) 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 584 of 870 sep 30, 2010 (7) when arbitration loss occurs due to a stop conditi on when attempting to gene rate a restart condition <1> when wtimn bit = 0 sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b 4: iicsn register = 01000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b 3: iicsn register = 01000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 585 of 870 sep 30, 2010 (8) when arbitration loss occurs due to low level of sda0n pin when attempting to generate a stop condition <1> when wtimn bit = 0 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b (wtimn bit = 0) s 4: iicsn register = 01000000b (example: when aldn bit is read during in terrupt servicing) 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b s 3: iicsn register = 01000000b (example: when aldn bit is read during in terrupt servicing) 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 586 of 870 sep 30, 2010 17.8 interrupt request signal (intiicn) generation timing and wait control the setting of the iiccn.wtimn bit determines the timi ng by which the intiicn r egister is generated and the corresponding wait control, as shown below (n = 0 to 2). table 17-3. intiicn genera tion timing and wait control during slave device operation du ring master device operation wtimn bit address data reception data transmission a ddress data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiicn signal and wait period occu r at the falling edge of the ninth clock only when there is a match with the address set to the svan register. at this point, ack is generated regardless of the val ue set to the iiccn.acken bit. for a slave device that has received an extension code, the intiicn signal occurs at the falling edge of the eighth clock. when the address does not match after restart, the intiicn signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not ma tch the contents of the svan regi ster and an extension code is not received, neither the intiicn signal nor a wait state is generated. remarks 1. the numbers in the table indicate the number of the serial clock?s cl ock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0 to 2 (1) during address transmission/reception ? slave device operation: interrupt and wait ti ming are determined regardless of the wtimn bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtimn bit. (2) during data reception ? master/slave device operation: interrupt and wait timing is determined according to the wtimn bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing is determined according to the wtimn bit.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 587 of 870 sep 30, 2010 (4) wait state cancellation method the four wait state cancella tion methods are as follows. ? by setting the iiccn.wreln bit to 1 ? by writing to the iicn register ? by start condition setting (iiccn.sttn bit = 1) note ? by stop condition setting (iiccn.sptn bit = 1) note note master only when an 8-clock wait has been selected (wtimn bit = 0), whether or not ac k has been generated must be determined prior to wait cancellation. remark n = 0 to 2 (5) stop condition detection the intiicn signal is generated w hen a stop condition is detected. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 588 of 870 sep 30, 2010 17.9 address match detection method in i 2 c bus mode, the master device can se lect a particular slave device by tr ansmitting the corresponding slave address. address match detection is performed autom atically by hardware. the intiicn signal occurs when a local address has been set to the svan register and when the address set to t he svan register matches the slave address sent by the master device, or when an extension code has been received (n = 0 to 2). 17.10 error detection in i 2 c bus mode, the status of t he serial data bus pin (sda0n) during data tr ansmission is captured by the iicn register of the transmitting device, so the data of the iicn register prior to transmission can be co mpared with the transmitted iicn data to enable detection of transmission errors. a transmi ssion error is judged as having occurred when the compared data values do not match (n = 0 to 2). 17.11 extension code (1) when the higher 4 bits of the rece ive address are either 0000 or 1111, the extension code fl ag (iicsn.excn bit) is set for extension code reception and an interrupt request si gnal (intiicn) is issued at the falling edge of the eighth clock (n = 0 to 2). the local address stored in the svan register is not affected. (2) if 11110xx0 is set to the svan register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. no te that the intiicn signal occurs at the falling edge of the eighth clock (n = 0 to 2). ? higher four bits of data match: excn bit = 1 ? seven bits of data match: iicsn.coin bit = 1 (3) since the processing after the interrupt request signal occu rs differs according to the dat a that follows the extension code, such processing is performed by software. for example, when operation as a slave is not desired after the extension code is received, set the iiccn.lreln bit to 1 and the cpu will enter the nex t communication wait state. table 17-4. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 589 of 870 sep 30, 2010 17.12 arbitration when several master devices simultaneous ly generate a start condition (when the ii ccn.sttn bit is set to 1 before the iicsn.stdn bit is set to 1), communication between the mast er devices is performed while the number of clocks is adjusted until the data differs. this kind of oper ation is called arbitration (n = 0 to 2). when one of the master devices loses in ar bitration, an arbitration loss flag (iicsn.a ldn bit) is set to 1 via the timing by which the arbitration loss occurred, and the scl0n and sda0n lines are both set to high impedance, which releases the bus (n = 0 to 2). arbitration loss is detected bas ed on the timing of the next interrupt request si gnal (intiicn) (the eight h or ninth clock, when a stop condition is detected, etc.) and the setting of the aldn bit to 1, which is made by software (n = 0 to 2). for details of interrupt request timing, see 17.7 i 2 c interrupt request signals (intiicn) . figure 17-14. arbitration timing example master 1 master 2 transfer lines scl0n sda0n scl0n sda0n scl0n sda0n master 1 loses arbitration hi-z hi-z remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 590 of 870 sep 30, 2010 table 17-5. status during arbitration a nd interrupt request si gnal generation timing status during arbitration inte rrupt request generation timing transmitting address transmission read/write data after address transmission transmitting extension code read/write data after extension code transmission transmitting data ack transfer period after data reception when restart condition is det ected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected duri ng data transfer when stop condition is generated (when iiccn.spien bit = 1) note 2 when sda0n pin is low level while attempting to generate restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate restart condition when stop condition is generated (when iiccn.spien bit = 1) note 2 when dsa0n pin is low level while attempting to generate stop condition when scl0n pin is low level while attempting to generate restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when the iiccn.wtimn bit = 1, an intiicn signal occu rs at the falling edge of t he ninth clock. when the wtimn bit = 0 and the extension code?s slave address is received, an intiicn signal occurs at the falling edge of the eighth clock (n = 0 to 2). 2. when there is a possibility that arbi tration will occur, set the spien bit to 1 for master device operation (n = 0 to 2). 17.13 wakeup function the i 2 c bus slave function is a function that generates an interrupt request si gnal (intiicn) when a local address and extension code have been received. this function makes processing more efficient by prev enting unnecessary the intiicn signal from occurring when addresses do not match. when a start condition is detected, wa keup standby mode is set. this wak eup standby mode is in effect while addresses are transmitted due to the possi bility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. however, when a stop condition is detect ed, the iiccn.spien bit is set regardl ess of the wakeup function, and this determines whether intiicn signal is enabled or disabled (n = 0 to 2).
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 591 of 870 sep 30, 2010 17.14 communication reservation 17.14.1 when communication reservation functi on is enabled (iicfn.iicrsvn bit = 0) to start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is releas ed. there are two modes in which the bus is not used. ? when arbitration results in neit her master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iiccn.lreln bit was set to 1) (n = 0 to 2). if the iiccn.sttn bit is set to 1 while the bus is not used, a start condition is automatica lly generated and a wait state is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is detected), writing to the iicn register causes master address transfer to start. at this point, the ii ccn.spien bit should be set to 1 (n = 0 to 2). when sttn has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status (n = 0 to 2). if the bus has been re leased .............................................a start condition is generated if the bus has not been released (standby mode)..............comm unication reservation to detect which operation mode has been deter mined for the sttn bit, set the sttn bit to 1, wait for the wait period, then check the iicsn.mstsn bit (n = 0 to 2). the wait periods, which should be set via software, are listed in table 17-6. these wait periods can be set by the smcn, cln1, and cln0 bits of the iiccln register and the iicxn.clxn bit (n = 0 to 2).
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 592 of 870 sep 30, 2010 table 17-6. wait periods clock selection clxn smcn cln1 cln0 wait period f xx (when ocksm = 18h set) 0 0 0 0 26 clocks f xx /2 (when ocksm = 10h set) 0 0 0 0 52 clocks f xx /3 (when ocksm = 11h set) 0 0 0 0 78 clocks f xx /4 (when ocksm = 12h set) 0 0 0 0 104 clocks f xx /5 (when ocksm = 13h set) 0 0 0 0 130 clocks f xx (when ocksm = 18h set) 0 0 0 1 47 clocks f xx /2 (when ocksm = 10h set) 0 0 0 1 94 clocks f xx /3 (when ocksm = 11h set) 0 0 0 1 141 clocks f xx /4 (when ocksm = 12h set) 0 0 0 1 188 clocks f xx /5 (when ocksm = 13h set) 0 0 0 1 235 clocks f xx 0 0 1 0 47 clocks f xx (when ocksm = 18h set) 0 0 1 1 37 clocks f xx /2 (when ocksm = 10h set) 0 0 1 1 74 clocks f xx /3 (when ocksm = 11h set) 0 0 1 1 111 clocks f xx /4 (when ocksm = 12h set) 0 0 1 1 148 clocks f xx /5 (when ocksm = 13h set) 0 0 1 1 185 clocks f xx (when ocksm = 18h set) 0 1 0 16 clocks f xx /2 (when ocksm = 10h set) 0 1 0 32 clocks f xx /3 (when ocksm = 11h set) 0 1 0 48 clocks f xx /4 (when ocksm = 12h set) 0 1 0 64 clocks f xx /5 (when ocksm = 13h set) 0 1 0 80 clocks f xx 0 1 1 0 16 clocks f xx (when ocksm = 18h set) 0 1 1 1 13 clocks f xx /2 (when ocksm = 10h set) 0 1 1 1 26 clocks f xx /3 (when ocksm = 11h set) 0 1 1 1 39 clocks f xx /4 (when ocksm = 12h set) 0 1 1 1 52 clocks f xx /5 (when ocksm = 13h set) 0 1 1 1 65 clocks f xx (when ocksm = 18h set) 1 1 0 10 clocks f xx /2 (when ocksm = 10h set) 1 1 0 20 clocks f xx /3 (when ocksm = 11h set) 1 1 0 30 clocks f xx /4 (when ocksm = 12h set) 1 1 0 40 clocks f xx /5 (when ocksm = 13h set) 1 1 0 50 clocks f xx 1 1 1 0 10 clocks remarks 1. n = 0 to 2 m = 0, 1 2. = don?t care the communication reservation timing is shown below.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 593 of 870 sep 30, 2010 figure 17-15. communication reservation timing 2 1 3456 2 1 3456 789 scl0n sda0n program processing hardware processing write to iicn set spdn and intiicn sttn = 1 communication reservation set stdn generated by master with bus access remark n = 0 to 2 sttn: bit of iiccn register stdn: bit of iicsn register spdn: bit of iicsn register communication reservations are accepted via the following timing. after the iicsn.stdn bit is set to 1, a communication reservation can be made by setting the iiccn.sttn bit to 1 before a stop condition is detected (n = 0 to 2). figure 17-16. timing for accep ting communication reservations scl0n sda0n stdn spdn standby mode remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 594 of 870 sep 30, 2010 the communication reservation flowchart is illustrated below. figure 17-17. communication reservation flowchart di set1 sttn define communication reservation wait cancel communication reservation no yes iicn register xxh ei mstsn bit = 0? (communication reservation) note (generate start condition) sets sttn bit (communication reservation). secures wait period set by software (see table 17-6 ). confirmation of communication reservation clears user flag. iicn register write operation defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation operation execut es a write to the iic n register when a stop condition interrupt request occurs. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 595 of 870 sep 30, 2010 17.14.2 when communication reservation functi on is disabled (iicfn.iicrsvn bit = 1) when the iiccn.sttn bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. there are two modes in which the bus is not used. ? when arbitration results in nei ther master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iiccn.lreln bit was set to 1) (n = 0 to 2). to confirm whether the start condition was generated or request was rejected, chec k the iicfn.stcfn flag. the time shown in table 17-7 is required until the stcf n flag is set after setting the sttn bit to 1. therefore, secure the time by software. table 17-7. wait periods ocksenm ocksm1 ocksm0 cln1 cln0 wait period 1 0 0 0 10 clocks 1 0 1 0 15 clocks 1 1 0 0 20 clocks 1 1 1 0 25 clocks 0 0 0 1 0 5 clocks remarks 1. : don?t care 2. n = 0 to 2 m = 0, 1
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 596 of 870 sep 30, 2010 17.15 cautions (1) when iicfn.stcenn bit = 0 immediately after the i 2 c0n operation is enabled, the bus communica tion status (iicfn.iicbsyn bit = 1) is recognized regardless of the actual bus status. to execute master comm unication in the status where a stop condition has not been detect ed, generate a stop condition and then releas e the bus before st arting the master communication. use the following sequence for generating a stop condition. <1> set the iiccln register. <2> set the iiccn.iicen bit. <3> set the iiccn.sptn bit. (2) when iicfn.stcenn bit = 1 immediately after i 2 c0n operation is enabled, the bus re leased status (iicbsyn bit = 0) is recognized regardless of the actual bus status. to gener ate the first start condition (iiccn.sttn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) when the iiccn.iicen bit of the v 850es/jg3 is set to 1 while communi cations among other devices are in progress, the start condition may be det ected depending on the status of the communication line. be sure to set the iiccn.iicen bit to 1 when the scl0n and sda0n lines are high level. (4) determine the operation clock frequency by the iiccln, iicxn, and ocksm registers before enabling the operation (iiccn.iicen bit = 1). to change the operation clo ck frequency, clear the iiccn.iicen bit to 0 once. (5) after the iiccn.sttn and iiccn.sptn bits have been set to 1, they must not be re-s et without being cleared to 0 first. (6) if transmission has been reserved, set the iiccn.spien bit to 1 so that an interrupt reques t is generated by the detection of a stop condition. after an interrupt request has been generated, the wait state will be released by writing communication data to i 2 cn, then transferring will begin. if an interrupt is not gener ated by the detec tion of a stop condition, transmission will halt in the wait state because an interrupt request was not generated. howe ver, it is not necessary to set the spien bit to 1 for the software to detect the iicsn.mstsn bit. remark n = 0 to 2 m = 0, 1
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 597 of 870 sep 30, 2010 17.16 communication operations the following shows three operati on procedures with the flowchart. (1) master operation in single master system the flowchart when using the v850 es/jg3 as the master in a singl e master system is shown below. this flowchart is broadly divided into the initial settings and communication processing. execute the initial settings at startup. if communication wit h the slave is required, prepare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 c0n bus multimaster system, whether the bus is released or used cannot be judged by the i 2 c bus specifications when the bus takes part in a communicati on. here, when data and clock are at a high level for a certain period (1 frame), the v850es/jg3 takes par t in a communication with bus released state. this flowchart is broadly divided into the initial setti ngs, communication waiting, and communication processing. the processing when the v850es/jg3 lose s in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. execute the initial settings at star tup to take part in a communication. then, wait for the communication request as the master or wait for the specif ication as the slav e. the actual communication is performed in the communication processi ng, and it supports the trans mission/reception with the slave and the arbitrati on with other masters. (3) slave operation an example of when the v850es/jg3 is used as the slave of the i 2 c0n bus is shown below. when used as the slave, operation is started by an interrupt. execute the init ial settings at start up, then wait for the intiicn interrupt occurrence (communication waiting). when the intiicn interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. by checking the flags, necessary communication processing is performed. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 598 of 870 sep 30, 2010 17.16.1 master operation in single master system figure 17-18. master operati on in single master system iicxn 0xh iiccln xxh ocksm xxh iicfn 0xh set stcenn, iicrsvn = 0 iiccn xxh acken = wtimn = spien = 1 iicen = 1 set ports initialize i 2 c bus note sptn = 1 svan xxh write iicn write iicn sptn = 1 wreln = 1 start end read iicn acken = 0 wtimn = wreln = 1 no no yes no no no yes yes yes yes stcenn = 1? acken = 1 wtimn = 0 intiicn interrupt occurred? transfer completed? transfer completed? restarted? trcn = 1? ackdn = 1? ackdn = 1? refer to table 4-15 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting communication start preparation (start condition generation) communication start (address, transfer direction specification) waiting for ack detection waiting for data transmission transmission start communication processing initial settings reception start waiting for data reception no yes intiicn interrupt occurred? waiting for ack detection communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiicn interrupt occurred? yes no intiicn interrupt occurred? yes no yes no yes no intiicn interrupt occurred? sttn = 1 note release the i 2 c0n bus (scl0n, sda0n pins = high level) in c onformity with the specif ications of the product in communication. for example, when the eeprom tm outputs a low level to the sda0n pin, set the scl0n pin to the output port and output clock pulses from that output port until when the sda0n pi n is constantly high level. remarks 1. for the transmission and reception formats, confo rm to the specificati ons of the product in communication. 2. n = 0 to 2, m = 0, 1
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 599 of 870 sep 30, 2010 17.16.2 master operation in multimaster system figure 17-19. master operation in multimaster system (1/3) iicxn 0xh iiccln xxh ocksm xxh iicfn 0xh set stcenn, iicrsvn iiccn xxh acken = wtimn = spien = 1 iicen = 1 set ports sptn = 1 svan xxh spien = 1 start slave operation slave operation bus release status for a certain period confirmation of bus status is in progress yes confirm bus status note master operation started? communication reservation enable communication reservation disable spdn = 1? stcenn = 1? iicrsvn = 0? a refer to table 4-15 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting (communication start request issued) (no communication start request) ? waiting for slave specification from another master ? waiting for communication start request (depending on user program) communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiicn interrupt occurred? intiicn interrupt occurred? yes no yes no spdn = 1? yes no slave operation no intiicn interrupt occurred? yes no 1 b spien = 0 yes no waiting for communication request communication waiting initial settings note confirm that the bus releas e status (iiccln.cldn bit = 1, iiccln. dadn bit = 1) has been maintained for a certain period (1 frame, for example). when the sda 0n pin is constantly low le vel, determine whether to release the i 2 c0n bus (scl0n, sda0n pins = high level) by re ferring to the specificat ions of the product in communication. remark n = 0 to 2, m = 0, 1
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 600 of 870 sep 30, 2010 figure 17-19. master operation in multimaster system (2/3) sttn = 1 wait slave operation yes mstsn = 1? excn = 1 or coin =1? communication start preparation (start condition generation) securing wait time by software (refer to table 17-6 ) waiting for bus release (communication reserved) wait status after stop condition detection and start condition generation by communication reservation function no intiicn interrupt occurred? yes yes no no a c sttn = 1 wait slave operation yes iicbsyn = 0? excn = 1 or coin =1? communication start preparation (start condition generation) communication reservation disabled communication reservation enabled securing wait time by software (refer to table 17-7 ) waiting for bus release stop condition detection no no intiicn interrupt occurred? yes yes no yes stcfn = 0? no b d c d communication processing communication processing remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 601 of 870 sep 30, 2010 figure 17-19. master operation in multimaster system (3/3) write iicn wtimn = 1 wreln = 1 read iicn acken = 1 wtimn = 0 wtimn = wreln = 1 acken = 0 write iicn yes trcn = 1? restarted? mstsn = 1? communication start (address, transfer direction specification) transmission start no yes waiting for data transmission reception start yes no intiicn interrupt occurred? yes no transfer completed? waiting for ack detection yes no intiicn interrupt occurred? waiting for data transmission not in communication yes no intiicn interrupt occurred? no yes ackdn = 1? no yes no c 2 yes mstsn = 1? no yes transfer completed? no yes ackdn = 1? no 2 yes mstsn = 1? no 2 waiting for ack detection yes no intiicn interrupt occurred? yes mstsn = 1? no c 2 yes excn = 1 or coin = 1? no 1 2 sptn = 1 sttn = 1 slave operation end communication processing communication processing remarks 1. conform the transmission and reception formats to t he specifications of the product in communication. 2. when using the v850es/jg3 as t he master in the multimaster syst em, read the iicsn.mstsn bit for each intiicn interrupt occurrence to confirm the arbitration result. 3. when using the v850es/jg3 as t he slave in the multimaster system , confirm the status using the iicsn and iicfn registers for each intiicn interr upt occurrence to determine the next processing. 4. n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 602 of 870 sep 30, 2010 17.16.3 slave operation the following shows the processing procedure of the slave operation. basically, the operation of the slave device is event-driven. therefore, processing by an intiicn interrupt (processing requiring a significant change of the operat ion status, such as stop condition detec tion during communication) is necessary. the following description assumes that data communication does not support extension codes. also, it is assumed that the intiicn interrupt servicing performs only status c hange processing and that the ac tual data communication is performed during the main processing. figure 17-20. software out line during slave operation i 2 c intiicn signal setting, etc. setting, etc. flag data main processing interrupt servicing therefore, the following three flags ar e prepared so that the data transfer pr ocessing can be performed by transmitting these flags to the main processing instead of intiicn signal. (1) communication mode flag this flag indicates the following communication statuses. clear mode: data communication not in progress communication mode: data communication in progress (va lid address detection stop condi tion detection, ack from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. this is the same status as an in tiicn interrupt during normal data transfer. this flag is set in the interrupt processi ng block and cleared in the main processing block. the ready flag for the first data for transmission is not set in the inte rrupt processing block, so t he first data is transmitted without clear processing (the address match is regarded as a request for the next data). (3) communication direction flag this flag indicates the direction of communication and is the same as the value of iicsn.trcn bit. the following shows the operation of the main processing block during slave operation. start i 2 c0n and wait for the communication enabled status. when communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). for transmission, repeat the transmission operation until the master device stops returning ack. when the master device stops returning ack , transfer is complete.
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 603 of 870 sep 30, 2010 for reception, receive the required num ber of data and do not return ack for the next data immediately after transfer is complete. after that, the master devi ce generates the stop condition or restart condition. this causes exit from communications. figure 17-21. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 0? read iicn clear ready flag clear ready flag communication direction flag = 1? wreln = 1 ackdn = 1? clear communication mode flag wreln = 1 write iicn iiccn xxh acken = wtimn = 1 spien = 0, iicen = 1 svan xxh local address setting iicxn 0xh iiccln xxh ocksm xxh set ports transfer clock selection iicfn 0xh set iicrsvn start condition setting transmission start reception start no yes no communication mode flag = 1? yes no ready flag = 1? refer to table 4-15 using port pin as alternate-function pins to set the i 2 c mode before this function is used. start initial settings communication processing remark n = 0 to 2, m = 0, 1
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 604 of 870 sep 30, 2010 the following shows an example of the proc essing of the slave device by an int iicn interrupt (it is assumed that no extension codes are used here). during an intiicn interrupt, t he status is confirmed and the following steps are executed. <1> when a stop condition is detect ed, communication is terminated. <2> when a start condition is detected, the address is confirmed. if the addr ess does not match, communication is terminated. if the address matches, the communication mode is set and wait state is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, w hen the ready flag is set, operation retu rns from the interrupt while the i 2 c0n bus remains in the wait state. remark <1> to <3> in the above correspond to <1> to <3> in figure 17-22 slave operation flowchart (2) . figure 17-22. slave operation flowchart (2) yes yes yes no no no intiicn occurred set ready flag interrupt servicing completed spdn = 1? stdn = 1? coin = 1? clear communication direction flag, ready flag, and communication mode flag <1> <2> <3> communication direction flag trcn set communication mode flag clear ready flag
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 605 of 870 sep 30, 2010 17.17 timing of data communication when using i 2 c bus mode, the master device out puts an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the ma ster device transmits the iicsn.trcn bit, which specifies the data transfer direction, and then starts serial communication with the slave device. the shift operation of the iicn register is synchronized with the falling edge of the serial clock pin (scl0n). the transmit data is transferred to the so latch and is output (msb first) via the sda0n pin. data input via the sda0n pin is captured by the iicn register at the ri sing edge of the scl0n pin. the data communication timing is shown below. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 606 of 870 sep 30, 2010 figure 17-23. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l l h h h l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iicn address iicn data iicn ffh transmit start condition receive (when excn = 1) note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 607 of 870 sep 30, 2010 figure 17-23. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h l l l l l l h h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iicn data iicn ffh note iicn ffh note iicn data transmit receive note note ack ack note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 608 of 870 sep 30, 2010 figure 17-23. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l l h h h l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn data iicn address iicn ffh note iicn ffh note stop condition start condition transmit note note (when spien = 1) receive (when spien = 1) ack note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 609 of 870 sep 30, 2010 figure 17-24. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l h l acken mstsn sttn l l sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iicn address iicn ffh note note iicn data start condition ack note to cancel master wait, writ e ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 610 of 870 sep 30, 2010 figure 17-24. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (2/3) (b) data iicn ackdn stdn spdn wtimn h h h l l l l l l l h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iicn data iicn data iicn ffh note iicn ffh note note to cancel master wait, writ e ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3 chapter 17 i 2 c bus r01uh0015ej0300 rev.3.00 page 611 of 870 sep 30, 2010 figure 17-24. example of sl ave to master communication (when 8-clock 9-clock wait for master and 9-clo ck wait for slave are selected) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 iicn address iicn ffh note note iicn data stop condition start condition (when spien = 1) nack (when spien = 1) note to cancel master wait, writ e ffh to iicn or set wreln. remark n = 0 to 2
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 612 of 870 sep 30, 2010 chapter 18 dma function (dma controller) the v850es/jg3 includes a direct memory access (dma) contro ller (dmac) that executes and controls dma transfer. the dmac controls data transfer between memory and i/o, between memo ries, or between i/os based on dma requests issued by the on-chip peripheral i/o (serial interface, timer/counter, and a/d converter), inte rrupts from external input pins, or software triggers (memory refe rs to internal ram or external memory). 18.1 features ? 4 independent dma channels ? transfer unit: 8/16 bits ? maximum transfer count: 65,536 (2 16 ) ? transfer type: two-cycle transfer ? transfer mode: single transfer mode ? transfer requests ? request by interrupts from on-chip peripheral i/o (serial interface, timer/counter, a/d converter) or interrupts from external input pin ? requests by software trigger ? transfer targets ? internal ram ? peripheral i/o ? peripheral i/o ? peripheral i/o ? internal ram ? external memory ? external memory ? peripheral i/o ? external memory ? external memory
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 613 of 870 sep 30, 2010 18.2 configuration cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850es/jg3 bus interface external bus external ram external rom external i/o dma source address register n (dsanh/dsanl) dma transfer count register n (dbcn) dma channel control register n (dchcn) dma destination address register n (ddanh/ddanl) dma addressing control register n (dadcn) dma trigger factor register n (dtfrn) remark n = 0 to 3
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 614 of 870 sep 30, 2010 18.3 registers (1) dma source address registers 0 to 3 (dsa0 to dsa3) the dsa0 to dsa3 registers set the dma source addresse s (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, dsanh and dsanl. these registers can be read or written in 16-bit units. external memory or on-chip peripheral i/o internal ram ir 0 1 specification of dma transfer source set the address (a25 to a16) of the dma transfer source (default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. sa25 to sa16 set the address (a15 to a0) of the dma transfer source (default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. sa15 to sa0 after reset: undefined r/w address: dsa0h fffff082h, dsa1h fffff08ah, dsa2h fffff092h, dsa3h fffff09ah, dsa0l fffff080h, dsa1l fffff088h, dsa2l fffff090h, dsa3l fffff098h dsanl (n = 0 to 3) sa15 sa14 sa13 sa12 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa7 sa8 sa9 sa10 sa11 dsanh (n = 0 to 3) ir 000 sa22 sa21 sa20 sa19 sa18 sa17 sa16 sa23 sa24 sa25 0 0 cautions 1. be sure to clear bits 14 to 10 of the dsanh register to 0. 2. set the dsanh and dsanl registers at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the dsan register is read, two 16-bit re gisters, dsanh and dsanl, are read. if reading and updating conflict, the value being updated may be read (see 18.13 cautions). 4. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 615 of 870 sep 30, 2010 (2) dma destination address regi sters 0 to 3 (dda0 to dda3) the dda0 to dda3 registers set the dma destination address (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, ddanh and ddanl. these registers can be read or written in 16-bit units. external memory or on-chip peripheral i/o internal ram ir 0 1 specification of dma transfer destination set an address (a25 to a16) of dma transfer destination (default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. da25 to da16 set an address (a15 to a0) of dma transfer destination (default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. da15 to da0 after reset: undefined r/w address: dda0h fffff086h, dda1h fffff08eh, dda2h fffff096h, dda3h fffff09eh, dda0l fffff084h, dda1l fffff08ch, dda2l fffff094h, dda3l fffff09ch ddanl (n = 0 to 3) da15 da14 da13 da12 da6 da5 da4 da3 da2 da1 da0 da7 da8 da9 da10 da11 ddanh (n = 0 to 3) ir 000 da22 da21 da20 da19 da18 da17 da16 da23 da24 da25 0 0 cautions 1. be sure to clear bits 14 to 10 of the ddanh register to 0. 2. set the ddanh and ddanl registers at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the ddan register is read, two 16-bit registers, ddanh and ddanl, are read. if reading and updating conflict, a va lue being updated may be read (see 18.13 cautions). 4. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 616 of 870 sep 30, 2010 (3) dma transfer count regi sters 0 to 3 (dbc0 to dbc3) the dbc0 to dbc3 registers are 16-bit registers that set the byte transfer c ount for dma channel n (n = 0 to 3). these registers hold the remaining tr ansfer count during dma transfer. these registers are decremented by 1 per one transfer regardless of the tr ansfer data unit (8/16 bits), and the transfer is terminated if a borrow occurs. these registers can be read or written in 16-bit units. byte transfer count 1 or remaining byte transfer count byte transfer count 2 or remaining byte transfer count : byte transfer count 65,536 (2 16 ) or remaining byte transfer count bc15 to bc0 0000h 0001h : ffffh byte transfer count setting or remaining byte transfer count during dma transfer after reset: undefined r/w address: dbc0 fffff0c0h, dbc1 fffff0c2h, dbc2 fffff0c4h, dbc3 fffff0c6h dbcn (n = 0 to 3) 15 bc15 14 bc14 13 bc13 12 bc12 11 bc11 10 bc10 9 bc9 8 bc8 7 bc7 6 bc6 5 bc5 4 bc4 3 bc3 2 bc2 1 bc1 0 bc0 the number of transfer data set first is held when dma transfer is complete. cautions 1. set the dbcn register at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 617 of 870 sep 30, 2010 (4) dma addressing control registers 0 to 3 (dadc0 to dadc3) the dadc0 to dadc3 registers are 16-b it registers that control the dma tr ansfer mode for dma channel n (n = 0 to 3). these registers can be read or written in 16-bit units. reset sets these registers to 0000h. dadcn (n = 0 to 3) 8 bits 16 bits ds0 0 1 setting of transfer data size increment decrement fixed setting prohibited sad1 0 0 1 1 sad0 0 1 0 1 setting of count direction of the transfer source address increment decrement fixed setting prohibited dad1 0 0 1 1 dad0 0 1 0 1 setting of count direction of the destination address after reset: 0000h r/w address: dadc0 fffff0d0h, dadc1 fffff0d2h, dadc2 fffff0d4h, dadc3 fffff0d6h sad1 sad0 dad1 dad0 0 0 0 0 0ds000 00 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 cautions 1. be sure to clear bits 15, 13 to 8, and 3 to 0 of the dadcn register to ?0?. 2. set the dadcn register at the following ti ming when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. the ds0 bit specifies the size of the transfer data, and does not control bus sizing. if 8-bit data (ds0 bit = 0) is set, therefore, the lower data bus is not always used. 4. if the transfer data size is set to 16 bits (ds0 bit = 1), transfer cannot be started from an odd address. transfer is always started from an address with the first bit of the lower address aligned to 0. 5. if dma transfer is executed on an on-chip pe ripheral i/o register (as the transfer source or destination), be sure to specify the same transfer size as the re gister size. for example, to execute dma transfer on an 8-bit register , be sure to specify 8-bit transfer.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 618 of 870 sep 30, 2010 (5) dma channel control registers 0 to 3 (dchc0 to dchc3) the dchc0 to dchc3 registers are 8-bi t registers that control the dma transfer operating mode for dma channel n. these registers can be read or written in 8-bit or 1-bit un its. (however, bit 7 is read-only and bits 1 and 2 are write- only. if bit 1 or 2 is read, the read value is always 0.) reset sets these registers to 00h. dchcn (n = 0 to 3) dma transfer had not completed. dma transfer had completed. it is set to 1 on the last dma transfer and cleared to 0 when it is read. tcn note 1 0 1 status flag indicates whether dma transfer through dma channel n has completed or not dma transfer disabled dma transfer enabled dma transfer is enabled when the enn bit is set to 1. when dma transfer is completed (when a terminal count is generated), this bit is automatically cleared to 0. to abort dma transfer, clear the enn bit to 0 by software. to resume, set the enn bit to 1 again. when aborting or resuming dma transfer, however, be sure to observe the procedure described in 18.13 cautions . enn 0 1 setting of whether dma transfer through dma channel n is to be enabled or disabled this is a software startup trigger of dma transfer. if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. stgn note 2 after reset: 00h r/w address: dchc0 fffff0e0h, dchc1 fffff0e2h, dchc2 fffff0e4h, dchc3 fffff0e6h tcn note 1 0 0 0 0 initn note 2 stgn note 2 enn <0> <1> <2> 3 4 5 6 <7> initn note 2 if the initn bit is set to 1 with dma transfer disabled (enn bit = 0), the dma transfer status can be initialized. when re-setting the dma transfer status (re-setting the ddanh, ddanl, dsanh, dsanl, dbcn, and dadcn registers) before dma transfer is completed (before the tcn bit is set to 1), be sure to initialize the dma channel. when initializing the dma controller, however, be sure to observe the procedure described in 18.13 cautions . notes 1. the tcn bit is read-only. 2. the initn and stgn bits are write-only. cautions 1. be sure to clear bits 6 to 3 of the dchcn register to 0. 2. when dma transfer is completed (when a terminal count is generated), the enn bit is cleared to 0 and then the tcn bit is set to 1. if the dchcn regist er is read while its bits are being updated, a value indicating ?transfer not co mpleted and transfer is disabled? (tcn bit = 0 and enn bit = 0) may be read.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 619 of 870 sep 30, 2010 (6) dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) the dtfr0 to dtfr3 registers are 8-bit registers that c ontrol the dma transfer start trigger via interrupt request signals from on-chip peripheral i/o. the interrupt request signals set by these re gisters serve as dma transfer start factors. these registers can be read or written in 8-bit units. however, dfn bit can be read or written in 1-bit units. reset sets these registers to 00h. dtfrn (n = 0 to 3) no dma transfer request dma transfer request dfn note 0 1 dma transfer request status flag after reset: 00h r/w address: dtfr0 fffff810h, dtfr1 fffff812h, dtfr2 fffff814h, dtfr3 fffff816h dfn 0 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 0 1 2 3 4 5 6 <7> note do not set the dfn bit to 1 by software. write 0 to this bit to clear a dma transfer request if an interrupt that is specified as the cause of starting dma transfer occurs while dma transfer is disabled. cautions 1. set the ifcn5 to if cn0 bits at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. an interrupt request that is generated in the standby mode (idel1, idle2, stop, or sub- idle mode) does not start the dma transfer cycle (nor is the dfn bit set to 1). 3. if a dma start factor is selected by the ifcn 5 to ifcn0 bits, the dfn bi t is set to 1 when an interrupt occurs from the selected on-chip pe ripheral i/o, regardless of whether the dma transfer is enabled or disable d. if dma is enabled in this status, dma transfer is immediately started. remark for the ifcn5 to ifcn0 bits, see table 18-1 dma start factors .
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 620 of 870 sep 30, 2010 table 18-1. dma start factors (1/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request by interrupt disabled 0 0 0 0 0 1 intp0 0 0 0 0 1 0 intp1 0 0 0 0 1 1 intp2 0 0 0 1 0 0 intp3 0 0 0 1 0 1 intp4 0 0 0 1 1 0 intp5 0 0 0 1 1 1 intp6 0 0 1 0 0 0 intp7 0 0 1 0 0 1 inttq0ov 0 0 1 0 1 0 inttq0cc0 0 0 1 0 1 1 inttq0cc1 0 0 1 1 0 0 inttq0cc2 0 0 1 1 0 1 inttq0cc3 0 0 1 1 1 0 inttp0ov 0 0 1 1 1 1 inttp0cc0 0 1 0 0 0 0 inttp0cc1 0 1 0 0 0 1 inttp1ov 0 1 0 0 1 0 inttp1cc0 0 1 0 0 1 1 inttp1cc1 0 1 0 1 0 0 inttp2ov 0 1 0 1 0 1 inttp2cc0 0 1 0 1 1 0 inttp2cc1 0 1 0 1 1 1 inttp3cc0 0 1 1 0 0 0 inttp3cc1 0 1 1 0 0 1 inttp4cc0 0 1 1 0 1 0 inttp4cc1 0 1 1 0 1 1 inttp5cc0 0 1 1 1 0 0 inttp5cc1 0 1 1 1 0 1 inttm0eq0 0 1 1 1 1 0 intcb0r/intiic1 0 1 1 1 1 1 intcb0t 1 0 0 0 0 0 intcb1r 1 0 0 0 0 1 intcb1t 1 0 0 0 1 0 intcb2r 1 0 0 0 1 1 intcb2t 1 0 0 1 0 0 intcb3r 1 0 0 1 0 1 intcb3t 1 0 0 1 1 0 intua0r/intcb4r 1 0 0 1 1 1 intua0t/intcb4t 1 0 1 0 0 0 intua1r/intiic2 1 0 1 0 0 1 intua1t 1 0 1 0 1 0 intua2r/intiic0 remark n = 0 to 3
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 621 of 870 sep 30, 2010 table 18-1. dma start factors (2/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 1 0 1 0 1 1 intua2t 1 0 1 1 0 0 intad 1 0 1 1 0 1 intkr other than above setting prohibited remark n = 0 to 3 18.4 transfer targets table 18-2 shows the relationship between the transfer targets ( : transfer enabled, : transfer disabled). table 18-2. relationship between transfer targets transfer destination internal rom on-chip peripheral i/o internal ram external memory on-chip peripheral i/o internal ram external memory source internal rom caution the operation is not guaranteed for combinat ions of transfer destination and source marked with ? ? in table 18-2.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 622 of 870 sep 30, 2010 18.5 transfer modes single transfer is supported as the transfer mode. in single transfer mode, the bus is released at each byte /halfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher priority dma transfer request is issued, the higher priority dma request always takes precedence. if a new transfer request of the same channel and a transf er request of another channel with a lower priority are generated in a transfer cycle, dma transfer of the channel with the lower priority is executed after the bus is released to the cpu (the new transfer request of the same channel is ignored in the transfer cycle). 18.6 transfer types as a transfer type, the 2-cycle transfer is supported. in two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. in the read cycle, the transfer source ad dress is output and reading is performed from the source to the dmac. in the write cycle, the transfer destination addr ess is output and writing is performed from the dmac to the destination. an idle cycle of one clock is always inserted between a read cycle and a write cycle. if the data bus width differs between the transfer source and destination for dma transfe r of two cycles, the operation is performed as follows. <16-bit data transfer> <1> transfer from 32-bit bus 16-bit bus a read cycle (the higher 16 bits are in a high-impedance state) is generated, follow ed by generation of a write cycle (16 bits). <2> transfer from 16-/32-bit bus to 8-bit bus a 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice. <3> transfer from 8-bit bus to 16-/32-bit bus an 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once. <4> transfer between 16-bit bus and 32-bit bus a 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once. for dma transfer executed to an on-chip peripheral i/o regist er (transfer source/destinati on), be sure to specify the same transfer size as the register size. for example, for dm a transfer to an 8-bit register, be sure to specify byte (8-bit) transfer. remark the bus width of each transfer target (tr ansfer source/destination) is as follows. ? on-chip peripheral i/o: 16-bit bus width ? internal ram: 32-bit bus width ? external memory: 8-bit or 16-bit bus width
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 623 of 870 sep 30, 2010 18.7 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 the priorities are checked for every transfer cycle. 18.8 time related to dma transfer the time required to respond to a dma request, and the mi nimum number of clocks required for dma transfer are shown below. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note 1 + transfer destination memory access (<2>) dma cycle minimum number of execution clocks <1> dma request response time 4 clocks (min.) + noise elimination time note 2 external memory access depends on connected memory. internal ram access 2 clocks note 3 <2> memory access peripheral i/o register access 3 clocks + number of wait cycles specified by vswc register note 4 notes 1. one clock is always inserted between a read cycle and a write cycle in dma transfer. 2. if an external interrupt (intpn) is specified as the tr igger to start dma transfer, noise elimination time is added (n = 0 to 7). 3. two clocks are required for a dma cycle. 4. more wait cycles are necessary for accessing a specific peripheral i/o register (for details, see 3.4.8 (2) ).
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 624 of 870 sep 30, 2010 18.9 dma transfer start factors there are two types of dma transfe r start factors, as shown below. (1) request by software if the stgn bit is set to 1 while the dchcn.tcn bit = 1 and enn bit = 1 (dma transfer enabled), dma transfer is started. to request the next dma transfer cycle i mmediately after that, confirm, by using the dbcn re gister, that the preceding dma transfer cycle has been completed, and set the stgn bit to 1 again (n = 0 to 3). tcn bit = 0, enn bit = 1 stgn bit = 1 ? starts the first dma transfer. confirm that the contents of the dbcn register have been updated. stgn bit = 1 ? starts the second dma transfer. : generation of terminal count ? enn bit = 0, tc n bit = 1, and intdman signal is generated. (2) request by on-chip peripheral i/o if an interrupt request is generated from the on-chip peripheral i/o set by the dtfrn register when the dchcn.tcn bit = 0 and enn bit = 1 (dma transf er enabled), dma transfer is started. cautions 1. two start factors (software trigger and hard ware trigger) cannot be u sed for one dma channel. if two start factors are simultaneously generate d for one dma channel, only one of them is valid. the start factor that is valid cannot be identified. 2. a new transfer request that is generate d after the preceding dma transfer request was generated or in the preceding dma tran sfer cycle is ignored (cleared). 3. the transfer request interval of the same dm a channel varies depending on the setting of bus wait in the dma transfer cycle, the start status of the other channels, or the external bus hold request. in particular, as described in caution 2, a new transfer request that is generated for the same channel before the dma transfer cycle or during the dma transfer cycle is ignored. therefore, the transfer request intervals fo r the same dma channel must be sufficiently separated by the system. when the software trigger is used, completion of the dma transfer cycle that was generated before can be checked by updating the dbcn register.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 625 of 870 sep 30, 2010 18.10 dma abort factors dma transfer is aborted if a bus hold occurs. the same applies if transfer is exec uted between the internal memory/on-chip peripheral i/o and internal memory/on- chip peripheral i/o. when the bus hold is cleared, dma transfer is resumed. 18.11 end of dma transfer when dma transfer has been completed the number of times set to the dbcn register and when the dchcn.enn bit is cleared to 0 and tcn bit is set to 1, a dma transfer end in terrupt request signal (intdman) is generated for the interrupt controller (intc) (n = 0 to 3). the v850es/jg3 does not output a terminal count signal to an external device. therefore, confirm completion of dma transfer by using the dma transfer end interrupt or polling the tcn bit. 18.12 operation timing figures 18-1 to 18-4 show dma operation timing.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 626 of 870 sep 30, 2010 figure 18-1. priority of dma (1) preparation for transfer read write idle end processing dma2 processing cpu processing dma1 processing cpu processing cpu processing dma0 processing dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit preparation for transfer read write idle end processing preparation for transfer read remarks 1. transfer in the order of dma0 dma1 dma2 2. in the case of transfer between external memory spaces (multiplexed bus, no wait)
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 627 of 870 sep 30, 2010 figure 18-2. priority of dma (2) preparation for transfer read write idle dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit cpu processing dma0 processing cpu processing dma1 processing cpu processing dma0 processing read write idle end processing read preparation for transfer preparation for transfer end processing remarks 1. transfer in the order of dma0 dma1 dma0 (dma2 is held pending.) 2. in the case of transfer between external memory spaces (multiplexed bus, no wait)
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 628 of 870 sep 30, 2010 figure 18-3. period in which dma transfer request is ignored (1) preparation for transfer read cycle write cycle idle end processing dma transfer mode of processing dfn bit system clock transfer request generated after this can be acknowledged dma0 processing cpu processing cpu processing note 2 note 2 dman transfer request note 1 note 2 notes 1. interrupt from on-chip peripheral i/o , or software trigger (stgn bit) 2. new dma request of the same channel is ignor ed between when the first request is generated and the end processing is complete. remark in the case of transfer between external memory spaces (multiplexed bus, no wait)
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 629 of 870 sep 30, 2010 figure 18-4. period in which dma transfer request is ignored (2) preparation for transfer read write idle end processing write end processing preparation for transfer read idle <1> <2> <3> <4> cpu processing dma0 processing cpu processing dma1 processing cpu processing preparation for transfer read dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit dma0 processing <1> dma0 transfer request <2> new dma0 transfer request is generated during dma0 transfer. a dma transfer request of the same channel is ignored during dma transfer. <3> requests for dma0 and dma1 are generated at the same time. dma0 request is ignored (a dma transfer request of the same channel during transfer is ignored). dma1 request is acknowledged. <4> requests for dma0, dma1, and dma2 are generated at the same time. dma1 request is ignored (a dma transfer request of the same channel during transfer is ignored). dma0 request is acknowledged according to priority. dma2 request is held pending (transfer of dma2 occurs next).
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 630 of 870 sep 30, 2010 18.13 cautions (1) caution for vswc register when using the dmac, be sure to set an appropriate value, in accordance with the operating frequency, to the vswc register. when the default value (77h) of the vswc r egister is used, or if an inappropriate value is set to the vswc register, the operation is not correctly performed (f or details of the vswc register, see 3.4.8 (1) (a) system wait control register (vswc) ). (2) caution for dma transfer executed on internal ram when executing the following instructions located in the internal ram, do not execute a dma transfer that transfers data to/from the internal ram (transfer source/destination) , because the cpu may not operate correctly afterward. ? bit manipulation instruction located in internal ram (set1, clr1, or not1) ? data access instruction to misaligned address located in internal ram conversely, when executing a dma transfer to transfer data to/from the internal ram (transfer source/destination), do not execute the above two instructions. (3) caution for reading dchcn .tcn bit (n = 0 to 3) the tcn bit is cleared to 0 when it is read, but it is not aut omatically cleared even if it is read at a specific timing. to accurately clear the tcn bit, add the following processing. (a) when waiting for completion of dma transfer by polling tcn bit confirm that the tcn bit has been set to 1 (after tcn bi t = 1 is read), and then read the tcn bit three more times. (b) when reading tcn bit in interrupt servicing routine execute reading the tcn bit three times.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 631 of 870 sep 30, 2010 (4) dma transfer initialization pr ocedure (setting dchcn.initn bit to 1) even if the initn bit is set to 1 when the channel execut ing dma transfer is to be initialized, the channel may not be initialized. to accurately initialize the chann el, execute either of the following two procedures. (a) temporarily stop transf er of all dma channels initialize the channel executing dma transfer using the procedure in <1> to <7> below. note, however, that tcn bit is cleared to 0 when step <5 > is executed. make sure that the other processing programs do not expect that the tcn bit is 1. <1> disable interrupts (di). <2> read the dchcn.enn bit of dma channels other than the one to be forcibly terminated, and transfer the value to a general-purpose register. <3> clear the enn bit of the dma channe ls used (including the channel to be forcibly terminated) to 0. to clear the enn bit of the last dma channel, execute the cl ear instruction twice. if the target of dma transfer (transfer source/destination) is the internal ram, execute the instruction three times. example: execute instructions in the following order if channels 0, 1, and 2 are used (if the target of transfer is not the internal ram). ? write dchc0 = 00h (clear the e00 bit to 0) ? write dchc1 = 00h (clear the e11 bit to 0) ? write dchc2 = 00h (clear the e22 bit to 0) ? write dchc2 = 00h again (clear the e22 bit to 0) <4> write dchcn = 04h to the channel to be forcibly terminated (set the initn bit to 1). <5> read the tcn bit of each channel not to be forcibly terminated. if both the tcn bit and the enn bit read in <2> are 1 (logical product (and) is 1), clear the saved enn bit to 0. <6> after the operation in <5>, write the enn bit value to the dchcn register. <7> enable interrupts (ei). cautions 1. be sure to execute st ep <5> above to prevent illegal setti ng of the enn bit of the channels whose dma transfer has been normally completed between <2> and <3>. 2. when a bit manipulation instruction is used, steps <3> and <4> (enn bit clear (0) and initn bit set (1)) are prohibited becau se the tcn bit is cleared to 0.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 632 of 870 sep 30, 2010 (b) repeatedly execute setting initn bit until transfer is forcibly terminated correctly <1> suppress a request from the dma request source of t he channel to be forcibly terminated (stop operation of the on-chip peripheral i/o). <2> check that the dma transfer request of the channel to be forcibly terminated is not held pending, by using the dtfrn.dfn bit. if a dma transfer request is held pe nding, wait until executi on of the pending request is completed. <3> when it has been confirmed that t he dma request of the channel to be forcibly terminated is not held pending, clear the enn bit to 0. <4> again, clear the enn bit of the channel to be forcibly terminated. if the target of transfer for the channel to be forcibly terminated (transfer source/des tination) is the internal ram, execute this operation once more. <5> copy the initial number of transfers of the channel to be forcibly terminated to a general-purpose register. <6> set the initn bit of the channel to be forcibly terminated to 1. <7> read the value of the dbcn register of the channel to be forcibly terminated, and compare it with the value copied in <5>. if the two values do not match, repeat operations <6> and <7>. remarks 1. when the value of the dbcn regist er is read in <7>, the initial number of transfers is read if forced termination has been correctly completed. if not, the remaining number of transfers is read. 2. note that method (b) may take a long time if the application frequently uses dma transfer for a channel other than the dma channel to be forcibly terminated. (5) procedure of temporarily stoppi ng dma transfer (clearing enn bit) stop and resume the dma transfer under ex ecution using the following procedure. <1> suppress a transfer request from the dma request source (stop the operation of t he on-chip peripheral i/o). <2> check the dma transfer request is not held pending , by using the dfn bit (check if the dfn bit = 0). if a request is pending, wait until execution of the pending dma transfer request is completed. <3> if it has been confirmed that no dma transfer request is held pending, clear the enn bit to 0 (this operation stops dma transfer). <4> set the enn bit to 1 to resume dma transfer. <5> resume the operation of the dma request source t hat has been stopped (start t he operation of the on-chip peripheral i/o). (6) memory boundary the operation is not guaranteed if the address of the transfer source or destination exceeds the area of the dma target (external memory, internal ram, or on-chip peripheral i/o) during dma transfer. (7) transferring misaligned data dma transfer of misaligned data with a 16-bit bus width is not supported. if an odd address is specified as the transfe r source or destination, the least signi ficant bit of the address is forcibly assumed to be 0.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 633 of 870 sep 30, 2010 (8) bus arbitration for cpu because the dma controller has a higher priority bus mastership than the cpu, a cpu access that takes place during dma transfer is held pe nding until the dma transfer cycle is comple ted and the bus is re leased to the cpu. however, the cpu can access the inte rnal rom, and internal ram to/from which dma transfer is not being executed. ? the cpu can access the internal rom and internal ram when dma transfer is being executed between the external memory and on-chip peripheral i/o. ? the cpu can access the internal rom when dma transfer is being executed between the on-chip peripheral i/o and internal ram. (9) registers/bits that must not be rewritten during dma operation set the following registers at the following ti ming when a dma operation is not under execution. [registers] ? dsanh, dsanl, ddanh, ddanl, dbcn, and dadcn registers ? dtfrn.ifcn5 to dtfrn.ifcn0 bits [timing of setting] ? period from after reset to start of the first dma transfer ? time after channel initializ ation to start of dma transfer ? period from after completion of dma transfer (tcn bit = 1) to start of the next dma transfer (10) be sure to set the foll owing register bits to 0. ? bits 14 to 10 of dsanh register ? bits 14 to 10 of ddanh register ? bits 15, 13 to 8, and 3 to 0 of dadcn register ? bits 6 to 3 of dchcn register (11) dma start factor do not start two or more dma channels with the same st art factor. if two or more channels are started with the same factor, dma for which a channel has already been se t may be started or a dma channel with a lower priority may be acknowledged earlier than a dma channel with a higher priority. the operat ion cannot be guaranteed.
v850es/jg3 chapter 18 dma function (dma controller) r01uh0015ej0300 rev.3.00 page 634 of 870 sep 30, 2010 (12) read values of dsan and ddan registers values in the middle of updating may be read from the ds an and ddan registers during dma transfer (n = 0 to 3). for example, if the dsanh register and then the dsanl register are read when the dma transfer source address (dsan register) is 0000ffffh and the co unt direction is incremental (da dcn.sad1 and dadcn.sad0 bits = 00), the value of the dsan register differs as follows, depending on whether dma transfe r is executed immediately after the dsanh register is read. (a) if dma transfer does not occu r while dsan register is read <1> read value of dsanh register: dsanh = 0000h <2> read value of dsanl register: dsanl = ffffh (b) if dma transfer occurs while dsan register is read <1> read value of dsanh register: dsanh = 0000h <2> occurrence of dma transfer <3> incrementing dsan register: dsan = 00100000h <4> read value of dsanl register: dsanl = 0000h
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 635 of 870 sep 30, 2010 chapter 19 interrupt/except ion processing function the v850es/jg3 is provided with a dedica ted interrupt controller (intc) for inte rrupt servicing and can process a total of 57 interrupt requests. an interrupt is an event that occurs independently of program execution, and an e xception is an event whose occurrence is dependent on program execution. the v850es/jg3 can process interrupt req uest signals from the on-chip peripheral hardware and external sources. moreover, exception processing can be started by the trap in struction (software exceptio n) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 19.1 features interrupts ? non-maskable interrupts: 2 sources ? maskable interrupts: external: 8, internal: 47 sources ? 8 levels of programmable priorities (maskable interrupts) ? multiple interrupt control according to priority ? masks can be specified for eac h maskable interrupt request. ? noise elimination, edge detection, and valid edge specification for external interrupt request signals. exceptions ? software exceptions: 32 sources ? exception trap: 2 sources (illegal opcode exception, debug trap) interrupt/exception sources are listed in table 19-1.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 636 of 870 sep 30, 2010 table 19-1. interrupt source list (1/2) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register reset interrupt ? reset reset pin input reset by internal source reset 0000h 00000000h undefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt2 wdt2 overflow wdt2 0020h 00000020h note 1 ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal opcode/dbtrap instruction ? 0060h 00000060h nextpc ? 0 intlvi low-voltage detection poclvi 0080h 00000080h nextpc lviic 1 intp0 external interrupt pin input edge detection (intp0) pin 0090h 00000090h nextpc pic0 2 intp1 external interrupt pin input edge detection (intp1) pin 00a0h 000000a0h nextpc pic1 3 intp2 external interrupt pin input edge detection (intp2) pin 00b0h 000000b0h nextpc pic2 4 intp3 external interrupt pin input edge detection (intp3) pin 00c0h 000000c0h nextpc pic3 5 intp4 external interrupt pin input edge detection (intp4) pin 00d0h 000000d0h nextpc pic4 6 intp5 external interrupt pin input edge detection (intp5) pin 00e0h 000000e0h nextpc pic5 7 intp6 external interrupt pin input edge detection (intp6) pin 00f0h 000000f0h nextpc pic6 8 intp7 external interrupt pin input edge detection (intp7) pin 0100h 00000100h nextpc pic7 9 inttq0ov tmq0 overflow tmq0 0110h 00000110h nextpc tq0ovic 10 inttq0cc0 tmq0 capture 0/compare 0 match tmq0 0120h 00000120h nextpc tq0ccic0 11 inttq0cc1 tmq0 capture 1/compare 1 match tmq0 0130h 00000130h nextpc tq0ccic1 12 inttq0cc2 tmq0 capture 2/compare 2 match tmq0 0140h 00000140h nextpc tq0ccic2 13 inttq0cc3 tmq0 capture 3/compare 3 match tmq0 0150h 00000150h nextpc tq0ccic3 14 inttp0ov tmp0 overflow tmp0 0160h 00000160h nextpc tp0ovic 15 inttp0cc0 tmp0 capture 0/compare 0 match tmp0 0170h 00000170h nextpc tp0ccic0 16 inttp0cc1 tmp0 capture 1/compare 1 match tmp0 0180h 00000180h nextpc tp0ccic1 17 inttp1ov tmp1 overflow tmp1 0190h 00000190h nextpc tp1ovic 18 inttp1cc0 tmp1 capture 0/compare 0 match tmp1 01a0h 000001a0h nextpc tp1ccic0 19 inttp1cc1 tmp1 capture 1/compare 1 match tmp1 01b0h 000001b0h nextpc tp1ccic1 20 inttp2ov tmp2 overflow tmp2 01c0h 000001c0h nextpc tp2ovic 21 inttp2cc0 tmp2 capture 0/compare 0 match tmp2 01d0h 000001d0h nextpc tp2ccic0 22 inttp2cc1 tmp2 capture 1/compare 1 match tmp2 01e0h 000001e0h nextpc tp2ccic1 23 inttp3ov tmp3 overflow tmp3 01f0h 000001f0h nextpc tp3ovic 24 inttp3cc0 tmp3 capture 0/compare 0 match tmp3 0200h 00000200h nextpc tp3ccic0 maskable interrupt 25 inttp3cc1 tmp3 capture 1/compare 1 match tmp3 0210h 00000210h nextpc tp3ccic1 notes 1. for the restoring in the case of intwdt2, see 19.2.2 (2) from intwdt2 signal . 2. n = 0 to fh
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 637 of 870 sep 30, 2010 table 19-1. interrupt source list (2/2) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 26 inttp4ov tmp4 overflow tmp4 0220h 00000220h nextpc tp4ovic 27 inttp4cc0 tmp4 capture 0/compare 0 match tmp4 0230h 00000230h nextpc tp4ccic0 28 inttp4cc1 tmp4 capture 1/compare 1 match tmp4 0240h 00000240h nextpc tp4ccic1 29 inttp5ov tmp5 overflow tmp5 0250h 00000250h nextpc tp5ovic 30 inttp5cc0 tmp5 capture 0/compare 0 match tmp5 0260h 00000260h nextpc tp5ccic0 31 inttp5cc1 tmp5 capture 1/compare 1 match tmp5 0270h 00000270h nextpc tp5ccic1 32 inttm0eq0 tmm0 compare match tmm0 0280h 00000280h nextpc tm0eqic0 33 intcb0r/ intiic1 csib0 reception completion/ csib0 reception error/ iic1 transfer completion csib0/ iic1 0290h 00000290h nextpc cb0ric/ iicic1 34 intcb0t csib0 consecutive transmission write enable csib0 02a0h 000002a0h nextpc cb0tic 35 intcb1r csib1 reception completion/ csib1 reception error csib1 02b0h 000002b0h nextpc cb1ric 36 intcb1t csib1 consecutive transmission write enable csib1 02c0h 000002c0h nextpc cb1tic 37 intcb2r csib2 reception completion/ csib2 reception error csib2 02d0h 000002d0h nextpc cb2ric 38 intcb2t csib2 consecutive transmission write enable csib2 02e0h 000002e0h nextpc cb2tic 39 intcb3r csib3 reception completion/ csib3 reception error csib3 02f0h 000002f0h nextpc cb3ric 40 intcb3t csib3 consecutive transmission write enable csib3 0300h 00000300h nextpc cb3tic 41 intua0r/ intcb4r uarta0 reception completion/ csib4 reception completion/ csib4 reception error uarta0/ csib4 0310h 00000310h nextpc ua0ric/ cb4ric 42 intua0t/ intcb4t uarta0 consecutive transmission enable/ csib4 consecutive transmission write enable uarta0/ csib4 0320h 00000320h nextpc ua0tic/ cb4tic 43 intua1r/ intiic2 uarta1 reception completion/ uarta1 reception error/ iic2 transfer completion uarta1/ iic2 0330h 00000330h nextpc ua1ric/ iicic2 44 intua1t uarta1 consecutive transmission enable uarta1 0340h 00000340h nextpc ua1tic 45 intua2r/ intiic0 uarta2 reception completion/ iic0 transfer completion uarta/ iic0 0350h 00000350h nextpc ua2ric/ iicic0 46 intua2t uarta2 consecutive transmission enable uarta2 0360h 00000360h nextpc ua2tic 47 intad a/d conversion completi on a/d 0370h 00000370h nextpc adic 48 intdma0 dma0 transfer completi on dma 0380h 00000380h nextpc dmaic0 49 intdma1 dma1 transfer completi on dma 0390h 00000390h nextpc dmaic1 50 intdma2 dma2 transfer completion dma 03a0h 000003a0h nextpc dmaic2 51 intdma3 dma3 transfer completion dma 03b0h 000003b0h nextpc dmaic3 52 intkr key return interrupt kr 03c0h 000003c0h nextpc kric 53 intwti watch timer interval wt 03d0h 000003d0h nextpc wtiic maskable interrupt 54 intwt watch timer reference time wt 03e0h 000003e0h nextpc wtic
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 638 of 870 sep 30, 2010 remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. the priority order of non-maskable interrupt is intwdt2 > nmi. restored pc: the value of the program counter (pc) saved to eipc, fepc, or dbpc when interrupt servicing is started. note, however, t hat the restored pc when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextpc (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value that starts the proc essing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4).
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 639 of 870 sep 30, 2010 19.2 non-maskable interrupts a non-maskable interrupt request signal is acknowledged uncond itionally, even when interr upts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupt request signals. this product has the following two non-maskable interrupt request signals. ? nmi pin input (nmi) ? non-maskable interrupt request signal generated by overflow of watchdog timer (intwdt2) the valid edge of the nmi pin can be se lected from four types: ?rising edge?, ?falling edge?, ?both edges?, and ?no edge detection?. the non-maskable interrupt request signal generated by over flow of watchdog timer 2 (intwdt2) functions when the wdtm2.wdm21 and wdtm2.wdm20 bits are set to ?01?. if two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority is serviced, as follows (the interrupt request signal with the lower priority is ignored). intwdt2 > nmi if a new nmi or intwdt2 request signal is issued while an nmi is being serviced, it is serviced as follows. (1) if new nmi request signal is i ssued while nmi is being serviced the new nmi request signal is held pending, regardless of the value of the psw.np bit. the pending nmi request signal is acknowledged after the nmi currently under exec ution has been serviced (after the reti instruction has been executed). (2) if intwdt2 request signal is issued while nmi is being serviced the intwdt2 request signal is held pending if the np bit remains set (1) while the nmi is being serviced. the pending intwdt2 request signal is acknowledged after the nmi currently under execution has been serviced (after the reti instruction has been executed). if the np bit is cleared (0) while the nmi is being se rviced, the newly generated intwdt2 request signal is executed (the nmi servicing is stopped). caution for the non-maskable interrupt servicing ex ecuted by the non-maskable interrupt request signal (intwdt2), see 19.2.2 (2) from intwdt2 signal. figure 19-1. non-maskable interrupt requ est signal acknowledgment operation (1/2) (a) nmi and intwdt2 request signa ls generated at the same time main routine system reset nmi and intwd t2 requests (generated simultaneously) intwd t2 servicing
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 640 of 870 sep 30, 2010 figure 19-1. non-maskable interrupt requ est signal acknowledgment operation (2/2) (b) non-maskable interrupt request signal ge nerated during non-maskab le interrupt servicing non-maskable interrupt being serviced non-maskable interrupt request signal generated during non-maskable interrupt servicing nmi intwdt2 nmi ? nmi request generated during nmi servicing ? intwdt2 request generated during nmi servicing (np bit = 1 retained before intwdt2 request) main routine nmi request nmi servicing (held pending) servicing of pending nmi nmi request main routine system reset nmi request nmi servicing (held pending) intwdt2 servicing intwdt2 request ? intwdt2 request generated during nmi servicing (np bit = 0 set before intwdt2 request) main routine system reset nmi request nmi servicing intwdt2 servicing intwdt2 request np = 0 ? intwdt2 request generated during nmi servicing (np = 0 set after intwdt2 request) main routine system reset nmi request nmi servicing intwdt2 servicing np = 0 ? intwdt2 request generated during intwdt2 servicing main routine system reset intwdt2 request intwdt2 servicing (invalid) ? nmi request generated during intwdt2 servicing intwdt2 main routine system reset intwdt2 request intwdt2 servicing (invalid) nmi request (held pending) intwdt2 request intwdt2 request
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 641 of 870 sep 30, 2010 19.2.1 operation if a non-maskable interrupt request signal is generated, t he cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes exception code (0010h, 0020h) to the higher halfword (fecc) of ecr. <4> sets the psw.np and psw.id bits to 1 and clears the psw.ep bit to 0. <5> sets the handler address (00000010h, 00000020h) corr esponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non- maskable interrupt is shown below. figure 19-2. servicing configurat ion of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h, 0020h 1 0 1 00000010h, 00000020h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 642 of 870 sep 30, 2010 19.2.2 restore (1) from nmi pin input execution is restored from the nmi se rvicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from fepc and fepsw, respectively, because the psw.ep bit is 0 and the psw.np bit is 1. <2> transfers control back to the address of the restored pc and psw. the processing of the reti in struction is shown below. figure 19-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the ep and np bits are changed by the ldsr instruction duri ng non-maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 0 and the np bit back to 1 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 643 of 870 sep 30, 2010 (2) from intwdt2 signal restoring from non-maskable interrupt servicing execut ed by the non-maskable interrupt request (intwdt2) by using the reti instruction is disabled. ex ecute the following software reset processing. figure 19-4. software reset processing intwdt2 occurs. fepc software reset processing address fepsw value that sets np bit = 1, ep bit = 0 reti reti 10 times (fepc and fepsw note must be set.) psw psw default value setting initialization processing intwdt2 servicing routine software reset processing routine note fepsw value that sets np bit = 1, ep bit = 0 19.2.3 np flag the np flag is a status flag that indicates that non -maskable interrupt servicing is under execution. this flag is set when a non-maskable interrupt request signal has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. 0 np ep id sat cy ov s z psw no nmi interrupt servicing nmi interrupt currently being serviced np 0 1 nmi interrupt servicing status after reset: 00000020h
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 644 of 870 sep 30, 2010 19.3 maskable interrupts maskable interrupt request signals can be masked by interrupt control registers. t he v850es/jg3 has 55 maskable interrupt sources. if two or more maskable interrupt request signals are generat ed at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). when an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request signals is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt service routine, the interr upt enabled (ei) status is set, which enables servicing of interrupts having a higher priority t han the interrupt request signal in progress (specified by the interrupt control register). note that only interrupts with a higher priority will have this capability; interrupts with the s ame priority level cannot be nested. to enable multiple interrupts, however, save eipc and eipsw to memory or general-purpose registers before executing the ei instruction, and execute the di instruction bef ore the reti instruction to re store the original values of eipc and eipsw. 19.3.1 operation if a maskable interrupt occurs, the cpu performs the following processing, and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the psw. id bit to 1 and clears the psw. ep bit to 0. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the maskable interrupt request signal masked by intc and the maskable interrupt request signal generated while another interrupt is being serviced (while the psw.np bit = 1 or the psw.id bit = 1) are held pending inside intc. in this case, servicing a new maskable interrupt is started in acco rdance with the priority of the pending maskable interrupt request signal if either the maskable interrupt is unmasked or the np and id bits are cleared to 0 by using the reti or ldsr instruction. how maskable interrupts are serviced is illustrated below.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 645 of 870 sep 30, 2010 figure 19-5. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc acknowledged yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address interrupt requested? note for the ispr register, see 19.3.6 in-service priority register (ispr) .
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 646 of 870 sep 30, 2010 19.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is executed , the cpu performs the following processi ng, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from eipc and ei psw, respectively, because the psw.ep bit is 0 and the psw.np bit is 0. <2> transfers control back to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 19-6. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for the ispr register, see 19.3.6 in-service priority register (ispr) . caution when the ep and np bits are changed by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 0 and the np bit back to 0 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 647 of 870 sep 30, 2010 19.3.3 priorities of maskable interrupts the intc performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are spec ified by the interrupt priority level spec ification bit (xxprn) of the interrupt cont rol register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupt request signals are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, see table 19-1 interrupt source list . the programmable priority control customizes in terrupt request signals into eight levels by setting the priority level specificatio n flag. note that when an interrupt request signal is acknowledged, the psw.id flag is automat ically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing the ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (see table 19-2 interrupt control register (xxicn) ) n: peripheral unit number (see table 19-2 interrupt control register (xxicn) ).
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 648 of 870 sep 30, 2010 figure 19-7. example of processing in which another interrupt request signal is issued while an interrupt is being serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, th e values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates t he relative priority between two interrupt request signals.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 649 of 870 sep 30, 2010 figure 19-7. example of processing in which another interrupt request signal is issued while an interrupt is being serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, th e values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 650 of 870 sep 30, 2010 figure 19-8. example of servicing interrupt request signals simu ltaneously generated default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution to perform multiple interrupt servicing, th e values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to c in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates t he relative priority between two interrupt request signals.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 651 of 870 sep 30, 2010 19.3.4 interrupt control register (xxicn) the xxicn register is assigned to each interrupt request signal (maskable interrupt ) and sets the control conditions for each maskable interrupt request. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 47h. caution disable interrupts (di) or mask the interrupt to read the xxicn.xxifn bi t. if the xxifn bit is read while interrupts are enabled (ei) or while the interrupt is unmasked, the correct value may not be read when acknowledging an interrupt and reading the bit conflict. xxifn interrupt request not issued interrupt request issued xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 interrupt servicing enabled interrupt servicing disabled (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest). specifies level 1. specifies level 2. specifies level 3. specifies level 4. specifies level 5. specifies level 6. specifies level 7 (lowest). xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff1a8h <6> <7> note the flag xxlfn is reset automatically by the hardwa re if an interrupt request signal is acknowledged. remark xx: identification name of each peripheral unit (see table 19-2 interrupt control register (xxicn) ) n: peripheral unit number (see table 19-2 interrupt control register (xxicn) ). the addresses and bits of the interrupt control registers are as follows.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 652 of 870 sep 30, 2010 table 19-2. interrupt control register (xxicn) (1/2) bit address register <7> <6> 5 4 3 2 1 0 fffff110h lviic lviif lvimk 0 0 0 lvipr2 lvipr1 lvipr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h pic7 pif7 pmk7 0 0 0 ppr72 ppr71 ppr70 fffff122h tq0ovic tq0ovif tq0ovmk 0 0 0 tq0ovpr2 tq0ovpr1 tq0ovpr0 fffff124h tq0ccic0 tq0ccif0 tq0ccmk0 0 0 0 tq0ccpr02 tq0ccpr01 tq0ccpr00 fffff126h tq0ccic1 tq0ccif1 tq0ccmk1 0 0 0 tq0ccpr12 tq0ccpr11 tq0ccpr10 fffff128h tq0ccic2 tq0ccif2 tq0ccmk2 0 0 0 tq0ccpr22 tq0ccpr21 tq0ccpr20 fffff12ah tq0ccic3 tq0ccif3 tq0ccmk3 0 0 0 tq0ccpr32 tq0ccpr31 tq0ccpr30 fffff12ch tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff12eh tp0ccic0 tp0ccif0 tp0ccmk0 0 0 0 tp0ccp r02 tp0ccpr01 tp0ccpr00 fffff130h tp0ccic1 tp0ccif1 tp0ccmk1 0 0 0 tp0ccpr12 tp0ccpr11 tp0ccpr10 fffff132h tp1ovic tp1ovif tp1ovmk 0 0 0 tp1ovpr2 tp1ovpr1 tp1ovpr0 fffff134h tp1ccic0 tp1ccif0 tp1ccmk0 0 0 0 tp1ccpr02 tp1ccpr01 tp1ccpr00 fffff136h tp1ccic1 tp1ccif1 tp1ccmk1 0 0 0 tp1ccpr12 tp1ccpr11 tp1ccpr10 fffff138h tp2ovic tp2ovif tp2ovmk 0 0 0 tp2ovpr2 tp2ovpr1 tp2ovpr0 fffff13ah tp2ccic0 tp2ccif0 tp2ccmk0 0 0 0 tp2ccp r02 tp2ccpr01 tp2ccpr00 fffff13ch tp2ccic1 tp2ccif1 tp2ccmk1 0 0 0 tp2ccpr12 tp2ccpr11 tp2ccpr10 fffff13eh tp3ovic tp3ovif tp3ovmk 0 0 0 tp3ovpr2 tp3ovpr1 tp3ovpr0 fffff140h tp3ccic0 tp3ccif0 tp3ccmk0 0 0 0 tp3ccpr02 tp3ccpr01 tp3ccpr00 fffff142h tp3ccic1 tp3ccif1 tp3ccmk1 0 0 0 tp3ccpr12 tp3ccpr11 tp3ccpr10 fffff144h tp4ovic tp4ovif tp4ovmk 0 0 0 tp4ovpr2 tp4ovpr1 tp4ovpr0 fffff146h tp4ccic0 tp4ccif0 tp4ccmk0 0 0 0 tp4ccpr02 tp4ccpr01 tp4ccpr00 fffff148h tp4ccic1 tp4ccif1 tp4ccmk1 0 0 0 tp4ccpr12 tp4ccpr11 tp4ccpr10 fffff14ah tp5ovic tp5ovif tp5ovmk 0 0 0 tp5ovpr2 tp5ovpr1 tp5ovpr0 fffff14ch tp5ccic0 tp5ccif0 tp5ccmk0 0 0 0 tp5ccpr02 tp5ccpr01 tp5ccpr00 fffff14eh tp5ccic1 tp5ccif1 tp5ccmk1 0 0 0 tp5ccp r12 tp5ccpr11 tp5ccpr10 fffff150h tm0eqic0 tm0eqif0 tm0eqmk0 0 0 0 tm0eqpr02 tm0eqpr01 tm0eqpr00 fffff152h cb0ric/ iicic1 cb0rif/ iicif1 cb0rmk/ iicmk1 0 0 0 cb0rpr2/ iicpr12 cb0rpr1/ iicpr11 cb0rpr0/ iicpr10 fffff154h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0 fffff156h cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff158h cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 fffff15ah cb2ric cb2rif cb2rmk 0 0 0 cb2rpr2 cb2rpr1 cb2rpr0 fffff15ch cb2tic cb2tif cb2tmk 0 0 0 cb2tpr2 cb2tpr1 cb2tpr0 fffff15eh cb3ric cb3rif cb3rmk 0 0 0 cb3rpr2 cb3rpr1 cb3rpr0 fffff160h cb3tic cb3tif cb3tmk 0 0 0 cb3tpr2 cb3tpr1 cb3tpr0
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 653 of 870 sep 30, 2010 table 19-2. interrupt control register (xxicn) (2/2) bit address register <7> <6> 5 4 3 2 1 0 fffff162h ua0ric/ cb4ric ua0rif/ cb4rif ua0rmk/ cb4rmk 0 0 0 ua0rpr2/ cb4rpr2 ua0rpr1/ cb4rpr1 ua0rpr0/ cb4rpr0 fffff164h ua0tic/ cb4tic ua0tif/ cb4tif ua0tmk/ cb4tmk 0 0 0 ua0tpr2/ cb4tpr2 ua0tpr1/ cb4tpr1 ua0tpr0/ cb4tpr0 fffff166h ua1ric/ iicic2 ua1rif/ iicif2 ua1rmk/ iicmk2 0 0 0 ua1rpr2/ iicpr22 ua1rpr1/ iicpr21 ua1rpr0/ iicpr20 fffff168h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff16ah ua2ric/ iicic0 ua2rif/ iicif0 ua2rmk/ iicmk0 0 0 0 ua2rpr2/ iicpr02 ua2rpr1/ iicpr01 ua2rpr0/ iicpr00 fffff16ch ua2tic ua2tif ua2tmk 0 0 0 ua2tpr2 ua2tpr1 ua2tpr0 fffff16eh adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff170h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff172h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff174h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff176h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff178h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff17ah wtiic wtiif wtimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff17ch wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0 19.3.5 interrupt mask register s 0 to 3 (imr0 to imr3) the imr0 to imr3 registers set the in terrupt mask state for the maskable interr upts. the xxmkn bit of the imr0 to imr3 registers is equivalent to the xxicn.xxmkn bit. the imrm register can be read or written in 16-bit units (m = 0 to 3). if the higher 8 bits of the imrm regi ster are used as an imrmh register and th e lower 8 bits as an imrml register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 3). reset sets these registers to ffffh. caution the device file defines the xxicn.xxmkn bit as a reser ved word. if a bit is manipulated using the name of xxmkn, the contents of the xxicn register, instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten).
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 654 of 870 sep 30, 2010 tp0ccmk0 pmk6 imr0 (imr0h note ) imr0l tp0ovmk pmk5 tq0ccmk3 pmk4 tq0ccmk2 pmk3 tq0ccmk1 pmk2 tq0ccmk0 pmk1 tq0ovmk pmk0 pmk7 lvimk after reset: ffffh r/w address: imr0 fffff100h, imr0l fffff100h, imr0h fffff101h after reset: ffffh r/w address: imr1 fffff102h, imr1l fffff102h, imr1h fffff103h after reset: ffffh r/w address: imr2 fffff104h, imr2l fffff104h, imr2h fffff105h tp5ccmk1 tp3ovmk imr1 (imr1h note ) imr1l tp5ccmk0 tp2ccmk1 tp5ovmk tp2ccmk0 tp4ccmk1 tp2ovmk tp4ccmk0 tp1ccmk1 tp4ovmk tp1ccmk0 tp3ccmk1 tp1ovmk tp3ccmk0 tp0ccmk1 admk cb3rmk cb3tmk tm0eqmk0 xxmkn 0 1 interrupt servicing enabled interrupt servicing disabled imr2 (imr2h note ) imr2l ua2tmk cb2tmk cb2rmk ua1tmk cb1tmk cb1rmk cb0tmk ua0tmk/ cb4tmk ua2rmk/ iicmk0 ua0rmk/ cb4rmk cb0rmk/ iicmk1 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 1 imr3 (imr3h note ) imr3l 1 wtmk 1 wtimk 1 krmk 1 dmamk3 dmamk2 dmamk1 dmamk0 after reset: ffffh r/w address: imr3 fffff106h, imr3l fffff106h, imr3h fffff107h 8 1 9 1 10 1 11 12 13 14 15 1 2 3 4 5 6 7 1 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 setting of interrupt mask flag 14 15 1 2 3 4 5 6 7 0 ua1rmk/ iic2mk note to read bits 8 to 15 of the imr0 to imr3 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of imr0h to imr3h registers. caution set bits 7 to 15 of the imr3 register to 1. if the setting of these bits is changed, the operation is not guaranteed. remark xx: identification name of each peripheral unit (see table 19-2 interrupt control register (xxicn) ). n: peripheral unit number (see table 19-2 interrupt control register (xxicn) )
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 655 of 870 sep 30, 2010 19.3.6 in-service priority register (ispr) the ispr register holds the priority level of the maskable in terrupt currently acknowledged. when an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that in terrupt request signal is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, t he bit corresponding to the interrupt request signal having the highest priority is automatically reset to 0 by hardware. ho wever, it is not reset to 0 when execut ion is returned from non-maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after the bits of the register have been set by acknowledging the interrupt may be read. to accurately read the valu e of the ispr register before an interrupt is acknowledged, read the register while interrupts are disabled (di). ispr7 interrupt request signal with priority n not acknowledged interrupt request signal with priority n acknowledged isprn 0 1 priority of interrupt currently acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah <7> <6> <5> <4> <3> <2> <1> <0> remark n = 0 to 7 (priority level)
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 656 of 870 sep 30, 2010 19.3.7 id flag this flag controls the maskable interrupt?s operating st ate, and stores control info rmation regarding enabling or disabling of interrupt request signals. an inte rrupt disable flag (id) is assigned to the psw. reset sets this flag to 00000020h. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled (pending) id 0 1 specification of maskable interrupt servicing note after reset: 00000020h note interrupt disable flag (id) function this bit is set to 1 by the di instruction and cleared to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instru ction when referencing the psw. non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. when a maskable interrupt request signal is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request signal generated during the acknowledgment disabled period (id flag = 1) is acknowledged when the xxicn.xxifn bit is set to 1, and the id flag is cleared to 0. 19.3.8 watchdog timer mode register 2 (wdtm2) this register can be read or writt en in 8-bit units (for details, see chapter 11 functions of watchdog timer 2 ). reset sets this register to 67h. 0 wdtm2 wdm21 wdm20 0 0 0 0 0 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode reset mode (initial-value) wdm21 0 0 1 wdm20 0 1 selection of watchdog timer operation mode
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 657 of 870 sep 30, 2010 19.4 software exception a software exception is generated when the cpu executes the trap instructi on, and can always be acknowledged. 19.4.1 operation if a software exception occurs, the cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits to 1. <5> sets the handler address (00000040h or 00000050h) corresponding to the software exception to the pc, and transfers control. the processing of a software exception is shown below. figure 19-9. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (t he vector is a value from 00h to 1fh.) the handler address is determined by the trap instruction?s oper and (vector). if the vector is 00h to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 658 of 870 sep 30, 2010 19.4.2 restore restoration from software exception processing is carried out by the reti instruction. by executing the reti instruct ion, the cpu carries out the following processing and shifts control to the restored pc?s address. <1> loads the restored pc and psw from ei pc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 19-10. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep and np bits are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 1 and the np bit back to 0 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 659 of 870 sep 30, 2010 19.4.3 ep flag the ep flag is a status flag used to indicate that exception proc essing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress. exception processing in progress. ep 0 1 exception processing status after reset: 00000020h
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 660 of 870 sep 30, 2010 19.5 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. in the v850es/jg3, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 19.5.1 illegal opcode definition the illegal instruction has an opcode (bit s 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an instruction applicable to this illegal instruction is executed. 15 16 23 22 xxxxxx0 x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to x: arbitrary caution since it is possible to assign this instruction to an illegal opcode in the futu re, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the follo wing processing, and transfers control to the handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. the processing of the exc eption trap is shown below. figure 19-11. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 661 of 870 sep 30, 2010 (2) restoration restoration from an exception trap is ca rried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. caution dbpc and dbpsw can be accessed only during th e interval between the execution of an illegal opcode and the dbret instruction. the restore processing from an exception trap is shown below. figure 19-12. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 662 of 870 sep 30, 2010 19.5.2 debug trap a debug trap is an exception that is generated when the db trap instruction is executed and is always acknowledged. (1) operation upon occurrence of a debug trap, the cpu performs the following processing. <1> saves restored pc to dbpc. <2> saves current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets handler address (00000060h) for debug trap to pc and transfers control. the debug trap processing format is shown below. figure 19-13. debug trap processing format dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 663 of 870 sep 30, 2010 (2) restoration restoration from a debug trap is exec uted with the dbret instruction. with the dbret instruction, the cpu performs the follo wing steps and transfers cont rol to the address of the restored pc. <1> the restored pc and psw are read from dbpc and dbpsw. <2> control is transferred to the fetc hed address of the restored pc and psw. caution dbpc and dbpsw can be accessed only duri ng the interval between the execution of the dbtrap instruction and the dbret instruction. the processing format for restoration from a debug trap is shown below. figure 19-14. processing format of restoration from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 664 of 870 sep 30, 2010 19.6 external interrupt request input pins (nmi and intp0 to intp7) 19.6.1 noise elimination (1) eliminating noise on nmi pin the nmi pin has an internal noise eliminat ion circuit that uses analog delay. therefore, the input level of the nmi pin is not detected as an edge unless it is maintained for a specific time or longer. therefore, an edge is detected after specific time. the nmi pin can be used to release the stop mode. in the stop mode, noise is not eliminated by using the system clock because the internal system clock is stopped. (2) eliminating noise on intp0 to intp7 pins the intp0 to intp7 pins have an internal noise eliminati on circuit that uses analog de lay. therefore, the input level of the nmi pin is not detected as an edge unless it is maintained for a specific time or longer. therefore, an edge is detected after specific time. 19.6.2 edge detection the valid edge of each of the nmi and intp0 to in tp7 pins can be selected from the following four. ? rising edge ? falling edge ? both rising and falling edges ? no edge detected the edge of the nmi pin is not detected after reset. therefore, the interr upt request signal is not acknowledged unless a valid edge is enabled by using the intf0 and intr0 re gister (the nmi pin functions as a normal port pin).
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 665 of 870 sep 30, 2010 (1) external interrupt fallin g, rising edge specification register 0 (intf0, intr0) the intf0 and intr0 registers are 8-bi t registers that specify detection of the falling and rising edges of the nmi pin via bit 2 and the external interrupt pins (intp0 to intp3) via bits 3 to 6. these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the external interrupt functi on (alternate function) to the port function, an edge may be detected. therefore, cl ear the intf0n and intr0n bits to 00, and then set the port mode. 0 intf0 intf06 intp3 intf05 intf04 intf03 intf02 0 0 after reset: 00h r/w address: intf0 fffffc00h, intr0 fffffc20h 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 intp2 intp1 intp0 nmi intp3 intp2 intp1 intp0 nmi remark for how to specify a valid edge, see table 19-3 . table 19-3. valid edge specification intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf0 n and intr0n bits to 00 when these registers are not used as the nmi or intp0 to intp3 pins. remark n = 2: control of nmi pin n = 3 to 6: control of intp0 to intp3 pins
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 666 of 870 sep 30, 2010 (2) external interrupt fallin g, rising edge specification register 3 (intf3, intr3) the intf3 and intr3 registers are 8-bi t registers that specify detection of the falling and rising edges of the external interrupt pin (intp7). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. cautions 1. when the function is changed from the ex ternal interrupt function (a lternate function) to the port function, an edge may be detected. there fore, clear the intf31 and intr31 bits to 00, and then set the port mode. 2. the intp7 pin and rxda0 pin are alternate -function pins. when using the pin as the rxda0 pin, disable edge detection for the intp7 al ternate-function pin (clear the intf3.intf31 bit and the inrt3.intr31 bit to 0). when using th e pin as the intp7 pin, stop uarta0 reception (clear the ua0ctl0.ua0rxe bit to 0). intf3 after reset: 00h r/w address: intf3 fffffc06h, intr3 fffffc26h 0 0 0 0 0 0 intf31 0 intr3 0 0 0 0 0 0 intr31 0 intp7 intp7 remark for how to specify a valid edge, see table 19-4 . table 19-4. valid edge specification intf31 intr31 valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf31 and intr31 bits to 00 when these registers are not used as intp7 pin.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 667 of 870 sep 30, 2010 (3) external interrupt fallin g, rising edge specification re gister 9h (intf9h, intr9h) the intf9h and intr9h registers are 8- bit registers that specify detection of the falling and rising edges of the external interrupt pins (intp4 to intp6). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the external interrupt functi on (alternate function) to the port function, an edge may be detected. therefore, cl ear the intf9n and intr9n bits to 0, and then set the port mode. intf9h after reset: 00h r/w address: intf9h fffffc13h, intr9h fffffc33h intf915 intf914 intf913 0 0 0 0 0 8 9 10 11 12 13 14 15 intr9h intr915 intr914 intr913 0 0 0 0 0 8 9 10 11 12 13 14 15 intp6 intp5 intp4 intp6 intp5 intp4 remark for how to specify a valid edge, see table 19-5 . table 19-5. valid edge specification intf9n intr9n valid edge specification (n = 13 to 15) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf9n and intr9n bi ts to 00 when these registers are not used as intp4 to intp6 pins. remark n = 13 to 15: control of intp4 to intp6 pins
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 668 of 870 sep 30, 2010 (4) noise elimination control register (nfc) digital noise elimination can be selected for the intp3 pin. the noise elimination settings are performed using the nfc register. when digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, and f xt . sampling is performed three times. when digital noise elimination is select ed, if the clock that performs sampli ng in the standby m ode is stopped, then the intp3 interrupt request signal cannot be used for releasing the standby mode. when f xt is used as the sampling clock, the intp3 interrupt request signal can be used for releasing either the subclock operating mode or the idle1/idle2/stop/sub-idle mode. this register can be read or written in 8-bit units. reset sets this register to 00h. caution after the sampling clock has been changed, it takes 3 sampling clocks to initialize the digital noise eliminator. therefore, if an intp3 valid ed ge is input within these 3 sampling clocks after the sampling clock has been changed, an interrupt request signal may be generated. therefore, be careful about the following points when using the interrupt and dma functions. ? when using the interrupt function, after the 3 sampling clocks have elapsed, enable interrupts after the interrupt request flag (p ic3.pif3 bit) has been cleared. ? when using the dma function (started by in tp3), enable dma after 3 sampling clocks have elapsed. nfen nfc 0 0 0 0 nfc2 nfc1 nfc0 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xt (subclock) nfc2 0 0 0 0 1 1 digital sampling clock setting prohibited nfc1 0 0 1 1 0 0 nfc0 0 1 0 1 0 1 after reset: 00h r/w address: fffff318h analog noise elimination (60 ns (typ.)) digital noise elimination nfen 0 1 settings of intp3 pin noise elimination other than above remarks 1. since sampling is performed three times, the reliably eliminated noise width is 2 sampling clocks. 2. in the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input.
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 669 of 870 sep 30, 2010 19.7 interrupt acknowledge time of cpu except the following cases, the interrupt acknowledge time of the cpu is 4 clo cks minimum. to input interrupt request signals successively, input the next interrupt request sig nal at least 5 clocks after the preceding interrupt. ? in idle1/idle2/stop mode ? when the external bus is accessed ? when interrupt request non-sampling instructions are successively executed (see 19.8 periods in which interrupts are not acknowledged by cpu .) ? when the interrupt control register is accessed figure 19-15. pipeline operation at interr upt request signal acknowledgment (outline) (1) minimum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem wb ifx idx int1 int2 int3 int4 4 system clocks (2) maximum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem mem mem wb ifx idx int1 int2 int3 int3 int3 int4 6 system clocks remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt acknowledge time (internal system clock) internal interrupt external interrupt condition minimum 4 4 + analog delay time maximum 6 6 + analog delay time the following cases are exceptions. ? in idle1/idle2/stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to peripheral i/o register
v850es/jg3 chapter 19 interrupt/ exception processi ng function r01uh0015ej0300 rev.3.00 page 670 of 870 sep 30, 2010 19.8 periods in which interrupts are not acknowledged by cpu an interrupt is acknowledged by the cpu while an instru ction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instructi on and the next instruction (int errupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the prcmd register ? the store, set1, not1, or clr1 inst ructions for the following registers. ? interrupt-related registers: interrupt control register (xxicn), interr upt mask registers 0 to 3 (imr0 to imr3) ? power save control register (psc) ? on-chip debug mode register (ocdm) remark xx: identification name of each peripheral unit (see table 19-2 interrupt control register (xxicn) ) n: peripheral unit number (see table 19-2 interrupt control register (xxicn) ). 19.9 cautions the nmi pin and p02 pin are an alternate- function pin, and function as a normal port pin after being reset. to enable the nmi pin, validate the nmi pin with the pmc0 register. the initial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge using the intf0 and intr0 registers.
v850es/jg3 chapter 20 key interrupt function r01uh0015ej0300 rev.3.00 page 671 of 870 sep 30, 2010 chapter 20 key interrupt function 20.1 function a key interrupt request signal (intkr) can be generated by inpu tting a falling edge to the eight key input pins (kr0 to kr7) by setting the krm register. table 20-1. assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units figure 20-1. key re turn block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0
v850es/jg3 chapter 20 key interrupt function r01uh0015ej0300 rev.3.00 page 672 of 870 sep 30, 2010 20.2 register (1) key return mode register (krm) the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. krm7 does not detect key return signal detects key return signal krmn 0 1 control of key return mode krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 after reset: 00h r/w address: fffff300h caution rewrite the krm register after once clearing the krm register to 00h. remark for the alternate-function pin settings, see table 4-15 using port pin as alternate- function pin . 20.3 cautions (1) if a low level is input to any of the kr0 to kr7 pins, the intkr signal is not generated even if the falling edge of another pin is input. (2) the rxda1 and kr7 pins must not be us ed at the same time. to use the rxda1 pin, do not use the kr7 pin. to use the kr7 pin, do not use the rxda1 pin (it is recomm ended to set the pfc91 bit to 1 and clear pfce91 bit to 0). (3) if the krm register is changed, an interrupt request si gnal (intkr) may be generated. to prevent this, change the krm register after disabling interrupts (di) or masking, t hen clear the interrupt request flag (kric.krif bit) to 0, and enable interrupts (ei) or clear the mask. (4) to use the key interrupt function, be sure to set the port pin to the key return pin and then enable the operation with the krm register. to switch from the key return pin to the port pin, dis able the operation with the krm register and then set the port pin.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 673 of 870 sep 30, 2010 chapter 21 standby function 21.1 overview the power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. the available stan dby modes are listed in table 21-1. table 21-1. standby modes mode functional outline halt mode mode in which only the operating clock of the cpu is stopped idle1 mode mode in which all the operations of the internal circuits except the oscillator, pll note , and flash memory are stopped idle2 mode mode in which all the operations of internal circuits except the oscillator are stopped stop mode mode in which all the operations of internal circuits except the subclock oscillator are stopped subclock operation mode mode in which the subclock is used as the internal system clock sub-idle mode mode in which all the operations of internal circuits except the oscillator are stopped, in the subclock operation mode note the pll holds the prev ious operating status.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 674 of 870 sep 30, 2010 figure 21-1. status transition reset subclock operation mode (fx operates, pll operates) subclock operation mode (fx stops, pll stops) sub-idle mode (fx operates, pll operates) sub-idle mode (fx stops, pll stops) stop mode (fx stops, pll stops) idle2 mode (fx operates, pll stops) idle1 mode (fx operates, pll operates) idle1 mode (fx operates, pll stops) halt mode (fx operates, pll stops) halt mode (fx operates, pll operates) normal operation mode oscillation stabilization wait clock through mode (pll operates) clock through mode (pll stops) pll mode (pll operates) internal oscillation clock operation wdt overflow oscillation stabilization wait note pll lockup time wait oscillation stabilization wait note oscillation stabilization wait note note if a wdt overflow occurs during an oscillation stabilization time, the cpu operates on the internal oscillation clock. remark f x : main clock oscillation frequency
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 675 of 870 sep 30, 2010 21.2 registers (1) power save control register (psc) the psc register is an 8-bit register t hat controls the standby func tion. the stp bit of this register is used to specify the stop mode. this register is a special register that can be written only by the special sequence combinations (see 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 psc nmi1m nmi0m intm 0 0 stp 0 releasing standby mode by intwdt2 signal enabled releasing standby mode by intwdt2 signal disabled nmi1m 0 1 control of releasing standby mode by intwdt2 signal releasing standby mode by nmi pin input enabled releasing standby mode by nmi pin input disabled nmi0m 0 1 control of releasing standby mode by nmi pin input releasing standby mode by maskable interrupt request signals enabled releasing standby mode by maskable interrupt request signals disabled intm 0 1 control of releasing standby mode by maskable interrupt request signals normal mode standby mode stp 0 1 standby mode setting after reset: 00h r/w address: fffff1feh < > < > < > < > note standby mode set by stp bit: idle1, idle2, stop, or sub-idle mode cautions 1. before setting the idle1, idle2, stop, or sub-idle mode, set the psmr.psm1 and psmr.psm0 bits and then set the stp bit. 2. settings of the nmi1m, nmi0m, and in tm bits are invalid when halt mode is released. 3. if the nmi1m, nmi0m, or intm bit is set to 1 at the same ti me the stp bit is set to 1, the setting of nmi1m, nmi0m, or in tm bit becomes invalid. if there is an unmasked interrupt request signal being held pending when the idle1/idle2/stop mode is set, set the bit corresponding to the interrupt request signal (nmi1m, nmi0m, or intm) to 1, and then set the stp bit to 1.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 676 of 870 sep 30, 2010 (2) power save mode register (psmr) the psmr register is an 8-bit register that controls the operation status in the power save mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 idle1, sub-idle modes stop, sub-idle modes idle2, sub-idle modes stop mode psm1 0 0 1 1 specification of operation in software standby mode psmr 0 0 0 0 0 psm1 psm0 after reset: 00h r/w address: fffff820h psm0 0 1 0 1 < > < > cautions 1. be sure to cl ear bits 2 to 7 to ?0?. 2. the psm0 and psm1 bits are valid only when the psc.stp bit is 1. remark idle1: in this mode, all operations except the oscillator operation and some other circuits (flash memory and pll) are stopped. after the idle1 mode is released, the norma l operation mode is restored without needing to secure the oscillation stabilization time, like the halt mode. idle2: in this mode, all operations ex cept the oscillator operation are stopped. after the idle2 mode is released, the nor mal operation mode is restored following the lapse of the setup time specified by t he osts register (flash memory and pll). stop: in this mode, all operations except the subclock oscillator operation are stopped. after the stop mode is released, the normal operation mode is restored following the lapse of the oscillation stabilization time specified by the osts register. sub-idle: in this mode, all other operations are halte d except for the oscillator. after the idle mode has been released by the interrupt request signal, the subclock operation mode will be restored after 12 cycles of the subclock have been secured.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 677 of 870 sep 30, 2010 (3) oscillation stabilization time select register (osts) the wait time until the oscillation stabi lizes after the stop mode is released or the wait time until the on-chip flash memory stabilizes after the idle2 mode is released is controlled by the osts register. the osts register can be read or written 8-bit units. reset sets this register to 06h. 0 osts 0 0 0 0 osts2 osts1 osts0 osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time/setup time note osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 after reset: 06h r/w address: fffff6c0h 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x 4 mhz 0.256 ms 0.512 ms 1.024 ms 2.048 ms 4.096 ms 8.192 ms 16.38 ms 5 mhz 0.205 ms 0.410 ms 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.107 ms f x setting prohibited note the oscillation stabilization time and setu p time are required when the stop mode and idle2 mode are released, respectively. cautions 1. the wait time following release of the stop mode does not include the time until the clock oscillation starts (?a? in the figure below) following release of the stop mode, regardless of whether th e stop mode is released by reset or the occurrence of an in terrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to clear bits 3 to 7 to ?0?. 3. the oscillation stabilization ti me following reset release is 2 16 /f x (because the initial value of the osts register = 06h). remark f x = main clock oscillation frequency
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 678 of 870 sep 30, 2010 21.3 halt mode 21.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock o scillator continues operating. only clock supply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the internal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction proce ssing by the cpu continue operating. table 21-3 shows the operating status in the halt mode. the average current consumpt ion of the system can be reduced by usi ng the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed while an unmasked interrupt request signal is being held pending, the status shifts to halt mode, but the halt mode is then released immediately by the pending interrupt request. 21.3.2 releasing halt mode the halt mode is released by a non-maskable interrupt r equest signal (nmi pin input, intwdt2 signal), unmasked external interrupt reques t signal (intp0 to intp7 pin input), unmasked inte rnal interrupt request signal from a peripheral function operable in the halt mode, or reset signal (rese t by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-m askable interrupt request signal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priori ty of the interrupt request signal. if the halt mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the halt mode is released, bu t that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signa l), the halt mode is re leased and that interrupt request signal is acknowledged. table 21-2. operation after releasing ha lt mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address or the next instruction is executed. the next instruction is executed.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 679 of 870 sep 30, 2010 (2) releasing halt mode by reset the same operation as the normal reset operation is performed. table 21-3. operating status in halt mode setting of halt mode operating status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled internal oscillator oscillation enabled pll operable cpu stops operation dma operable interrupt controller operable timer p (tmp0 to tmp5) operable timer q (tmq0) operable timer m (tmm0) operable when a clock other than f xt is selected as the count clock operable watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable when a clock other than f xt is selected as the count clock operable csib0 to csib4 operable i 2 c00 to i 2 c02 operable serial interface uarta0 to uarta2 operable a/d converter operable d/a converter operable real-time output function (rto) operable key interrupt function (kr) operable crc operation circuit operable (no data input to the crcin register because the cpu is stopped) external bus interface see 2.2 pin states . port function retains status before halt mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 680 of 870 sep 30, 2010 21.4 idle1 mode 21.4.1 setting and operation status the idle1 mode is set by clearing the psmr.psm1 and psm r.psm0 bits to 00 and setting the psc.stp bit to 1 in the normal operation mode. in the idle1 mode, the clock oscillator , pll, and flash memory continue operating but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle1 mode was set are retained. the cpu and other on-chip peripheral func tions stop operating. however, the on-chip peripheral functions that can operate with the subclock or an exte rnal clock continue operating. table 21-5 shows the operating status in the idle1 mode. the idle1 mode can reduce the power consumption more t han the halt mode because it stops the operation of the on-chip peripheral functions. the main clock oscillator does not stop, so the normal operat ion mode can be restored without waiting for the oscillation stabilization time after t he idle1 mode has been released, in the same manner as when the halt mode is released. cautions 1. insert five or more nop in structions after the instruction that stores data in the psc register to set the idle1 mode. 2. if the idle1 mode is set while an unmasked in terrupt request signal is being held pending, the idle1 mode is released immediatel y by the pending interrupt request. 21.4.2 releasing idle1 mode the idle1 mode is released by a non-maskable interrupt r equest signal (nmi pin input, intwdt2 signal), unmasked external interrupt reques t signal (intp0 to intp7 pin input), unmasked inte rnal interrupt request signal from a peripheral function operable in the idle1 mode, or reset signal (rese t by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). after the idle1 mode has been released, the normal operation mode is restored. (1) releasing idle1 mode by non- maskable interrupt request signal or unmasked maskable interrupt request signal the idle1 mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle1 mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is processed as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the idle1 mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal ), the idle1 mode is rel eased and that interrupt request signal is acknowledged. caution an interrupt request signal that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and idle1 mode is not released.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 681 of 870 sep 30, 2010 table 21-4. operation after releasing id le1 mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address or the next instruction is executed. the next instruction is executed. (2) releasing idle1 mode by reset the same operation as the normal reset operation is performed. table 21-5. operating status in idle1 mode setting of idle1 mode operating status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled internal oscillator oscillation enabled pll operable cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable when f r is selected as the count clock operable when f r or f xt is selected as the count clock csib0 to csib4 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation serial interface uarta0 to uarta2 stops operation (but uarta0 is operable when the ascka0 input clock is selected) a/d converter holds operation (conversion result held) note d/a converter holds operation (output held note ) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see 2.2 pin states . port function retains status before idle1 mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle1 mode was set. note to realize low power consumption, stop the a/d converter and d/a converter before shifting to the idle1 mode.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 682 of 870 sep 30, 2010 21.5 idle2 mode 21.5.1 setting and operation status the idle2 mode is set by setting the psmr.psm1 and psmr.psm 0 bits to 10 and setting the psc.stp bit to 1 in the normal operation mode. in the idle2 mode, the clock oscillator continues operation but clock supply to the cpu, pll, flash memory, and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle2 mode was set are retained. the cpu, pll, and other on-chip peripheral functions stop operating. however, t he on-chip peripheral functions that can operate with the subclock or an exte rnal clock continue operating. table 21-7 shows the operating status in the idle2 mode. the idle2 mode can reduce the power cons umption more than the idle1 mode becaus e it stops the op erations of the on-chip peripheral functions, pll, and flash memory. howeve r, because the pll and flash memory are stopped, a setup time for the pll and flash memory is required when idle2 mode is released. cautions 1. insert five or more nop in structions after the instruction that stores data in the psc register to set the idle2 mode. 2. if the idle2 mode is set while an unmasked in terrupt request signal is being held pending, the idle2 mode is released immediatel y by the pending interrupt request. 21.5.2 releasing idle2 mode the idle2 mode is released by a non-maskable interrupt r equest signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the idle2 mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). the pll returns to the operating status it was in before the idle2 mode was set. after the idle2 mode has been released, the normal operation mode is restored. (1) releasing idle2 mode by non- maskable interrupt request signal or unmasked maskable interrupt request signal the idle2 mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle2 mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is processed as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the idle2 mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal ), the idle2 mode is re leased and that interrupt request signal is acknowledged. caution the interrupt request signal that is di sabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and idle2 mode is not released.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 683 of 870 sep 30, 2010 table 21-6. operation after releasing id le2 mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after securing the prescribed setup time. maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing the prescribed setup time. the next instruction is executed after securing the prescribed setup time. (2) releasing idle2 mode by reset the same operation as the normal reset operation is performed. table 21-7. operating status in idle2 mode setting of idle2 mode operating status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled internal oscillator oscillation enabled pll stops operation cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable when f r is selected as the count clock operable when f r or f xt is selected as the count clock csib0 to csib4 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation serial interface uarta0 to uarta2 stops operation (but uarta0 is operable when the ascka0 input clock is selected) a/d converter holds operation (conversion result held) note d/a converter holds operation (output held note ) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see 2.2 pin states . port function retains status before idle2 mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle2 mode was set. note to realize low power consumption, stop the a/d converter and d/a converter before shifting to the idle2 mode.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 684 of 870 sep 30, 2010 21.5.3 securing setup time when releasing idle2 mode secure the setup time for the flash me mory after releasing the idle2 mode bec ause the operation of the blocks other than the main clock oscillator stops after the idle2 mode is set. (1) releasing idle2 mode by non- maskable interrupt request signal or unmasked maskable interrupt request signal secure the specified setup time by setting the osts register. when the releasing source is generated, the dedicated internal timer starts counting according to the osts register setting. when it overflows, the normal operation mode is restored. oscillated waveform rom circuit stopped setup time count main clock idle mode status interrupt request (2) release by reset (reset pin input, wdt2r es generation) this operation is the same as that of a normal reset. the oscillation stabilization time is the initial value of the osts register, 2 16 /f x .
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 685 of 870 sep 30, 2010 21.6 stop mode 21.6.1 setting and operation status the stop mode is set by setting t he psmr.psm1 and psmr.psm0 bits to 01 or 11 and setting the psc.stp bit to 1 in the normal operation mode. in the stop mode, the subclock oscillato r continues operating but the main clo ck oscillator stops. clock supply to the cpu and the on-chip peripher al functions is stopped. as a result, program execution stops , and the contents of the internal ram before the stop mode was set are retained. the on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. table 21-9 shows the operating status in the stop mode. because the stop mode stops operation of the main clock oscillator, it reduc es the power consumption to a level lower than the idle2 mode. if the subclock oscillator, inte rnal oscillator, and external clock are not used, the power consumption can be minimized with only leakage current flowing. cautions 1. insert five or more nop in structions after the instruction that stores data in the psc register to set the stop mode. 2. if the stop mode is set while an unmasked interrupt request signal is being held pending, the stop mode is released immediatel y by the pending interrupt request. 21.6.2 releasing stop mode the stop mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the stop mode, or reset signal (r eset by reset pin input, wdt2res signal, or low-voltage detector (lvi)). after the stop mode has been released, the normal operati on mode is restored after the oscillation stabilization time has been secured. (1) releasing stop mode by non-m askable interrupt request signal or unmasked maskable interrupt request signal the stop mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priori ty of the interrupt request signal. if the stop mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the stop mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal ), the stop mode is rele ased and that interrupt request signal is acknowledged. caution the interrupt request that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and stop mode is not released.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 686 of 870 sep 30, 2010 table 21-8. operation after releasing st op mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after securing the oscillation stabilization time. maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing the oscillation stabilization time. the next instruction is executed after securing the oscillation stabilization time.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 687 of 870 sep 30, 2010 (2) releasing stop mode by reset the same operation as the normal reset operation is performed. table 21-9. operating status in stop mode setting of stop mode operating status item when subclock is not used when subclock is used main clock oscillator stops oscillation subclock oscillator ? oscillation enabled internal oscillator oscillation enabled pll stops operation cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer stops operation operable when f xt is selected as the count clock watchdog timer 2 operable when f r is selected as the count clock operable when f r or f xt is selected as the count clock csib0 to csib4 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation serial interface uarta0 to uarta2 stops operation (but uarta0 is operable when the ascka0 input clock is selected) a/d converter stops operation (conversion result undefined) notes 1, 2 d/a converter stops operation notes 3, 4 (high impedance is output) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see 2.2 pin states . port function retains status before stop mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the stop mode was set. notes 1. if the stop mode is set while the a/d converter is operating, the a/d converter is automatically stopped and starts operating again after the stop mode is released. however, in that case, the a/d conversion results after the stop mode is released are invalid. all the a/ d conversion results before the stop mode is set are invalid. 2. even if the stop mode is set while the a/d converte r is operating, the power consumption is reduced equivalently to when the a/d converter is stopped before the stop mode is set. 3. if the stop mode is set while the d/a converter is operating, the d/a converter is automatically stopped and the pin status becomes high impedanc e. after the stop mode is released, d/a conversion resumes, the setting time elapses, and the status returns to the output level before the stop mode was set. 4. even if the stop mode is set while the d/a conver ter is operating, the power consumption is reduced equivalently to when the d/a converter is stopped before the stop mode is set.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 688 of 870 sep 30, 2010 21.6.3 securing oscillation stabilizati on time when releasing stop mode secure the oscillation stabilization time for the main clo ck oscillator after releasing the stop mode because the operation of the main clock oscillator stops after stop mode is set. (1) releasing stop mode by non-m askable interrupt request signal or unmasked maskable interrupt request signal secure the oscillation stabilization time by setting the osts register. when the releasing source is generated, the dedicated internal timer starts counting according to the osts register setting. when it overflows, the normal operation mode is restored. oscillated waveform rom circuit stopped setup time count main clock stop status interrupt request (2) release by reset this operation is the same as that of a normal reset. the oscillation stabilization time is the initial value of the osts register, 2 16 /f x .
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 689 of 870 sep 30, 2010 21.7 subclock operation mode 21.7.1 setting and operation status the subclock operation mode is set by setting the pcc.ck3 bit to 1 in the normal operation mode. when the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. check whether the clock has been s witched by using the pcc.cls bit. when the pcc.mck bit is set to 1, the operation of the main clock oscillator is stopped. as a result, the system operates only on the subclock. in the subclock operation mode, the pow er consumption can be reduced to a le vel lower than in the normal operation mode because the subclock is used as the internal system clock. in addition , the power consumption can be further reduced to the level of the stop mode by stoppi ng the operation of the main clock oscillator. table 21-10 shows the operating st atus in subclock operation mode. cautions 1. when manipulating the ck3 bit, do not ch ange the set values of the pcc.ck2 to pcc.ck0 bits (using a bit manipulation instruction to manipulat e the bit is recommended). for details of the pcc register, see 6.3 (1) processor clock control register (pcc). 2. if the following conditions are not satisfied, ch ange the ck2 to ck0 bits so that the conditions are satisfied and set the subclock operation mode. internal system clock (f clk ) > subclock (f xt = 32.768 khz) 4 remark internal system clock (f clk ): clock generated from main clock (f xx ) in accordance with the settings of the ck2 to ck0 bits 21.7.2 releasing subc lock operation mode the subclock operation mode is released by a reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)) when the ck3 bit is cleared to 0. if the main clock is stopped (mck bit = 1), set the mck bit to 1, secure the oscillation st abilization time of the main clock by software, and clear the ck3 bit to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details of the pcc register, see 6.3 (1 ) processor clock control register (pcc).
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 690 of 870 sep 30, 2010 table 21-10. operating status in subclock operation mode operating status setting of subclock operation mode item when main clock is oscillating when main clock is stopped subclock oscillator oscillation enabled internal oscillator oscillation enabled pll operable stops operation note cpu operable dma operable interrupt controller operable timer p (tmp0 to tmp5) operable stops operation timer q (tmq0) operable stops operation timer m (tmm0) operable operable when f r /8 or f xt is selected as the count clock watch timer operable operable when f xt is selected as the count clock watchdog timer 2 operable operable when f r or f xt is selected as the count clock csib0 to csib4 operable operable when the sckbn input clock is selected as the count clock (n = 0 to 4) i 2 c00 to i 2 c02 operable stops operation serial interface uarta0 to uarta2 operable stops operation (but uarta0 is operable when the ascka0 input clock is selected) a/d converter operable stops operation d/a converter operable real-time output function (rto) oper able stops operation (output held) key interrupt function (kr) operable crc operation circuit operable external bus interface see 2.2 pin states . port function settable internal data settable note be sure to stop the pll (pllctl.pllon bi t = 0) before stopping the main clock. caution when the cpu is operating on the subclock and main clock oscillation is stopped, accessing a register in which a wait occurs is disabled. if a wait is generated, it can be released only by reset (see 3.4.8 (2)).
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 691 of 870 sep 30, 2010 21.8 sub-idle mode 21.8.1 setting and operation status the sub-idle mode is set by setting the psmr.psm1 and psmr.psm0 bits to 00 or 10 and setting the psc.stp bit to 1 in the subclock operation mode. in this mode, the clock oscillator continues operating but cl ock supply to the cpu, flash memory, and the other on-chip peripheral functions is stopped. as a result, program execution stops and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and the other on-chip pe ripheral functions are stopped. however, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. because the sub-idle mode stops operat ion of the cpu, flash memory, and other on-chip peripheral functions, it can reduce the power consumption more than the subclock operation mode. if the sub-idle mode is set after the main clock has been stopped, the current consumpt ion can be reduced to a level as low as that in the stop mode. table 21-12 shows the operating status in the sub-idle mode. cautions 1. following the store instruction to the psc register for setting the sub- idle mode, insert the five or more nop instructions. 2. if the sub-idle mode is set while an unmasked interrupt request signal is being held pending, the sub-idle mode is then released immedi ately by the pending interrupt request. 21.8.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable inte rrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the su b-idle mode, or reset signal (reset by reset pin input, wdt2res signal, low- voltage detector (lvi), or clock monitor (clm)). the pll re turns to the operating status it was in before the sub-idle mode was set. when the sub-idle mode is released by an interrupt request signal, the subclock operation mode is set. (1) releasing sub-idle mo de by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the sub-idle mode is released by a non-maskable inte rrupt request signal or an unmasked maskable interrupt request signal, regardless of the priori ty of the interrupt request signal. if the sub-idle mode is set in an interrupt servicing routi ne, however, an interrupt request signal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the sub-idle mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal ), the sub-idle mode is released and that interrupt request signal is acknowledged. cautions 1. the interrupt request signal that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and sub-idle mode is not released. 2. when the sub-idle mode is rele ased, 12 cycles of the subclock (about 366 s) elapse from when the interrupt request signa l that releases the sub-idle mo de is generated to when the mode is released.
v850es/jg3 chapter 21 standby function r01uh0015ej0300 rev.3.00 page 692 of 870 sep 30, 2010 table 21-11. operation after releasing sub- idle mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address or the next instruction is executed. the next instruction is executed. (2) releasing sub-idle mode by reset the same operation as the normal reset operation is performed. table 21-12. operating status in sub-idle mode setting of sub-idle mode operating status item when main clock is oscillating when main clock is stopped subclock oscillator oscillation enabled internal oscillator oscillation enabled pll operable stops operation note 1 cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release is possible) timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 or f xt is selected as the count clock watch timer stops operation operable when f xt is selected as the count clock watchdog timer 2 operable when f r or f xt is selected as the count clock csib0 to csib4 operable when the sckbn input cloc k is selected as the count clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation serial interface uarta0 to uarta2 stops operation (but uarta0 is operable when the ascka0 input clock is selected) a/d converter holds operation (conversion result held) note 2 d/a converter holds operation (output held note 2 ) real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see 2.2 pin states (same operation status as idle1, idle2 mode). port function retains status before sub-idle mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the sub-idle mode was set. notes 1. be sure to stop the pll (pllctl.pllon bi t = 0) before stopping the main clock. 2. to realize low power consumption, stop the a/d and d/a converters before shifting to the sub-idle mode.
v850es/jg3 chapter 22 reset functions r01uh0015ej0300 rev.3.00 page 693 of 870 sep 30, 2010 chapter 22 reset functions 22.1 overview the following reset functions are available. (1) four kinds of reset sources ? external reset input via the reset pin ? reset via the watchdog timer 2 (wdt2) overflow (wdt2res) ? system reset via the comparison of the low-volt age detector (lvi) supply voltage and detected voltage ? system reset via the detecting clock monitor (clm) oscillation stop after a reset is released, the source of the reset can be confirmed with the reset source flag register (resf). (2) emergency operation mode if the wdt2 overflows during the main clock oscillati on stabilization time inserted after reset, a main clock oscillation anomaly is judged and the cpu starts operating on the internal oscillation clock. caution in emergency operation mode , do not access on-chip peripheral i/o registers other than registers used for interrupts, port function, wdt2, or timer m, each of wh ich can operate with the internal oscillation clock. in additi on, operation of csib0 to csib 4 and uarta0 using the externally input clock is also prohibited in this mode. figure 22-1. block di agram of reset function clmrf lvirf wdt2rf reset source flag register (resf) internal bus wdt2 reset signal clm reset signal reset lvi reset signal reset signal reset signal reset signal to lvim/lvis register clear set set clear clear set caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register
v850es/jg3 chapter 22 reset functions r01uh0015ej0300 rev.3.00 page 694 of 870 sep 30, 2010 22.2 registers to check reset source the v850es/jg3 has four kinds of rese t sources. after a reset has been rele ased, the source of the reset that occurred can be checked with the reset source flag register (resf). (1) reset source flag register (resf) the resf register is a special regist er that can be written only by a co mbination of specific sequences (see 3.4.7 special registers ). the resf register indicates the source from which a reset signal is generated. this register is read or written in 8-bit or 1-bit units. reset pin input clears this register to 00h. the default value differs if the source of reset is other than the reset pin signal. 0 wdt2rf 0 1 not generated generated resf 0 0 wdt2rf 0 0 clmrf lvirf after reset: 00h note r/w address: fffff888h reset signal from wdt2 lvirf 0 1 not generated generated reset signal from lvi clmrf 0 1 not generated generated reset signal from clm note the value of the resf register is cleared to 00h when a reset is executed via the reset pin. when a reset is executed by the watchdog timer 2 (wdt2), lo w-voltage detector (lvi), or clock monitor (clm), the reset flags of this register (wdt2rf bit, clmrf bi t, and lvirf bit) are set. however, other sources are retained. caution only ?0? can be written to each bit of this register. if writing ?0? conflicts with setting the flag (occurrence of reset), setting the flag takes precedence.
v850es/jg3 chapter 22 reset functions r01uh0015ej0300 rev.3.00 page 695 of 870 sep 30, 2010 22.3 operation 22.3.1 reset operation via reset pin when a low level is input to the reset pin, the syst em is reset, and each hardware unit is initialized. when the level of the reset pin is changed from low to high, the reset status is released. table 22-1. hardware status on reset pin input item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues internal oscillator oscillation stops oscillation starts peripheral clock (f x to f x /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f clk ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to fxx/8) cpu initialized program execution starts after securing oscillation stabilization time watchdog timer 2 operation stops (initialized to 0) counts up from 0 with internal oscillation clock as source clock. internal ram undefined if power-on reset or cpu acce ss and reset input conflict (data is damaged). otherwise value imm ediately after reset input is retained. i/o lines (ports/alternate-function pins) high impedance note on-chip peripheral i/o registers initialized to sp ecified status, ocdm register is set (01h). other on-chip peripheral functions operation st ops operation can be started after securing oscillation stabilization time note when the power is turned on, the following pin may output an undefined level temporarily, even during reset. ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin caution the ocdm register is initialized by the reset pin input. therefore, note with caution that, if a high level is input to the p05/drst pin after a reset release before the ocdm.o cdm0 bit is cleared, the on- chip debug mode is entered. for de tails, see chapter 4 port functions.
v850es/jg3 chapter 22 reset functions r01uh0015ej0300 rev.3.00 page 696 of 870 sep 30, 2010 figure 22-2. timing of reset operation by reset pin input counting of oscillation stabilization time initialized to f xx /8 operation oscillation stabilization timer overflows internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay figure 22-3. timing of power-on reset operation oscillation stabilization time count must be on-chip regulator stabilization time (1 ms (max.)) or longer. initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal reset f x v dd f clk analog delay
v850es/jg3 chapter 22 reset functions r01uh0015ej0300 rev.3.00 page 697 of 870 sep 30, 2010 22.3.2 reset operation by watchdog timer 2 when watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (wdt2res signal generation), a system reset is executed and the hardware is initialized to the initial status. following watchdog timer 2 overflow, the reset status is en tered and lasts the predetermined time (analog delay), and the reset status is then aut omatically released. the main clock oscillator is stopped during the reset period. table 22-2. hardware status during watchdog timer 2 reset operation item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues internal oscillator oscillation stops oscillation starts peripheral clock (f xx to f xx /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to fxx/8) cpu initialized program execution after securing oscillation stabilization time watchdog timer 2 operation stops (initialized to 0) counts up from 0 with internal oscillation clock as source clock. internal ram undefined if power-on reset or cpu ac cess and reset input conflict (data is damaged). otherwise value imm ediately after reset input is retained. i/o lines (ports/alternate-function pins) high impedance on-chip peripheral i/o register initialized to spec ified status, ocdm register retains its value. on-chip peripheral functions other than above operation stops operation can be started after securing oscillation stabilization time.
v850es/jg3 chapter 22 reset functions r01uh0015ej0300 rev.3.00 page 698 of 870 sep 30, 2010 figure 22-4. timing of reset oper ation by wdt2res signal generation counting of oscillation stabilization time initialized to f xx /8 operation oscillation stabilization timer overflow internal system reset signal wdt2res f x f clk analog delay
v850es/jg3 chapter 22 reset functions r01uh0015ej0300 rev.3.00 page 699 of 870 sep 30, 2010 22.3.3 reset operation by low-voltage detector if the supply voltage falls below the vo ltage detected by the low- voltage detector when lvi operation is enabled, a system reset is executed (when the lvim.lvimd bit is set to 1), and the hardware is initia lized to the initial status. the reset status lasts from when a s upply voltage drop has been detected until t he supply voltage rises above the lvi detection voltage. the main clock oscillator is stopped during the reset period. when the lvimd bit = 0, an interrupt request signal (i ntlvi) is generated if a low voltage is detected. table 22-3. hardware status during reset operation by low-voltage detector item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues internal oscillator oscillation stops oscillation starts peripheral clock (f x to f x /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu initialized program execution starts after securing oscillation stabilization time wdt2 operation stops (initialized to 0) counts up from 0 with internal oscillation clock as source clock. internal ram undefined if power-on reset or cpu ac cess and reset input conflict (data is damaged). otherwise value imm ediately after reset input is retained. i/o lines (ports/alternate-function pins) high impedance on-chip peripheral i/o register initialized to spec ified status, ocdm register retains its value. lvi operation continues on-chip peripheral functions other than above operation stops operation can be started after securing oscillation stabilization time. remark for the reset timing of the low-voltage detector, see chapter 24 low-voltage detector (lvi) .
v850es/jg3 chapter 22 reset functions r01uh0015ej0300 rev.3.00 page 700 of 870 sep 30, 2010 22.3.4 operation after reset release after the reset is released, the main clock starts oscillatio n and oscillation stabilization time (osts register initial value: 2 16 /f x ) is secured, and the cpu st arts program execution. wdt2 immediately begins to operate after a reset has been released using the internal oscillation clock as a source clock. figure 22-5. operation after reset release main clock reset counting of oscillation stabilization time normal operation (f cpu = main clock) operation stops operation in progress operation stops operation in progress clock monitor internal oscillation clock v850es/jg3 wdt2 (1) emergent operation mode if an anomaly occurs in the main clock before oscillation stabilization time is secured, wdt2 overflows before executing the cpu program. at this ti me, the cpu starts program execution by using the internal oscillation clock as the source clock. figure 22-6. operation after reset release main clock reset counting of oscillation stabilization time wdt overflows emergency mode (f cpu = internal oscillation clock) operation stops operation in progress operation in progress (re-count) operation stops clock monitor internal oscillation clock v850es/jg3 wdt2 the cpu operation clock states c an be checked with the cpu operation clock status register (ccls).
v850es/jg3 chapter 22 reset functions r01uh0015ej0300 rev.3.00 page 701 of 870 sep 30, 2010 22.3.5 reset function operation flow start (reset source occurs) main clock oscillation stabilization time secured? no ccls.cclsf bit = 1? yes no (in normal operation mode) no (in emergent operation mode) reset source generated? yes no yes (in normal operation mode) wdt2 overflow? no yes (in emergent operation mode) set resf register note 1 reset occurs reset release emergent operation software processing normal operation cpu operation starts from reset address (f cpu = f x /8, f r ) f cpu = f x f cpu = f r note 2 ccls.cclsf bit 1 wdt2 restart internal oscillation and main clock oscillation start, wdt2 count up starts (reset mode) notes 1. bit to be set differs depending on the reset source. reset source wdt2rf bit crmrf bit lvirf bit reset pin 0 0 0 wdt2 1 value before reset is retained. value before reset is retained. clm value before reset is retained. 1 value before reset is retained. lvi value before reset is retained. value before reset is retained. 1 2. the internal oscillator cannot be stopped.
v850es/jg3 chapter 23 clock monitor r01uh0015ej0300 rev.3.00 page 702 of 870 sep 30, 2010 chapter 23 clock monitor 23.1 functions the clock monitor samples the main clock by using the inte rnal oscillation clock and generates a reset request signal when oscillation of the main clock is stopped. once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset. when a reset by the clock monitor occurs, the resf.clmrf bit is set. for details on the resf register, see 22.2 registers to check reset source . the clock monitor automatically stops under the following conditions. ? during oscillation stabilization time after stop mode is released ? when the main clock is stopped (from when the pcc.mck bi t = 1 during subclock operation, until the pcc.cls bit = 0 during main clock operation) ? when the sampling clock (internal oscillation clock) is stopped ? when the cpu operates with the internal oscillation clock 23.2 configuration the clock monitor includes the following hardware. table 23-1. configuration of clock monitor item configuration control register clock monitor mode register (clm) figure 23-1. timing of reset via the reset pin input main clock internal oscillation clock internal reset signal enable/disable clme clock monitor mode register (clm)
v850es/jg3 chapter 23 clock monitor r01uh0015ej0300 rev.3.00 page 703 of 870 sep 30, 2010 23.3 register the clock monitor is controlled by the clock monitor mode register (clm). (1) clock monitor mode register (clm) the clm register is a special regist er. this can be written only in a special combination of sequences (see 3.4.7 special registers ). this register is used to set the operation mode of the clock monitor. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: fffff870h 7 6 5 4 3 2 1 <0> clm 0 0 0 0 0 0 0 clme clme clock monitor operation enable or disable 0 disable clock monitor operation. 1 enable clock monitor operation. cautions 1. once the clme bit h as been set to 1, it cannot be cleared to 0 by any means other than reset. 2. when a reset by the clock monitor occu rs, the clme bit is cleared to 0 and the resf.clmrf bit is set to 1.
v850es/jg3 chapter 23 clock monitor r01uh0015ej0300 rev.3.00 page 704 of 870 sep 30, 2010 23.4 operation this section explains the functions of the clock m onitor. the start and stop conditions are as follows. enabling operation by setting the clm.clme bit to 1 ? while oscillation stabilization time is being counted after stop mode is released ? when the main clock is stopped (from when pcc.mck bit = 1 during subclock operation to when pcc.cls bit = 0 during main clock operation) ? when the sampling clock (internal oscillation clock) is stopped ? when the cpu operates using the internal oscillation clock table 23-2. operation status of clock monitor (when clm.clme bit = 1, during inte rnal oscillation clock operation) cpu operating clock operation mode status of main clock status of internal oscillation clock status of clock monitor halt mode oscillates oscillates note 1 operates note 2 idle1, idle2 modes oscillates oscillates note 1 operates note 2 main clock stop mode stops oscillates note 1 stops subclock (mck bit of pcc register = 0) sub-idle mode oscillates oscillates note 1 operates note 2 subclock (mck bit of pcc register = 1) sub-idle mode stops oscillates note 1 stops internal oscillation clock ? stops oscillates note 3 stops during reset ? stops stops stops notes 1. the internal oscillator can be stopped by setting the rcm.rstop bit to 1. 2. the clock monitor is stopped while t he internal oscillator is stopped. 3. the internal oscillator cannot be stopped by software.
v850es/jg3 chapter 23 clock monitor r01uh0015ej0300 rev.3.00 page 705 of 870 sep 30, 2010 (1) operation when main clock osc illation is stopped (clme bit = 1) if oscillation of the main clock is stopped when the clme bi t = 1, an internal reset signal is generated as shown in figure 23-2. figure 23-2. reset period due to that oscillation of main clock is stopped four internal oscillation clocks main clock internal oscillation clock internal reset signal clm.clme bit resf.clmrf bit (2) clock monitor status after reset input reset input clears the clm.clme bit to 0 and stops the cl ock monitor operation. when clme bit is set to 1 by software at the end of the oscillati on stabilization time of the main clock, monitoring is started. figure 23-3. clock monitor status after reset input (clm.clme bit = 1 is set after reset input and at the end of main clock oscillation stabilization time) cpu operation clock monitor status clme reset internal oscillation clock main clock reset oscillation stabilization time normal operation clock supply stopped normal operation monitoring monitoring stopped monitoring set to 1 by software
v850es/jg3 chapter 23 clock monitor r01uh0015ej0300 rev.3.00 page 706 of 870 sep 30, 2010 (3) operation in stop mode or after stop mode is released if the stop mode is set with the clm.cl me bit = 1, the monitor operation is stopped in the stop mode and while the oscillation stabilization time is bei ng counted. after the oscillation stabilization time, the monitor operation is automatically started. figure 23-4. operation in stop mode or after stop mode is released clock monitor status during monitor monitor stops during monitor clme internal oscillation clock main clock cpu operation normal operation stop oscillation stabilization time normal operation oscillation stops oscillation stabilization time (set by osts register) (4) operation when main clock is stopped (arbitrary) during subclock operation (pcc.cls bit = 1) or when the main clock is stopped by setting the pcc.mck bit to 1, the monitor operation is stopped until the main clock operat ion is started (pcc.cls bit = 0). the monitor operation is automatically started when the ma in clock operation is started. figure 23-5. operation when main clock is stopped (arbitrary) clock monitor status during monitor monitor stops monitor stops during monitor clme internal oscillation clock main clock cpu operation oscillation stops subclock operation main clock operation oscillation stabilization time (set by osts register) oscillation stabilization time count by software pcc.mck bit = 1 (5) operation while cpu is operating on inte rnal oscillation clock (ccls.cclsf bit = 1) the monitor operation is not stopped when the cclsf bi t is 1, even if the clme bit is set to 1.
v850es/jg3 chapter 24 low-voltage detector (lvi) r01uh0015ej0300 rev.3.00 page 707 of 870 sep 30, 2010 chapter 24 low-voltage detector (lvi) 24.1 functions the low-voltage detector (lvi) has the following functions. ? if the interrupt occurrence at low voltage detection is se lected, the low-voltage detecto r continuously compares the supply voltage (v dd ) and the detected voltage (v lvi ), and generates an internal interrupt signal when the supply voltage drops or rises ac ross the detected voltage. ? if the reset occurrence at low voltage detection is sele cted, the low-voltage detector generates an interrupt reset signal when the supply voltage (v dd ) drops across the detected voltage (v lvi ). ? interrupt or reset signal c an be selected by software. ? can operate in stop mode. if the low-voltage detector is used to generate a reset signal, the resf.lvirf bit is set to 1 when the reset signal is generated. for details of resf register, see 22.2 registers to check reset source . 24.2 configuration the block diagram of the low-vo ltage detector is shown below. figure 24-1. block diagram of low-voltage detector lvis0 lvion detected voltage source (v lvi ) v dd v dd intlvi internal bus n-ch low-voltage detection level select register (lvis) low-voltage detection register (lvim) lvimd lvif internal reset signal selector low- voltage detection level selector ? +
v850es/jg3 chapter 24 low-voltage detector (lvi) r01uh0015ej0300 rev.3.00 page 708 of 870 sep 30, 2010 24.3 registers the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level select register (lvis) ? internal ram data status register (rams) (1) low-voltage detection register (lvim) the lvim register is a special register . this can be written only in the spec ial combination of the sequences (see 3.4.7 special registers ). the lvim register is used to enable or disable low-volt age detection, and to set the operation mode of the low- voltage detector. this register can be read or written in 8-bit or 1- bit units. however, the lvif bit is read-only. after reset: note 1 r/w address: fffff890h <7> 6 5 4 3 2 <1> <0> lvim lvion 0 0 0 0 0 lvimd lvif lvion low-voltage detection operation enable or disable 0 disable operation. 1 enable operation. lvimd selection of operation mode of low-voltage detection 0 generates interrupt request signal intlvi when the supply voltage drops or rises across the detection voltage value. 1 generate internal reset signal lvires when the supply voltage drops across the detected voltage value. lv i f note 2 low-voltage detection flag 0 when supply voltage > detected voltage, or when operation is disabled 1 supply voltage of connected power supply < detected voltage notes 1. reset by low-voltage detection: 82h reset due to other source: 00h 2. after the lvi operation has started (lvion bi t = 1) or when intlvi has occurred, confirm the supply voltage state using the lvif bit. cautions 1. when the lvion and lvimd bits to 1, the low-voltage detector cannot be stopped until the reset request due to other than th e low-voltage detection is generated. 2. when the lvion bit is set to 1, the comparator in the lvi circuit starts operating. wait 0.2 ms or longer by software before checking the voltage at the lvif bit after the lvion bit is set. 3. be sure to clear bits 6 to 2 to ?0?.
v850es/jg3 chapter 24 low-voltage detector (lvi) r01uh0015ej0300 rev.3.00 page 709 of 870 sep 30, 2010 (2) low-voltage detection level select register (lvis) the lvis register is used to select t he level of low voltage to be detected. this register can be read or written in 8-bit or 1-bit units. after reset: note r/w address: fffff891h 7 6 5 4 3 2 1 0 lvis 0 0 0 0 0 0 0 lvis0 lvis0 detection level 0 2.95 v (typ.) 0.10 v 1 reserved (setting prohibited) note reset by low-voltage detection: retained reset due to other source: 00h cautions 1. this register cannot be written until a reset request due to something other than low-voltage detection is generated after the lvim.lvion and lvim.lvimd bits are set to 1. 2. be sure to clear bits 7 to 1 to ?0?. (3) internal ram data status register (rams) the rams register is a special regi ster. this can be written only in a special combination of sequences (see 3.4.7 special registers ). this register is a flag register that indica tes whether the internal ram is valid or not. this register can be read or written in 8-bit or 1-bit units. the set/clear conditions for the ramf bit are shown below. ? setting conditions: detection of voltage lower than specified level set by instruction ? clearing condition: writing of 0 in specific sequence after reset: 01h note r/w address: fffff892h 7 6 5 4 3 2 1 <0> rams 0 0 0 0 0 0 0 ramf ramf internal ram voltage detection 0 voltage lower than ram retention voltage is not detected. 1 voltage lower than ram retention voltage is detected. note this register is reset only when a voltage dr op below the ram retention voltage is detected.
v850es/jg3 chapter 24 low-voltage detector (lvi) r01uh0015ej0300 rev.3.00 page 710 of 870 sep 30, 2010 24.4 operation depending on the setting of the lvim.vimd bit, an interrupt si gnal (intlvi) or an internal reset signal is generated. how to specify each operation is described below, together with timing charts. 24.4.1 to use for inte rnal reset signal <1> mask the interrupt of lvi. <2> select the voltage to be detected by using the lvis.lvis0 bit. <3> set the lvim.lvion bit to 1 (to enable operation). <4> insert a wait cycle of 0.2 ms (max.) or more by software. <5> by using the lvim.lvif bit, check if the supply voltage > detected voltage. <6> set the lvimd bit to 1 (to generate an internal reset signal). caution if the lvimd bit is set to 1, the contents of the lvim and lvis registers cannot be changed until a reset request other than lvi is generated. figure 24-2. operation timing of low- voltage detector (lvimd bit = 1) supply voltage (v dd ) lvi detected voltage (2.95 v (typ.)) lvion bit lvi detected signal internal reset signal (active low) lvi reset request signal delay clear delay time
v850es/jg3 chapter 24 low-voltage detector (lvi) r01uh0015ej0300 rev.3.00 page 711 of 870 sep 30, 2010 24.4.2 to use for interrupt <1> mask the interrupt of lvi. <2> select the voltage to be detected by using the lvis.lvis0 bit. <3> set the lvim.lvion bit to 1 (to enable operation). <4> insert a wait cycle of 0.2 ms (max.) or more by software. <5> by using the lvim.lvif bit, check if the supply voltage > detected voltage. <6> clear the interrupt request flag of lvi. <7> unmask the interrupt of lvi. clear the lvion bit to 0. figure 24-3. operation timing of low- voltage detector (lvimd bit = 0) external reset ic detected voltage reset pin intlvi signal supply voltage (v dd ) lvi detected voltage (2.95 v (typ.)) lvion bit lvi detected signal internal reset signal (active low) delay clear delay time delay note note since the lvion bit is the initial value (operation disabled) due to the external reset input, no intlvi interrupts occur. caution when the intlvi signal is ge nerated, confirm, using the lvim/lvif bit, whether the intlvi signal is generated due to a supply voltage dr op or rise across the detected voltage.
v850es/jg3 chapter 24 low-voltage detector (lvi) r01uh0015ej0300 rev.3.00 page 712 of 870 sep 30, 2010 24.5 ram retention voltage detection operation the supply voltage and detected voltage are compared. when the supply volt age drops below the detected voltage (including on power application), the rams.ramf bit is set to 1. figure 24-4. operation timing of ram retention voltage detection function supply voltage (v dd ) 2.0 v (minimum ram retention voltage) reset pin rams.ramf bit initialize ram (ramf bit is also cleared) when power application, ramf bit is set ram data is not retained ramf bit = 0 is retained regardless of reset pin if v dd > 2.0 v initialize ram (ramf bit is also cleared) v dd < 2.0 v detected set ramf bit ram data is not retained remarks 1. the ramf bit is set to 1 if the supply volt age drops under the minimum ram retention voltage (2.0 v (typ.)). 2. the ramf bit operates regardl ess of the reset pin status.
v850es/jg3 chapter 24 low-voltage detector (lvi) r01uh0015ej0300 rev.3.00 page 713 of 870 sep 30, 2010 24.6 emulation function when an in-circuit emulator is used, the operation of the ram retention flag (rams.ramf bit) can be pseudo- controlled and emulated by manipulating the pemu1 register on the debugger. this register is valid only in the emulation mode. it is invalid in the normal mode. (1) peripheral emulation register 1 (pemu1) after reset: 00h r/w address: fffff9feh 7 6 5 4 3 2 1 0 pemu1 0 0 0 0 0 evaramin 0 0 evaramin pseudo specification of ram retention voltage detection signal 0 do not detect voltage lower than ram retention voltage. 1 detect voltage lower than ram retention voltage (set ramf flag). caution this bit is not automatically cleared. [usage] when an in-circuit emulator is used, pseu do emulation of ramf is realized by rewriting this register on the debugger. <1> cpu break (cpu operation stops.) <2> set the evaramin bit to 1 by using a register write command. by setting the evaramin bit to 1, the ramf bit is se t to 1 on hardware (the internal ram data is invalid). <3> clear the evaramin bit to 0 by using a register write command again. unless this operation is performed (clearing the evaram in bit to 0), the ramf bit cannot be cleared to 0 by a cpu operation instruction. <4> run the cpu and resume emulation.
v850es/jg3 chapter 25 crc function r01uh0015ej0300 rev.3.00 page 714 of 870 sep 30, 2010 chapter 25 crc function 25.1 functions ? crc operation circuit for detection of data block errors ? generation of 16-bit crc code using a crc-ccitt (x 16 + x 12 + x 5 + 1) generation polynomial for blocks of data of any length in 8-bit units ? crc code is set to the crc data register each time 1-byte data is transferred to the crci n register, after the initial value is set to the crcd register. 25.2 configuration the crc function includes the following hardware. table 25-1. crc configuration item configuration control registers crc input register (crcin) crc data register (crcd) figure 25-1. block diagram of crc register crc data register (crcd) (16 bits) crc input register (crcin) (8 bits) internal bus internal bus crc code generator
v850es/jg3 chapter 25 crc function r01uh0015ej0300 rev.3.00 page 715 of 870 sep 30, 2010 25.3 registers (1) crc input register (crcin) the crcin register is an 8-bit register for setting data. this register can be read or written in 8-bit units. reset sets this register to 00h. crcin 654321 after reset: 00h r/w address: fffff310h 7 0 (2) crc data register (crcd) the crcd register is a 16-bit register that stores the crc-ccitt operation results. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the crcd register is pr ohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock crcd 12 10 8 6 4 2 after reset: 0000h r/w address: fffff312h 14 0 13 11 9 7 5 3 15 1
v850es/jg3 chapter 25 crc function r01uh0015ej0300 rev.3.00 page 716 of 870 sep 30, 2010 25.4 operation an example of the crc operation circuit is shown below. figure 25-2. crc operation circui t operation example (lsb first) (1) setting of crcin = 01h 1189h b15 b0 b0 b7 crc code is stored (2) crcd register read the code when 01h is sent lsb first is (1000 0000). therefore, the crc code from generation polynomial x 16 + x 12 + x 5 + 1 becomes the remainder when (1000 0000) x 16 is divided by (1 0001 0000 0010 0001) using the modulo-2 operation formula. the modulo-2 operation is performed based on the following formula. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 ? 1 = 1 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb lsb msb msb therefore, the crc code becomes . since lsb first is used, this corresponds to 1189h in hexadecimal notation. 1001 9811 0001 1000 1000
v850es/jg3 chapter 25 crc function r01uh0015ej0300 rev.3.00 page 717 of 870 sep 30, 2010 25.5 usage method how to use the crc logic circuit is described below. figure 25-3. crc operation flow start write of 0000h to crcd register crcd register read crcin register write yes no input data exists? end [basic usage method] <1> write 0000h to the crcd register. <2> write the required quantity of data to the crcin register. <3> read the crcd register.
v850es/jg3 chapter 25 crc function r01uh0015ej0300 rev.3.00 page 718 of 870 sep 30, 2010 communication errors can easily be detected if the c rc code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. the following is an illustration using the transmission of 12345678h (0001 0010 0011 0100 0101 0110 0111 1000b) lsb-first as an example. figure 25-4. crc transmission example 78 transmit/receive data (12345678h) crc code (08f6h) 56 34 12 f6 08 setting procedure on transmitting side <1> write the initial value 0000h to the crcd register. <2> write the 1 byte of data to be transmitted first to the tr ansmit buffer register. (at this time, also write the same data to the crcin register.) <3> when transmitting several bytes of data, write the same data to the crcin register each time transmit data is written to the transmit buffer register. <4> after all the data has been transmitted, write the co ntents of the crcd register (crc code) to the transmit buffer register and transmit them. (since this is lsb fi rst, transmit the data starting fr om the lower bytes, then the higher bytes.) setting procedure on receiving side <1> write the initial value 0000h to the crcd register. <2> when reception of the first 1 byte of data is comp lete, write that receive data to the crcin register. <3> if receiving several bytes of data, write the receive da ta to the crcin register upon every reception completion. (in the case of normal reception, when all the receive data has been written to the crcin register, the contents of the crcd register on the receiving side and the contents of the crcd register on the transmitting side are the same.) <4> next, the crc code is transmitted from the transmitting si de, so write this data to the crcin register similarly to receive data. <5> when reception of all the data, including the crc code, has been completed, reception was normal if the contents of the crcd register are 0000h. if the content s of the crcd register ar e other than 0000h, this indicates a communication error, so transmit a resend request to the transmitting side.
v850es/jg3 chapter 26 regulator r01uh0015ej0300 rev.3.00 page 719 of 870 sep 30, 2010 chapter 26 regulator 26.1 overview the v850es/jg3 includes a regulator to reduce power consumption and noise. this regulator supplies a stepped-down v dd power supply voltage to the oscillator block and internal logic circuits (except the a/d converter, d/a converte r, and output buffers). the regulator output voltage is set to 2.5 v (typ.). figure 26-1. regulator ev dd av ref0 av ref1 flmd0 v dd ev dd regc bidirectional level shifter ev dd i/o buffer regulator a/d converter d/a converter flash memory main oscillator internal digital circuits 2.5 v (typ.) sub-oscillator caution use the regulator with a setting of v dd = ev dd = av ref0 = av ref1 .
v850es/jg3 chapter 26 regulator r01uh0015ej0300 rev.3.00 page 720 of 870 sep 30, 2010 26.2 operation the regulator of this product always o perates in any mode (normal operation mode, halt mode, idle1 mode, idle2 mode, stop mode, or during reset). be sure to connect a capacitor (4.7 f (recommended value)) to the regc pin to stabilize the regulator output. a diagram of the regulator pin connection method is shown below. figure 26-2. regc pin connection reg v dd v ss regc voltage supply to sub-oscillator input voltage = 2.85 to 3.6 v voltage supply to main oscillator/internal logic = 2.5 v (typ.) 4.7 f (recommended value)
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 721 of 870 sep 30, 2010 chapter 27 flash memory the v850es/jg3 incorporates a flash memory. ? pd70f3739: 384 kb flash memory ? pd70f3740: 512 kb flash memory ? pd70f3741: 768 kb flash memory ? pd70f3742: 1024 kb flash memory flash memory versions offer the following advantages for development environments and mass production applications. for altering software after the v850es/jg3 is soldered onto the target system. for data adjustment when starting mass production. for differentiating software according to the specif ication in small scale production of various models. for facilitating inventory management. for updating software after shipment. 27.1 features 4-byte/1-clock access (when instruction is fetched) capacity: 1024 kb/768 kb/512 kb/384 kb write voltage: erase/write with a single power supply rewriting method ? rewriting by communication with dedicated flash pr ogrammer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) flash memory write prohibit f unction supported (security function) safe rewriting of entire flash memory area by self programming using boot swap function interrupts can be acknowledged during self programming.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 722 of 870 sep 30, 2010 27.2 memory configuration the v850es/jg3 internal flash memory area is divided into 4 kb blocks and can be programmed/erased in block units. all or some of the blocks can also be erased at once. when the boot swap function is used, the physical memory allo cated at the addresses of bl ocks 0 to 15 is replaced by the physical memory allocated at the addresses of blocks 16 to 31. for details of the boot swap function, see 27.5 rewriting by self programming .
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 723 of 870 sep 30, 2010 figure 27-1. flash memory mapping pd70f3742 (1024 kb) block 0 (4 kb) block 1 (4 kb) : block 15 (4 kb) block 16 (4 kb) block 17 (4 kb) : block 31 (4 kb) block 32 (4 kb) block 63 (4 kb) block 64 (4 kb) : : block 95 (4 kb) : : : : block 255 (4 kb) pd70f3741 (768 kb) block 0 (4 kb) block 1 (4 kb) block 15 (4 kb) block 16 (4 kb) block 17 (4 kb) block 31 (4 kb) block 32 (4 kb) block 63 (4 kb) block 64 (4 kb) : block 127 (4 kb) block 128 (4 kb) : block 159 (4 kb) block 160 (4 kb) : block 191 (4 kb) block 95 (4 kb) block 96 (4 kb) block 96 (4 kb) block 159 (4 kb) block 160 (4 kb) block 191 (4 kb) block 192 (4 kb) note 2 note 1 block 127 (4 kb) block 128 (4 kb) : : : : : : : : pd70f3740 (512 kb) block 0 (4 kb) block 1 (4 kb) block 15 (4 kb) block 16 (4 kb) block 17 (4 kb) block 31 (4 kb) block 32 (4 kb) block 63 (4 kb) block 64 (4 kb) : block 127 (4 kb) block 95 (4 kb) block 96 (4 kb) : : : : pd70f3739 (384 kb) block 0 (4 kb) block 1 (4 kb) block 15 (4 kb) block 16 (4 kb) block 17 (4 kb) block 31 (4 kb) block 32 (4 kb) block 63 (4 kb) block 64 (4 kb) block 95 (4 kb) 000fffffh 000ff000h 000fefffh 000c1000h 000c0fffh 000c0000h 000bffffh 000bf000h 000befffh 000a1000h 000a0fffh 000a0000h 0009ffffh 0009f000h 0009efffh 00081000h 00080fffh 00080000h 0007ffffh 0007f000h 0007efffh 00061000h 00060fffh 00060000h 0005ffffh 0005f000h 0005efffh 00041000h 00040fffh 00040000h 0003ffffh 0003f000h 0003efffh 00021000h 00020fffh 00020000h 0001ffffh 0001f000h 0001efffh 00012000h 00011fffh 00011000h 00010fffh 00010000h 0000ffffh 0000f000h 0000efffh 00002000h 00001fffh 00001000h 00000fffh 00000000h notes 1. area to be replaced with the boot area by the boot swap function 2. boot area
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 724 of 870 sep 30, 2010 27.3 functional outline the internal flash memory of the v850es/jg3 can be rewri tten by using the rewrite func tion of the dedicated flash programmer, regardless of whether the v850es/jg3 has already been mounted on the target system or not (off-board/on- board programming). in addition, a security function that prohibits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. the rewrite function using the user program (self programming) is ideal for an application w here it is assumed that the program is changed after production/shipment of the target syst em. a boot swap function that rewrites the entire flash memory area safely is also supported. in addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten under various conditions, such as while communicating with an external device. table 27-1. rewrite method rewrite method functional outline operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of off-board/on- board programming. (during self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. therefore, the rewrite program must be transferred to the internal ram or external memory in advance.) normal operation mode remark the fa series is a product of naito densei machida mfg. co., ltd.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 725 of 870 sep 30, 2010 table 27-2. basic functions support ( : supported, : not supported) function functional outline on-board/off-board programming self programming blank check the erasure status of the entire memory is checked. chip erasure the contents of the entire memory area are erased all at once. note block erasure the contents of specified memory blocks are erased. program writing to specified addresses, and a verify check to see if write level is secured are performed. verify/checksum data read from the flash memory is compared with data transferred from the flash memory programmer. (can be read by user program) read data written to the flash memory is read. security setting use of the chip erase command, block erase command, program command, and read command can be prohibited, and rewriting of the boot block cluster can be prohibited. (supported only when setting is changed from enable to disable) note this is possible by selecting the entire memory area for the block erase function. the following table lists the security functions. the ch ip erase command prohibit, block erase command prohibit, program command prohibit, read command prohibit, and rewriting boot block cluster prohibit functions are enabled by default after shipment, and security can be set by rewriting via on-board/off-board programming. each security function can be used in combination with the others at the same time. table 27-3. security functions function functional outline chip erase command prohibit execution of block erase and chip erase commands on all of the blocks is prohibited. once prohibition is set, all of the settings of prohi bition cannot be initialized because the chip erase command cannot be executed. block erase command prohibit execution of a block erase command on all of the blocks is prohi bited. setting of prohibition can be initialized by execution of a chip erase command. program command prohibit execution of program command and bl ock erase commands on all of the blocks is prohibited. setting of prohibition can be initialized by execution of the chip erase command. read command prohibit execution of a read command on all of t he blocks is prohibited. setting of the prohibition can be initialized by execution of the chip erase command. rewriting boot block cluster prohibit boot block clusters in block 0 to the specified block can be protected. rewriting (erasing and writing) the protected boot block clusters is disabled. even if the chip erase command is executed, setting of prohibition cannot be initialized. the maximum number of specifiable blocks is as follows. 384 kb version: 95 blocks 512/768/1024 kb versions: 127 blocks
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 726 of 870 sep 30, 2010 table 27-4. security setting erase, write, read operations when each security is set ( : executable, : not executable, ? : not supported) notes on security setting function on-board/ off-board programming self programming on-board/ off-board programming self programming chip erase command prohibit chip erase command: block erase command: program command: note 1 read command: chip erasure: ? block erasure (flashblockerase): write (flashwordwrite): read (flashwordread): setting of prohibition cannot be initialized. block erase command prohibit chip erase command: block erase command: program command: read command: chip erasure: ? block erasure (flashblockerase): write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. program command prohibit chip erase command: block erase command: program command: read command: chip erasure: ? block erasure (flashblockerase): write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. read command prohibit chip erase command: block erase command: program command: read command: chip erasure: ? block erasure (flashblockerase): write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. supported only when setting is changed from enable to disable boot block cluster rewrite prohibit chip erase command: block erase command: note 2 program command: note 2 read command: chip erasure: ? block erasure (flashblockerase): note 2 write (flashwordwrite): note 2 read (flashwordread): setting of prohibition cannot be initialized. supported only when setting is changed from enable to disable note 3 notes 1. in this case, since the erase command is invalid, data different from the data alre ady written in the flash memory cannot be written. 2. executable except in boot block cluster. 3. the boot block cluster rewrite prohibit functi on becomes effective after the reset input.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 727 of 870 sep 30, 2010 27.4 rewriting by dedicated flash programmer the flash memory can be rewritten by using a dedicated flash programmer a fter the v850es/jg3 is mounted on the target system (on-board programming). the flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (fa series). 27.4.1 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850es/jg3. figure 27-2. environment required fo r writing programs to flash memory host machine rs-232c v850es/jg3 flmd1 note v dd v ss reset uarta0/csib0/csib3 flmd0 usb dedicated flash programmer note connect the flmd1 pin to the flash programmer or con nect to a gnd via a pull-down resistor on the board. a host machine is required for controlling the dedicated flash programmer. uarta0, csib0, or csib3 is used for the interface betw een the dedicated flash programmer and the v850es/jg3 to perform writing, erasing, etc. a dedicated program adapter (fa series ) required for off-board writing. ? fa-70f3353gc-8ea-rx (already wired) ? fa-100gc-8eu-a (not wired: wiring required) remark the fa series is a product of naito densei machida mfg. co., ltd.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 728 of 870 sep 30, 2010 27.4.2 communication mode communication between the dedicated flash programmer and the v850es/jg3 is performed by serial communication using the uarta0, csib0, or csib 3 interfaces of the v850es/jg3. (1) uarta0 transfer rate: 9,600 to 153,600 bps figure 27-3. communication with dedicated flash programmer (uarta0) v850es/jg3 v dd v ss reset txda0 rxda0 flmd1 flmd1 note v dd gnd reset rxd txd flmd0 flmd0 dedicated flash programmer note connect the flmd1 pin to the flash programmer or con nect to gnd via a pull-down resistor on the board. (2) csib0, csib3 serial clock: 2.4 khz to 2.5 mhz (msb first) figure 27-4. communication with dedica ted flash programmer (csib0, csib3) v850es/jg3 flmd1 note v dd v ss reset sob0, sob3 sib0, sib3 sckb0, sckb3 flmd1 v dd gnd reset si so sck flmd0 flmd0 dedicated flash programmer note connect the flmd1 pin to the flash programmer or con nect to gnd via a pull-down resistor on the board.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 729 of 870 sep 30, 2010 (3) csib0 + hs, csib3 + hs serial clock: 2.4 khz to 2.5 mhz (msb first) figure 27-5. communication with dedicated flash programmer (csib0 + hs, csib3 + hs) v850es/jg3 v dd v ss reset sob0, sob3 sib0, sib3 sckb0, sckb3 pcm0 v dd flmd1 flmd1 note gnd reset si so sck hs flmd0 flmd0 dedicated flash programmer note connect the flmd1 pin to the flash programmer or con nect to a gnd via a pull-down resistor on the board. the dedicated flash programmer outputs the transfer clock, and the v850es/jg3 operates as a slave. when the pg-fp4 is used as the dedicated flash programmer, it generates the following signals to the v850es/jg3. for details, refer to the pg-fp4 user?s manual (u15260e) . table 27-5. signal connections of dedicated flash programmer (pg-fp4) pg-fp4 v850es/jg3 pr ocessing for connection signal name i/o pin function pin name uarta0 csib0, csib3 csib0 + hs, csib3 + hs flmd0 output write enable/disable flmd0 flmd1 output write enable/disable flmd1 note 1 note 1 note 1 vdd ? v dd voltage generation/voltage monitor v dd gnd ? ground v ss clk output clock output to v850es/jg3 x1, x2 note 2 note 2 note 2 reset output reset signal reset si/rxd input receive signal sob0, sob3/ txda0 so/txd output transmit signal sib0, sib3/ rxda0 sck output transfer clock sckb0, sckb3 hs input handshake signal for csib0 + hs, csib3 + hs communication pcm0 notes 1. wire these pins as shown in figure 27-6, or connect then to gnd via pull-down resistor on board. 2. clock cannot be supplied via the clk pin of the flash programmer. create an oscillator on board and supply the clock. remark : must be connected. : does not have to be connected.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 730 of 870 sep 30, 2010 table 27-6. wiring of flash writing adap ter for v850es/jg3 (fa-100gc-8eu-a) (1/2) flash programmer (pg-fp4) connection pins when csib0 + hs is used when csib0 is used when uarta0 is used signal name i/o pin function pin name on fa board pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal si p41/sob0/scl01 23 p41/sob0/scl01 23 p30/txda0/sob4 25 so/txd output transmit signal so p40/sib0 /sda01 22 p40/sib0/sda01 22 p31/rxda0/intp7/ sib4 26 sck output transfer clock sck p42/sckb0 24 p42/sckb0 24 not necessary ? x1 not necessary ? not necessary ? not necessary ? clk output clock to v850es/jg3 x2 not necessary ? not necessary ? not necessary ? /reset output reset signal /reset reset 14 reset 14 reset 14 flmd0 output write voltage flmd0 flmd0 8 flmd0 8 flmd0 8 flmd1 output write voltage flmd1 pdl5/ad5/flmd1 76 pdl5/ad5/flmd1 76 pdl5/ad5/flmd1 76 hs input handshake signal of csi0 + hs communication reserve / hs pcm0/wait 61 not necessary ? not necessary ? v dd 9 v dd 9 v dd 9 ev dd 34, 70 ev dd 34, 70 ev dd 34, 70 av ref0 1 av ref0 1 av ref0 1 vdd ? vdd voltage generation/ voltage monitor vdd av ref1 5 av ref1 5 av ref1 5 v ss 11 v ss 11 v ss 11 av ss 2 av ss 2 av ss 2 gnd ? ground gnd ev ss 33, 69 ev ss 33, 69 ev ss 33, 69 cautions 1. be sure to conn ect the regc pin to gnd via a 4.7 f (recommended value) capacitor. 2. a clock cannot be supplied from the clk pin of the flash programmer. create an oscillator on the board and supply the clock from that oscillator.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 731 of 870 sep 30, 2010 table 27-6. wiring of flash writing adap ter for v850es/jg3 (fa-100gc-8eu-a) (2/2) flash programmer (pg-fp4) connection pins when csib3 + hs is used when csib3 is used signal name i/o pin function pin name on fa board pin name pin no. pin name pin no. si/rxd input receive signal si p911/a11/sob3 54 p911/a11/sob3 54 so/txd output transmit signal so p910/a10/sib3 53 p910/a10/sib3 53 sck output transfer clock sck p912/a12/sckb3 55 p912/a12/sckb3 55 x1 not necessary ? not necessary ? clk output clock to v850es/jg3 x2 not necessary ? not necessary ? /reset output reset signal /reset reset 14 reset 14 flmd0 output write voltage flmd0 flmd0 8 flmd0 8 flmd1 output write voltage flmd1 pdl5/ad5/flmd1 76 pdl5/ad5/flmd1 76 hs input handshake signal of csi0 + hs communication reserve/hs pcm0/wait 61 not necessary ? v dd 9 v dd 9 ev dd 34, 70 ev dd 34, 70 av ref0 1 av ref0 1 vdd ? vdd voltage generation/ voltage monitor vdd av ref1 5 av ref1 5 v ss 11 v ss 11 av ss 2 av ss 2 gnd ? ground gnd ev ss 33, 69 ev ss 33, 69 cautions 1. be sure to conn ect the regc pin to gnd via a 4.7 f (recommended value) capacitor. 2. a clock cannot be supplied from the clk pin of the flash programmer. create an oscillator on the board and supply the clock from that oscillator.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 732 of 870 sep 30, 2010 figure 27-6. example of wiring of v850es/jg 3 flash writing adapte r (fa-100gc-8eu-a) (in csib0 + hs mode) (1/2) v850es/jg3 rfu-3 rfu-2 vde flmd1 flmd0 rfu-1 si so sck /reset v pp reserve/hs x1 x2 vdd gnd gnd vdd gnd vdd vdd gnd 1 5 10 15 20 25 75 70 65 60 55 51 26 30 35 40 45 50 100 95 90 85 80 76 connect this pin to vdd. connect this pin to gnd. note 3 note 2 note 1 note 4 4.7 f (recommended value)
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 733 of 870 sep 30, 2010 figure 27-6. example of wiring of v850es/jg 3 flash writing adapte r (fa-100gc-8eu-a) (in csib0 + hs mode) (2/2) notes 1. wire the flmd1 pin as shown below, or connect it to gnd on board via a pull-down resistor. 2. pins used when csib3 is used 3. supply a clock by creating an oscillator on the fl ash writing adapter (enclosed by the broken lines). here is an example of the oscillator. example x1 x2 4. pins used when uarta0 is used. caution do not input a high level to the drst pin. remarks 1. process the pins not shown in accord ance with processing of unused pins (see 2.3 pin i/o circuit types, i/o buffer power supplies and handling of unused pins ). 2. this adapter is for the 100-pin plastic lqfp package.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 734 of 870 sep 30, 2010 27.4.3 flash memory control the following shows the procedure for manipulating the flash memory. figure 27-7. procedure for manipulating flash memory start select communication system manipulate flash memory end? yes supplies flmd0 pulse no end switch to flash memory programming mode
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 735 of 870 sep 30, 2010 27.4.4 selection of communication mode in the v850es/jg3, the communication mode is selected by inputting pulses (12 pulses max.) to the flmd0 pin after switching to the flash memory programming mode. the fl md0 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. figure 27-8. selection of communication mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxda0 (input) txda0 (output) v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset released note the number of clocks is as follows depending on the communication mode. flmd0 pulse communication mode remarks 0 uarta0 communication rate: 9,600 bps (after reset), lsb first 8 csib0 v850es/jg3 performs slave operation, msb first 9 csib3 v850es/jg3 performs slave operation, msb first 11 csib0 + hs v850es/jg3 performs slave operation, msb first 12 csib3 + hs v850es/jg3 performs slave operation, msb first other rfu setting prohibited caution when uarta0 is selected , the receive clock is calculate d based on the reset command sent from the dedicated flash programme r after receiving the flmd0 pulse.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 736 of 870 sep 30, 2010 27.4.5 communication commands the v850es/jg3 communicates with the dedicated flash progr ammer by means of commands. the signals sent from the dedicated flash programmer to the v850es/jg3 are called ?commands?. t he response signals sent from the v850es/jg3 to the dedicated flash prog rammer are called ?response commands?. figure 27-9. communication commands v850es/jg3 command response command dedicated flash programmer the following shows the commands for flash memory control in the v850es/jg3. all of these commands are issued from the dedicated flash programmer, and the v850es/jg3 performs the processing corresponding to the commands. table 27-7. flash memory control commands support classification command name csib0, csib3 csib0 + hs, csib3 + hs uarta0 function blank check block blank check command checks if the contents of the memory in the specified block have been correctly erased. chip erase command erases the contents of the entire memory. erase block erase command erases the contents of the memory of the specified block. write program command writes the specified address range, and executes a contents verify check. verify command compares the contents of memory in the specified address range with data transferred from the flash programmer. verify checksum command reads the checksum in the specified address range. read read command reads the data written to the flash memory. silicon signature command reads silicon signature information. system setting, control security setting command disables the chip erase command, block erase command, program command, read command, and boot area rewrite.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 737 of 870 sep 30, 2010 27.4.6 pin connection when performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset. theref ore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) flmd0 pin in the normal operation mode, input a voltage of v ss level to the flmd0 pin. in the flash memory programming mode, supply a write voltage of v dd level to the flmd0 pin. because the flmd0 pin serves as a write protection pin in the self programming mode, a voltage of v dd level must be supplied to the flmd0 pin via port control, etc., before writing to the flash memory. for details, see 27.5.5 (1) flmd0 pin . figure 27-10. flmd0 pin connection example v850es/jg3 flmd0 dedicated flash programmer connection pin pull-down resistor (r flmd0 ) (2) flmd1 pin when 0 v is input to the flmd0 pin, t he flmd1 pin does not function. when v dd is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v must be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. figure 27-11. flmd1 pin connection example flmd1 pull-down resistor (r flmd1 ) other device v850es/jg3 caution if the v dd signal is input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 738 of 870 sep 30, 2010 table 27-8. relationship between flmd0 and flmd1 pi ns and operation mode wh en reset is released flmd0 flmd1 operation mode 0 don?t care normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited (3) serial interface pin the following shows the pins used by each serial interface. table 27-9. pins used by serial interfaces serial interface pins used uarta0 txda0, rxda0 csib0 sob0, sib0, sckb0 csib3 sob3, sib3, sckb3 csib0 + hs sob0, sib0, sckb0, pcm0 csib3 + hs sob3, sib3, sckb3, pcm0 when connecting a dedicated flash programmer to a serial interface pin that is co nnected to another device on- board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) conflict of signals when the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other devi ce to the output high-impedance status. figure 27-12. conflict of signals (serial interface input pin) v850es/jg3 input pin conflict of signals dedicated flash programmer connection pins other device output pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 739 of 870 sep 30, 2010 (b) malfunction of other device when the dedicated flash programmer (outpu t or input) is connected to a seri al interface pin (input or output) that is connected to another device (i nput), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device. figure 27-13. malfunction of other device v850es/jg3 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the v850es/jg3 outputs affects the other device, isolate the signal on the other device side. v850es/jg3 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 740 of 870 sep 30, 2010 (4) reset pin when the reset signals of the dedicated flash programmer are connected to the reset pin that is connected to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of si gnals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 27-14. conflict of signals (reset pin) v850es/jg3 reset dedicated flash programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. (5) port pins (including nmi) when the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. if the ex ternal device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to v dd via a resistor or connecting to v ss via a resistor. (6) other signal pins connect x1, x2, xt1, xt2, and regc in the same status as that in t he normal operation mode. during flash memory programming, input a low level to t he drst pin or leave it open. do not input a high level. (7) power supply supply the same power (v dd , v ss , ev dd , ev ss , av ref0 , av ref1 , av ss ) as in normal operation mode.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 741 of 870 sep 30, 2010 27.5 rewriting by self programming 27.5.1 overview the v850es/jg3 supports a flash macro serv ice that allows the user program to rewrite the internal flash memory by itself. by using this interface and a self programming libr ary that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal ram or external memory. consequently, the user program can be upgraded and constant data can be rewritten in the field. figure 27-15. concept of self programming application program self programming library flash macro service flash memory flash function execution flash information erase, write
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 742 of 870 sep 30, 2010 27.5.2 features (1) secure self programming (boot swap function) the v850es/jg3 supports a boot swap function that can exchange the physi cal memory of blocks 0 to 15 with the physical memory of blocks 16 to 31. by writing the start program to be rewr itten to blocks 16 to 31 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user prog ram always exists in blocks 0 to 15. figure 27-16. rewriting entire memory area (boot swap) block 0 block 1 : block 15 block 16 block 17 : block 31 block 32 : last block block 0 block 1 : block 15 block 16 block 17 : block 31 block 32 : last block block 0 block 1 : block 15 block 16 block 17 : block 31 block 32 : last block boot swap rewriting blocks 16 to 31 (2) interrupt support instructions cannot be fetched from the flash memory dur ing self programming. conventionally, a user handler written to the flash memory could not be used even if an interrupt occurred. therefore, in the v850es/jg 3, to use an interrupt during self program ming, processing transits to the specific address note in the internal ram. allocate the jump instruction that transits processing to the user interrupt servicing at the specific address note in the internal ram. note nmi interrupt: start address of internal ram maskable interrupt: start address of internal ram + 4 addresses
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 743 of 870 sep 30, 2010 27.5.3 standard self programming flow the entire processing to rewrite the flash memory by flash self programming is illustrated below. figure 27-17. standard self programming flow flash environment initialization processing erase processing write processing internal verify processing flash memory manipulation flash environment end processing end of processing all blocks end? ? disable accessing flash area ? disable stopping clock ? disable setting of a standby mode other than the halt mode ? disable dma transfer yes no
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 744 of 870 sep 30, 2010 27.5.4 flash functions table 27-10. flash function list function name outline support flashinit self-programming library initialization flashenv flash environment start/end flashflmdcheck flmd pin check flashstatuscheck hardware proc essing execution status check flashblockerase block erase flashwordwrite data write flashblockiverify internal verification of block flashblockblankcheck blank check of block flashsetinfo flash information setting flashgetinfo flash information acquisition flashbootswap boot swap execution 27.5.5 pin processing (1) flmd0 pin the flmd0 pin is used to set the operation mode when rese t is released and to protect the flash memory from being written during self rewriting. it is therefore necessary to keep the voltage applied to the flmd0 pin at 0 v when reset is released and a normal operation is execut ed. it is also necessary to apply a voltage of v dd level to the flmd0 pin during the self programming mode period via port control before the memory is rewritten. when self programming has been completed, the volt age on the flmd0 pin must be returned to 0 v. figure 27-18. mode change timing reset signal flmd0 pin v dd 0 v v dd 0 v self programming mode normal operation mode normal operation mode caution make sure that the flmd0 pin is at 0 v when reset is released.
v850es/jg3 chapter 27 flash memory r01uh0015ej0300 rev.3.00 page 745 of 870 sep 30, 2010 27.5.6 internal resources used the following table lists the internal resources used for self programming. these internal resources can also be used freely for purposes other than self programming. table 27-11. internal resources used resource name description stack area note an extension of the stack used by the user is used by the library (can be used in both the internal ram and external ram). library code note program entity of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as a user application. calls flash functions. maskable interrupt can be used in user application execut ion status or self programming status. to use this interrupt in the self-programming status, since the processing transits to the address of the internal ram start address + 4 addresses, allocate the jump instruction that transits the processing to the user interrupt servicing at the address of the internal ram start address + 4 addresses in advance. nmi interrupt can be used in user application execution status or self programming status. to use this interrupt in the self-programming status, since the processing transits to the address of the internal ram start address, allocate the jump instruction that transits the processing to the user interrupt servicing at the internal ram start address in advance. note about resources used, refer to the flash memory self-programming library user?s manual.
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 746 of 870 sep 30, 2010 chapter 28 on-chip debug function the v850es/jg3 on-chip debug function can be implemented by the following two methods. ? using the dcu (debug control unit) on-chip debug function is implement ed by the on-chip dcu in the v850es/ jg3, with using the drst, dck, dms, ddi, and ddo pins as the debug interface pins. ? not using the dcu on-chip debug function is implemented by minicube2 or t he like, using the user res ources, instead of the dcu. the following table shows the features of the two on-chip debug functions. table 28-1. on-chip debug function features debugging using dcu debugging without using dcu debug interface pins drst, dck, dms, ddi, ddo ? when uarta0 is used rxd0, txd0 ? when csib0 is used sib0, sob0, sckb0, hs (pcm0) ? when csib3 is used sib3, sob3, sckb3, hs (pcm0) securement of user resources not required required hardware break function 2 points 2 points internal rom area 4 points 4 points software break function internal ram area 2000 points 2000 points real-time ram monitor function note 1 available available dynamic memory modification (dmm) function note 2 available available mask function reset, nmi, intwdt2, hldrq, wait reset pin rom security function 10-byte id code aut hentication 10-byte id code authentication hardware used ninicube ? , etc. ninicube2, etc. trace function not supported. not supported. debug interrupt interface function (dbint) not supported. not supported. notes 1. this is a function which reads out memo ry contents during program execution. 2. this is a function which rewrites ra m contents during program execution.
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 747 of 870 sep 30, 2010 28.1 debugging with dcu programs can be debugged using the debug interface pins (drst, dck, dms, ddi, and ddo) to connect the on-chip debug emulator (minicube). 28.1.1 connection circuit example figure 28-1. circuit connection example when debu g interface pins are used for communication interface minicube v850es/jg3 vdd dck dms ddi ddo drst reset flmd0 gnd ev dd dck dms ddi ddo drst note 2 reset flmd0 note 3 flmd1/pdl5 ev ss note 1 status target power xxxxx xxxxxx xxxx notes 1. example of pin connection wh en minicube is not connected 2. a pull-down resistor is provided on chip. 3. for flash memory rewriting 28.1.2 interface signals the interface signals are described below. (1) drst this is a reset input signal for the on-chip debug unit. it is a negative-logic signal that asynchronously initializes the debug control unit. minicube raises the drst signal when it detects v dd of the target system after the integrated d ebugger is started, and starts the on-chip debug unit of the device. when the drst signal goes high, a reset signal is also generated in the cpu. when starting debugging by starti ng the integrated debugger, a cpu reset is always generated.
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 748 of 870 sep 30, 2010 (2) dck this is a clock input signal. it supplies a 20 mhz or 10 mhz clock from minicube. in the on-chip debug unit, the dms and ddi signals are sampled at t he rising edge of the dck signal, and t he data ddo is output at its falling edge. (3) dms this is a transfer mode select signal. the transfer stat us in the debug unit changes depending on the level of the dms signal. (4) ddi this is a data input signal. it is sampled in the on-chip debug unit at the rising edge of dck. (5) ddo this is a data output signal. it is output from the on- chip debug unit at the falling edge of the dck signal. (6) ev dd this signal is used to detect vdd of the target system. if vdd from the tar get system is not det ected, the signals output from minicube (drst, dck, dms, ddi, flmd 0, and reset) go into a high-impedance state. (7) flmd0 the flash self programming function is used for the function to download data to the flash memory via the integrated debugger. during flash self programming, the flmd0 pin must be kept high. in addition, connect a pull-down resistor to the flmd0 pin. the flmd0 pin can be controlled in either of the following two ways. <1> to control from minicube connect the flmd0 signal of minicube to the flmd0 pin. in the normal mode, nothing is dr iven by minicube (high impedance). during a break, minicube raises the flmd0 pin to the high level when the download function of the integrated debugger is executed. <2> to control from port connect any port of the device to the flmd0 pin. the same port as the one used by t he user program to realize the flas h self programming function may be used. on the console of the int egrated debugger, make a setting to raise the port pin to high level before executing the download function, or lower the port pi n after executing the download function. for details, refer to the id850qb ver. 3.10 integrated de bugger operation user?s manual (u17435e) . (8) reset this is a system reset input pin. if the drst pin is made in valid by the value of th e ocdm0 bit of the ocdm register set by the user program, on-chip debugging cannot be executed. therefore, reset is effected by minicube, using the reset pin, to make the drst pin valid (initialization).
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 749 of 870 sep 30, 2010 28.1.3 maskable functions reset, nmi, intwdt2, wait, and hldrq signals can be masked. the maskable functions with the debugger (id850qb) and the corresponding v850es/jg3 f unctions are listed below. table 28-2. maskable functions maskable functions with id850qb corresponding v850es/jg3 functions nmi0 nmi pin input nmi2 non-maskable interrupt request signal (intwdt2) generation stop ? hold hldrq pin input reset reset signal generation by reset pin input, low-voltage detector, clock monitor, or watchdog timer (wdt2) overflow wait wait pin input 28.1.4 register (1) on-chip debug m ode register (ocdm) the ocdm register is used to select the normal operation mode or on-chip debug mode. this register is a special register and can be written only in a combination of specific sequences (see 3.4.7 special registers ). this register is also used to specify whether a pin provided with an on-chip debug func tion is used as an on-chip debug pin or as an ordinary port/peripheral function pin. it also is used to disconnect the internal pull-down resistor of the p05/intp2/drst pin. the ocdm register can be written only while a low level is input to the drst pin. this register can be read or written in 8-bit or 1-bit units.
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 750 of 870 sep 30, 2010 0 ocdm0 0 1 operation mode ocdm 0 0 0 0 0 0 ocdm0 after reset: 01h note r/w address: fffff9fch when drst pin is low: normal operation mode (in which a pin that functions alternately as an on-chip debug function pin is used as a port/peripheral function pin) when drst pin is high: on-chip debug mode (in which a pin that functions alternately as an on-chip debug function pin is used as an on-chip debug mode pin) selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the p05/intp2/drst pin. < > note reset input sets this register to 01h. after rese t by the wdt2res signal, clock monitor (clm), or low- voltage detector (lvi), however, the val ue of the ocdm register is retained. cautions 1. when using the ddi, ddo, dck, and dms pins not as on-chip debu g pins but as port pins after external reset, any of the following actions must be taken. ? input a low level to the p05/intp2/drst pin. ? set the ocdm0 bit. in this case, take the following actions. <1> clear the ocdm0 bit to 0. <2> fix the p05/intp2/drst pin to low level until <1> is completed. 2. the drst pin has an on-chip pull-down resistor. this resi stor is disconnected when the ocdm0 flag is cleared to 0. ocdm0 flag (1: pull-down on, 0: pull-down off) 10 to 100 k (30 k (typ.)) drst
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 751 of 870 sep 30, 2010 28.1.5 operation the on-chip debug function is made invalid under the conditions shown in the table below. when this function is not used, keep the drst pin low until the ocdm.ocdm0 flag is cleared to 0. ocdm0 flag drst pin 0 1 l invalid invalid h invalid valid remark l: low-level input h: high-level input figure 28-2. timing when on-chip debug function is not used low-level input after ocdm0 bit is cleared, high level can be input/output. clearing ocdm0 bit releasing reset reset ocdm0 p05/intp2/drst 28.1.6 cautions (1) if a reset signal is input (from the target system or a reset signal from an internal reset source) during run (program execution), the br eak function may malfunction. (2) even if the reset signal is masked by the mask function, the i/o buffer (port pi n) may be reset if a reset signal is input from a pin. (3) pin reset during a break is masked a nd the cpu and peripheral i/o are not reset. if pin reset or internal reset is generated as soon as the flash memory is rewritten by dmm or read by the ram monitor function while the user program is being executed, the cpu and peripheral i/o may not be correctly reset. (4) in the on-chip debug mode, the ddo pin is forcibly set to the high-level output.
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 752 of 870 sep 30, 2010 28.2 debugging without using dcu the following describes how to implement an on-chip debu g function using minicube2 with pins for uarta0 (rxda0 and txda0), pins for csib0 (sib0, sob0, sckb0, and hs (pcm0)), or pins for csib3 (sib3, sob3, sckb3, and hs (pcm0)) as debug interfac es, without using the dcu. 28.2.1 circuit connection examples figure 28-3. circuit connection example when uart a0/csib0/csib3 is used for communication interface qb-mini2 v850es/jg3 gnd v dd v dd reset_out rxd/si note 1 vdd txd/so note 1 sck hs clk flmd1 note 2 flmd0 note 2 reset_in note 3 v ss txda0/sob0/sob3 v dd rxda0/sib0/sib3 sckb0/sckb3 flmd1 reset circuit flmd0 port x reset signal v dd note 4 v dd v dd hs (pcm0) reset minicube2 notes 1. connect txda0/sob0/sob3 (transmit side) of t he v850es/jg3 to rxd/si (receive side) of the target connector, and txd/so (tr ansmit side) of the target connec tor to rxda0/sib0/sib3 (receive side) of the v850es/jg3. 2. the v850es/jg3-side pin connected to this pi n (flmd0, flmd1) can be used as an alternate- function pin other than while the memory is rewri tten during a break in debugging, because this pin is in a hi-z state. 3. this connection is designed assuming that the reset signal is output from the n-ch open-drain buffer (output resistance: 100 or less). 4. the circuit enclosed by a dashed line is designed for flash self programming, which controls the flmd0 pin via ports. use the port for inputting or outputting the high level. when flash self programming is not performed, a pull-down resistance for the flmd0 pin can be within 1 k to 10 k . remark refer to table 28-3 for pins used when uarta0, csib0, or csib3 is used for communication interface.
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 753 of 870 sep 30, 2010 table 28-3. wiring between v850es/jg3 and minicube2 pin configuration of minicube2 (qb-mini2) with csib0-hs with csib3-hs with uarta0 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/rxd input pin to receive commands and data from v850es/jg3 p41/sob0 23 p911/sob3 54 p30/txd0 25 so/txd output pin to transmit commands and data to v850es/jg3 p40/sib0 22 p910/sib3 53 p31/rxd0 26 sck output clock output pin for 3-wire serial communication p42/sckb0 24 p912/sckb3 55 not needed ? clk output clock output pin not needed ? not needed ? not needed ? reset_out output reset output pin to v850es/jg3 reset 14 reset 14 reset 14 flmd0 output output pin to set v850es/jg3 to debug mode or programming mode flmd0 8 flmd0 8 flmd0 8 flmd1 output output pin to set programming mode pdl5/flmd1 76 pdl5/flmd1 76 pdl5/flmd1 76 hs input handshake signal for csi0 + hs communication pcm0/wait 61 pcm0/wait 61 not needed ? v ss 11 v ss 11 v ss 11 av ss 2 av ss 2 av ss 2 gnd ? ground ev ss 33, 69 ev ss 33, 69 ev ss 33, 69 reset_in input reset input pin on the target system 28.2.2 maskable functions only reset signals can be masked. the maskable functions with the debugger (id850qb) and the corresponding v850es/jg3 f unctions are listed below. table 28-4. maskable functions maskable functions with id850qb corresponding v850es/jg3 functions nmi0 ? nmi1 ? nmi2 ? stop ? hold ? reset reset signal generation by reset pin input wait ?
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 754 of 870 sep 30, 2010 28.2.3 securement of user resources the user must prepare the following to perform communication between minicube2 and the target device and implement each debug function. these it ems need to be set in the user program or using the compiler options. (1) securement of memory space the shaded portions in figure 28-4 are the areas rese rved for placing the debug monitor program, so user programs and data cannot be allocated in these spaces. these spaces must be secured so as not to be used by the user program. (2) security id setting the id code must be embedded in the area between 0 000070h and 0000079h in figure 28-4, to prevent the memory from being read by an unauthorized person. for details, refer to 28.3 rom security function .
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 755 of 870 sep 30, 2010 figure 28-4. memory spaces where de bug monitor programs are allocated csi0/uart receive interrupt vector (4 bytes) reset vector (4 bytes) interrupt vector for debugging (4 bytes) (2 kb) security id area (10 bytes) : debugging area note 1 note 2 internal rom (16 bytes) access-prohibited area internal ram internal rom area internal ram area note 3 0000000h 0000060h 0000070h 0000290h 3ffefffh 3ffeff0h notes 1. address values vary depending on the product. internal rom size address value pd70f3739 384 kb 005f800h to 005ffffh pd70f3740 512 kb 007f800h to 007ffffh pd70f3741 768 kb 00bf800h to 00bffffh pd70f3742 1024 kb 00ff800h to 00fffffh 2. this is the address when csib0 is used. it starts at 00002f0h when csib3 is used, and at 0000310h when uarta0 is used. 3. address values vary depending on the product. internal rom size address value pd70f3739 32 kb 3ff7000h pd70f3740 40 kb 3ff5000h pd70f3741 pd70f3742 60 kb 3ff0000h
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 756 of 870 sep 30, 2010 (3) reset vector a reset vector includes the jump in struction for the debug monitor program. [how to secure areas] it is not necessary to secure this area intentionally. when downloading a program, howe ver, the debugger rewrites the reset vector in accordance with the following cases. if the rewritten pattern does not match the following cases, the debugger generates an error (f 0c34 when using the id850qb). (a) when two nop instructions ar e placed in succession from address 0 before rewriting after rewriting 0x0 nop jumps to debug monitor program at 0x0 0x2 nop 0x4 xxxx 0x4 xxxx (b) when two 0xffff are successively placed from address 0 (already era sed device) before rewriting after rewriting 0x0 0xffff jumps to debug monitor program at 0x0 0x2 0xffff 0x4 xxxx 0x4 xxxx (c) the jr instruction is placed at address 0 (when using ca850) before rewriting after rewriting 0x0 jr disp22 jumps to debug monitor program at 0x0 0x4 jr disp22 - 4 (d) mov32 and jmp are placed in succession from address 0 (when using iar compiler iccv850) before rewriting after rewriting 0x0 mov imm32,reg1 jumps to debug monitor program at 0x0 0x6 jmp [reg1] 0x4 mov imm32,reg1 0xa jmp [reg1] (e) the jump instruction for the debug monitor program is placed at address 0 before rewriting after rewriting jumps to debug monitor program at 0x0 no change
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 757 of 870 sep 30, 2010 (4) securement of area for debug monitor program the shaded portions in figure 28-4 are the areas wher e the debug monitor program is allocated. the monitor program performs initialization processing for debug communication interface and run or break processing for the cpu. the internal rom area must be filled with 0xff. this area must not be rewritten by the user program. [how to secure areas] it is not necessarily required to secure this area if the user program does not use this area. to avoid problems that may occur during the debugger start up, however, it is recommended to secure this area in advance, using the compiler. the following shows examples for securing the area, us ing the renesas electronics compiler ca850. add the assemble source file and link directive code, as shown below. ? assemble source (add the following code as an assemble source file.) -- secures 2 kb space for monitor rom section .section ?monitorrom?, const .space 0x800, 0xff -- secures interrupt vector for debugging .section ?dbg0? .space 4, 0xff -- secures interrupt vector for serial communication -- change the section name according to the serial communication mode used .section ?intcb0r? .space 4, 0xff -- secures 16-byte space for monitor ram section .section ?monitorram?, bss .lcomm monitorramsym, 16, 4 -- defines symbol monitorramsym ? link directive (add the following code to the link directive file.) the following shows an example w hen the internal rom has 1024 kb (e nd address is 00fffffh) and internal ram has 60 kb (end address is 3ffefffh). mromseg : !load ?r v0x0ff800{ monitorrom = $progbits ?a monitorrom; }; mramseg : !load ?rw v0x03ffeff0{ monitorram = $nobits ?aw monitorram; };
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 758 of 870 sep 30, 2010 (5) securement of communication serial interface uarta0, csib0, or csib3 is used for communication between minicube2 and the tar get system. the settings related to the serial interface modes are performed by th e debug monitor program, but if the setting is changed by the user program, a communication error may occur. to prevent such a problem from occurring, communication serial interface must be secured in the user program. [how to secure communica tion serial interface] ? on-chip debug mode register (ocdm) for the on-chip debug function using the uarta0, csib0, or csib3, set the ocdm register functions to normal mode. be sure to set as follows. ? input low level to the p05/intp2/drst pin. ? set the ocdm0 bit as shown below. <1> clear the ocdm0 bit to 0. <2> fix the p05/intp2/drst pin input to low level until the processing of <1> is complete. ? serial interface registers do not set the registers related to csib0, csib3, or uarta0 in the user program. ? interrupt mask register when csib0 is used, do not mask the transmit end interru pt (intcb0r). when csib 3 is used, do not mask the transmit end interrupt (intcb3r). when uarta0 is used, do not mask the receive end interrupt (intua0r). (a) when csib0 is used cb0ric 0 6543210 7 (b) when csib3 is used cb3ric 0 6543210 7 (c) when uarta0 is used ua0ric 0 6543210 7 remark : don?t care
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 759 of 870 sep 30, 2010 ? port registers when uarta0 is used when uarta0 is used, port registers are set to make the txda0 and rxda0 pins valid by the debug monitor program. do not change the following register setti ngs with the user program during debugging. (the same value can be overwritten.) pfc3 00 6543210 7 pmc3l 11 6543210 7 remark : don?t care ? port registers when csib0 is used when csib0 is used, port registers are set to make the sib0, sob0, sckb0, and hs (pmc0) pins valid by the debug monitor program. do not change the following regi ster settings with the user program during debugging. (the same value can be overwritten.) (a) sib0, sob0, and sckb0 settings pmc4 111 6543210 7 pfc4 00 6543210 7 (b) hs (pmc0 pin) settings pmcm 0 6543210 7 pcm note 6543210 7 note writing to this bit is prohibited. the port values corresponding to the hs pin ar e changed by the monitor program according to the debugger status. to perform port register settings in 8-bit units, the user program can usually use read-modify-write. if an interrupt for debugging occurs before writing, however, an unexpected operation may be performed. remark : don?t care
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 760 of 870 sep 30, 2010 ? port registers when csib3 is used when csib3 is used, port registers are set to make the sib3, sob3, sckb3, and hs (pmc0) pins valid by the debug monitor program. do not change the following regi ster settings with the user program during debugging. (the same value can be overwritten.) (a) sib3, sob3, and sckb3 settings pmc9h 11 1 6543210 7 pfc9h 111 6543210 7 (b) hs (pmc0 pin) settings pmcm 0 6543210 7 pcm note 6543210 7 note writing to this bit is prohibited. the port values corresponding to the hs pin ar e changed by the monitor program according to the debugger status. to perform port register settings in 8-bit units, the user program can usually use read-modify-write. if an interrupt for debugging occurs before writing, however, an unexpected operation may be performed. remark : don?t care 28.2.4 cautions (1) handling of device that was used for debugging do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewritten during debugging and the numbe r of rewrites of the flash memory cannot be guaranteed. moreover, do not embed the debug monitor program into mass-produced products. (2) when breaks cannot be executed forced breaks cannot be executed if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial interface, which is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby releas e by a maskable interrupt is prohibited ? mode for communication between minicube2 and the tar get device is uarta0, and the main clock has been stopped
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 761 of 870 sep 30, 2010 (3) when pseudo real-ti me ram monitor (rrm) function and dmm function do not operate the pseudo rrm function and dmm function do not operat e if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial interface, which is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby releas e by a maskable interrupt is prohibited ? mode for communication between minicube2 and the tar get device is uarta0, and the main clock has been stopped ? mode for communication between minicube2 and the target device is uarta0, and a clock different from the one specified in the debugger is used for communication (4) standby release with pseudo rrm and dmm functions enabled the standby mode is released by the pseudo rrm function and dmm function if one of the following conditions is satisfied. ? mode for communication between minicube2 and the target device is csib0 or csib3 ? mode for communication between minicube2 and the tar get device is uarta0, and the main clock has been supplied. (5) writing to peripheral i/o re gisters that requires a specifi c sequence, using dmm function peripheral i/o registers that re quires a specific sequence cannot be written with the dmm function. (6) flash self programming if a space where the debug monitor program is allocated is rewritten by flash self programming, the debugger can no longer operate normally.
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 762 of 870 sep 30, 2010 28.3 rom security function 28.3.1 security id the flash memory versions of the v850es/jg3 perform authentication using a 10-byte id code to prevent the contents of the flash memory from being read by an unauthorized pe rson during on-chip debugging by the on-chip debug emulator. set the id code in the 10-byte on-chip flash memory ar ea from 0000070h to 0000079h to allow the debugger perform id authentication. if the ids match, the security is released and reading flash memory and using the on-chip debug emulator are enabled. ? set the 10-byte id code to 0000070h to 0000079h. ? bit 7 of 0000079h is the on-chip debug emulator enable flag. (0: disable, 1: enable) ? when the on-chip debug emulator is started, the debugger requests id input. when the id code input on the debugger and the id code set in 0000070h to 0000079h match, the debugger starts. ? debugging cannot be performed if the on-chip debug emul ator enable flag is 0, even if the id codes match. figure 28-5. security id area 0000079h 0000070h 0000000h security id (10 bytes) caution after the flash memory is erased , 1 is written to the entire area.
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 763 of 870 sep 30, 2010 28.3.2 setting the following shows how to set the id code as shown in table 28-5. when the id code is set as shown in t able 28-5, the id code input in the conf iguration dialog box of the id850qb is ?123456789abcdef123d4? (the id code is case-insensitive). table 28-5. id code address value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9a 0x75 0xbc 0x76 0xde 0x77 0xf1 0x78 0x23 0x79 0xd4 the id code can be specified for the devic e file that supports ca850 ver. 3.10 or later and the security id using the pm+ compiler common option setting.
v850es/jg3 chapter 28 on-chip debug function r01uh0015ej0300 rev.3.00 page 764 of 870 sep 30, 2010 [program example (when usi ng ca850 ver. 3.10 or later)] #-------------------------------------- # securityid #-------------------------------------- .section ?security_id? --interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xf1debc9a --4-7 byte code .hword 0xd423 --8-9 byte code remark add the above program exam ple to the startup files.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 765 of 870 sep 30, 2010 chapter 29 electrical specifications absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v ev dd v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v av ref0 v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v av ref1 v dd = ev dd = av ref0 = av ref1 ? 0.5 to +4.6 v v ss v ss = ev ss = av ss ? 0.5 to +0.5 v av ss v ss = ev ss = av ss ? 0.5 to +0.5 v supply voltage ev ss v ss = ev ss = av ss ? 0.5 to +0.5 v v i1 reset, flmd0, pdh4, pdh5, pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 ? 0.5 to ev dd + 0.5 note 1 v v i2 p10, p11 ? 0.5 to av ref1 + 0.5 note 1 v v i3 x1, x2 ? 0.5 to v ro note 2 + 0.5 note 1 v v i4 p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915 ? 0.5 to +6.0 v input voltage v i5 xt1, xt2 ? 0.5 to v dd + 0.5 note 1 v analog input voltage v ian p70 to p711 ? 0.5 to av ref0 + 0.5 note 1 v notes 1. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 2. on-chip regulator output voltage (2.5 v (typ.)) remark unless specified otherwise, the characte ristics of alternate-function pins are the same as those of port pins.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 766 of 870 sep 30, 2010 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin 4 ma p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4, pdh5 total of all pins 50 ma per pin 4 ma pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 total of all pins 50 ma per pin 4 ma p10, p11 total of all pins 8 ma per pin 4 ma output current, low i ol p70 to p711 total of all pins 20 ma per pin ? 4 ma p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4, pdh5 total of all pins ? 50 ma per pin ? 4 ma pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 total of all pins ? 50 ma per pin ? 4 ma p10, p11 total of all pins ? 8 ma per pin ? 4 ma output current, high i oh p70 to p711 total of all pins ? 20 ma operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 40 to +125 c cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however , can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolu te maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics re present the quality assurance range during normal operation. remark unless specified otherwise, the characte ristics of alternate-function pins are the same as those of port pins.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 767 of 870 sep 30, 2010 capacitance (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 = v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i/o capacitance c io f x = 1 mhz unmeasured pins returned to 0 v 10 pf operating conditions (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) supply voltage internal system clock frequency conditions v dd ev dd av ref0 , av ref1 unit c = 4.7 f (recommended value), a/d converter stopped, d/a converter stopped 2.85 to 3.6 2.85 to 3.6 2.85 to 3.6 v f xx = 2.5 to 32 mhz c = 4.7 f (recommended value), a/d converter operating, d/a converter operating 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 v f xt = 32.768 khz c = 4.7 f (recommended value), a/d converter stopped, d/a converter stopped 2.85 to 3.6 2.85 to 3.6 2.85 to 3.6 v
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 768 of 870 sep 30, 2010 main clock oscillator characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) resonator circuit example parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 2.5 10 mhz after reset is released 2 16 /f x s after stop mode is released 1 note 4 note 3 ms ceramic resonator/ crystal resonator x2 x1 oscillation stabilization time note 2 after idle2 mode is released 350 note 4 note 3 s notes 1. the oscillation frequency shown above indicates only osci llator characteristics. us e the v850es/jg3 so that the internal operation conditions do not exceed the ratings shown in ac characteristics and dc characteristics . 2. time required from start of oscillation until the resonator stabilizes. 3. the value varies depending on the setting of the osts register. 4. time required to set up the flash memory. se cure the setup time using the osts register. cautions 1. when using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adver se effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main clock is stopped and the devi ce is operating on the subclock, wait until the oscillation stabilization time has b een secured by the program before switching back to the main clock. 3. for the resonator selection and oscillator constant, customers are re quested to either evaluate the oscillation themselves or apply to the r esonator manufacturer for evaluation.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 769 of 870 sep 30, 2010 (i) kyocera kinseki corporation: crystal resonator (t a = ? 10 to +70 c) recommended circuit constant oscillation voltage range type circuit example part number oscillation frequency f x (khz) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) cx49gfwb04000d0peszz 4.000 8 8 0 2.2 3.6 cx49gfwb05000d0peszz 5.000 8 8 0 2.2 3.6 cx49gfwb06000d0peszz 6.000 8 8 0 2.2 3.6 cx49gfwb08000d0peszz 8.000 8 8 0 2.2 3.6 surface mounting x2 x1 c1 c2 rd cx49gfwb10000d0peszz 10.000 8 8 0 2.2 3.6 caution this oscillator constant is a reference value based on evaluation under a specific en vironment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual a pplication, apply to the resonator manufacturer for evaluati on on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteristics. use the v850es/jg3 so that the internal operating conditions are within the specifications of the dc and ac characteristics. (ii) murata mfg. co. ltd.: ceramic resonator (t a = ? 20 to +80 c) recommended circuit constant oscillation voltage range type circuit example part number oscillation frequency f x (khz) c1 (pf) c2 (pf) rd ( ) min. (v) max. (v) cstcc2m50g56-r0 2.500 (47) (47) 3300 2.85 3.6 cstcr4m00g55-r0 4.000 (39) (39) 1500 2.85 3.6 cstcr5m00g53-r0 5.000 (15) (15) 1500 2.85 3.6 cstcr6m00g53-r0 6.000 (15) (15) 1500 2.85 3.6 cstce8m00g55-r0 8.000 (33) (33) 330 2.85 3.6 surface mounting cstce10m0g52-r0 10.000 (10) (10) 470 2.85 3.6 cstls4m00g56-b0 4.000 (47) (47) 1500 2.85 3.6 cstls5m00g53-b0 5.000 (15) (15) 1500 2.85 3.6 cstls6m00g53-b0 6.000 (15) (15) 1500 2.85 3.6 cstls8m00g53-b0 8.000 (15) (15) 680 2.85 3.6 lead xt2 xt1 c1 c2 rd cstls10m0g53-b0 10.000 (15) (15) 680 2.85 3.6 caution this oscillator constant is a reference value based on evaluation under a specific en vironment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual a pplication, apply to the resonator manufacturer for evaluati on on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteristics. use the v850es/jg3 so that the internal operating conditions are within the specifications of the dc and ac characteristics. remark figures in parentheses in columns c1 and c2 indicate the capacitance incorporated in the resonator.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 770 of 870 sep 30, 2010 subclock oscillator characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) resonator circuit example parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz crystal resonator xt2 xt1 oscillation stabilization time note 2 10 s notes 1. the oscillation frequency shown above indicates only oscill ator characteristics. us e the v850es/jg3 so that the internal operation conditions do not exceed the ratings shown in ac characteristics and dc characteristics . 2. time required from when v dd reaches the oscillation voltage range (2.85 v (min.)) to when the crystal resonator stabilizes. cautions 1. when using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subclock oscillator is designed as a low- amplitude circuit for reducing power consumption, and is more prone to malf unction due to noise than the main clock oscillator. particular care is theref ore required with the wiring method when the subclock is used. 3. for the resonator selection and oscillator constant, customers are re quested to either evaluate the oscillation themselves or apply to the r esonator manufacturer for evaluation.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 771 of 870 sep 30, 2010 pll characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4 mode 2.5 5 mhz input frequency f x 8 mode 2.5 4 mhz 4 mode 10 20 mhz output frequency f xx 8 mode 20 32 mhz lock time t pll after v dd reaches 2.85 v (min.) 800 s internal oscillator characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit output frequency f r 100 220 400 khz regulator characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage v dd f xx = 32 mhz (max.) 2.85 3.6 v output voltage v ro 2.5 v regulator output stabilization time t reg after v dd reaches 2.85 v (min.), stabilization capacitance c = 4.7 f (recommended value) connected to regc pin 1 ms v dd v ro t reg reset
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 772 of 870 sep 30, 2010 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) (1/3) parameter symbol conditions min. typ. max. unit v ih1 pdh4, pdh5 0.7ev dd ev dd v v ih2 reset, flmd0 0.8ev dd ev dd v v ih3 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p915 0.8ev dd 5.5 v v ih4 p38, p39, p40, p41, p90, p91 0.7ev dd 5.5 v v ih5 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 0.7ev dd ev dd v v ih6 p70 to p711 0.7av ref0 av ref0 v input voltage, high v ih7 p10, p11 0.7av ref1 av ref1 v v il1 pdh4, pdh5 ev ss 0.3ev dd v v il2 reset, flmd0 ev ss 0.2ev dd v v il3 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p915 ev ss 0.2ev dd v v il4 p38, p39, p40, p41, p90, p91 ev ss 0.3ev dd v v il5 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 ev ss 0.3ev dd v v il6 p70 to p711 av ss 0.3av ref0 v input voltage, low v il7 p10, p11 av ss 0.3av ref1 v input leakage current, high i lih v i = v dd = ev dd = av ref0 = av ref1 5 a input leakage current, low i lil v i = 0 v ? 5 a output leakage current, high i loh v o = v dd = ev dd = av ref0 = av ref1 5 a output leakage current, low i lol v o = 0 v ? 5 a remark unless specified otherwise, the characte ristics of alternate-function pins are the same as those of port pins.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 773 of 870 sep 30, 2010 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) (2/3) parameter symbol conditions min. typ. max. unit per pin i oh = ? 1.0 ma total of all pins ? 20 ma ev dd ? 1.0 ev dd v v oh1 p02 to p06, p30 to p39, p40 to p42, p50 to p55, p90 to p915, pdh4, pdh5 per pin i oh = ? 100 a total of all pins ? 6.0 ma ev dd ? 0.5 ev dd v per pin i oh = ? 1.0 ma total of all pins ? 20 ma ev dd ? 1.0 ev dd v v oh2 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 per pin i oh = ? 100 a total of all pins ? 2.8 ma ev dd ? 0.5 ev dd v per pin i oh = ? 0.4 ma total of all pins ? 4.8 ma av ref0 ? 1.0 av ref0 v v oh3 p70 to p711 per pin i oh = ? 100 a total of all pins ? 1.2 ma av ref0 ? 0.5 av ref0 v per pin i oh = ? 0.4 ma total of all pins ? 0.8 ma av ref1 ? 1.0 av ref1 v output voltage, high v oh4 p10, p11 per pin i oh = ? 100 a total of all pins ? 0.2 ma av ref1 ? 0.5 av ref1 v v ol1 p02 to p06, p30 to p37, p42, p50 to p55, p92 to p915, pdh4, pdh5 per pin i ol = 1.0 ma 0 0.4 v v ol2 p38, p39, p40, p41, p90, p91 per pin i ol = 3.0 ma total of all pins 20 ma 0 0.4 v v ol3 pcm0 to pcm3, pct0, pct1, pct4, pct6, pdh0 to pdh3, pdl0 to pdl15 per pin i ol = 1.0 ma total of all pins 20 ma 0 0.4 v output voltage, low v ol4 p10, p11, p70 to p711 per pin i ol = 0.4 ma total of all pins 5.6 ma 0 0.4 v software pull-down resistor r 1 p05 v i = v dd 10 20 100 k remarks 1. unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins. 2. when the i oh and i ol conditions are not satisfied for a pin but the total value of all pins is satisfied, only that pin does not satisfy the dc characteristics.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 774 of 870 sep 30, 2010 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) (3/3) parameter symbol conditions min. typ. max. unit f xx = 32 mhz (f x = 4 mhz) 40 64 ma i dd1 normal operation f xx = 20 mhz (f x = 5 mhz) 30 50 ma f xx = 32 mhz (f x = 4 mhz) 27 45 ma i dd2 halt mode f xx = 20 mhz (f x = 5 mhz) 19 30 ma i dd3 idle1 mode f xx = 5 mhz (f x = 5 mhz), pll off 0.9 2.4 ma i dd4 idle2 mode f xx = 5 mhz (f x = 5 mhz), pll off 0.3 0.8 ma i dd5 subclock operating mode f xt = 32.768 khz, main clock, internal oscillator stopped 80 600 a i dd6 sub-idle mode f xt = 32.768 khz, main clock, internal oscillator stopped 11 100 a subclock stopped, internal oscillator stopped 8 80 a subclock operating, internal oscillator stopped 11 90 a i dd7 stop mode subclock stopped, internal oscillator operating 13 90 a f xx = 32 mhz (f x = 4 mhz) 45 74 ma supply current note i dd8 flash memory programming mode f xx = 20 mhz (f x = 5 mhz) 34 60 ma note to t a l o f v dd and ev dd currents. current flowing through the output buffers, a/d converter, d/a converter, and on-chip pull-down resistor is not included.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 775 of 870 sep 30, 2010 data retention characteristics in stop mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode (all functions stopped) 1.9 3.6 v data retention current i dddr stop mode (all functions stopped), v dddr = 2.0 v 8 80 a supply voltage rise time t rvd 200 s supply voltage fall time t fvd 200 s supply voltage retention time t hvd after stop mode setting 0 ms stop release signal input time t drel after v dd reaches 2.85 v (min.) 0 ms data retention input voltage, high v ihdr v dd = ev dd = v dddr 0.9v dddr v dddr v data retention input voltage, low v ildr v dd = ev dd = v dddr 0 0.1v dddr v caution shifting to stop mode and restoring from st op mode must be performed within the rated operating range. t drel t hvd t fvd t rvd stop release signal input stop mode setting v dddr v ihdr v ihdr v ildr v dd /ev dd reset (input) stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) operating voltage lower limit
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 776 of 870 sep 30, 2010 ac characteristics ac test input measurement points (v dd , av ref0 , av ref1 , ev dd ) v dd 0 v v ih v il v ih v il measurement points ac test output measurement points v oh v ol v oh v ol measurement points load conditions dut (device under measurement) c l = 50 pf caution if the load capaci tance exceeds 50 pf due to the circ uit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 777 of 870 sep 30, 2010 clkout output timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. max. unit output cycle t cyk <1> 31.25 ns 31.25 s high-level width t wkh <2> t cyk /2 ? 6 ns low-level width t wkl <3> t cyk /2 ? 6 ns rise time t kr <4> 6 ns fall time t kf <5> 6 ns clock timing clkout (output) <1> <2> <3> <4> <5>
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 778 of 870 sep 30, 2010 bus timing (1) in multiplexed bus mode caution when operating at f xx > 20 mhz, be sure to insert address hold waits and address setup waits. (a) read/write cycle (clkout asynchronous) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <6> (0.5 + t asw )t ? 20 ns address hold time (from astb ) t hsta <7> (0.5 + t ahw )t ? 15 ns delay time from rd to address float t frda <8> 16 ns data input setup time from address t said <9> (2 + n + t asw + t ahw )t ? 35 ns data input setup time from rd t srid <10> (1 + n)t ? 25 ns delay time from astb to rd, wrm t dstrdwr <11> (0.5 + t ahw )t ? 15 ns data input hold time (from rd ) t hrdid <12> 0 ns address output time from rd t drda <13> (1 + i)t ? 15 ns delay time from rd, wrm to astb t drdwrst <14> 0.5t ? 15 ns delay time from rd to astb t drdst <15> (1.5 + i + t asw )t ? 15 ns rd, wrm low-level width t wrdwrl <16> (1 + n)t ? 15 ns astb high-level width t wsth <17> (1 + i + t asw )t ? 15 ns data output time from wrm t dwrod <18> 15 ns data output setup time (to wrm ) t sodwr <19> (1 + n)t ? 20 ns data output hold time (from wrm ) t hwrod <20> t ? 15 ns t sawt1 <21> n 1 (1.5 + t asw + t ahw )t ? 35 ns wait setup time (to address) t sawt2 <22> (1.5 + n + t asw + t ahw )t ? 35 ns t hawt1 <23> n 1 (0.5 + n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <24> (1.5 + n + t asw + t ahw )t ns t sstwt1 <25> n 1 (1 + t ahw )t ? 25 ns wait setup time (to astb ) t sstwt2 <26> (1 + n + t ahw )t ? 25 ns t hstwt1 <27> n 1 (n + t ahw )t ns wait hold time (from astb ) t hstwt2 <28> (1 + n + t ahw )t ns remarks 1. t asw : number of address setup wait clocks t ahw : number of address hold wait clocks 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: number of idle states inserted after a read cycle (0 or 1) 6. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 779 of 870 sep 30, 2010 read cycle (clkout asynchronous ): in multiplexed bus mode clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 data address hi-z <6> <7> <17> <9> <12> <14> <10> <11> <25> <27> <26> <28> <21> <23> <22> <24> <16> <8> <13> <15> remark wr0 and wr1 are high level.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 780 of 870 sep 30, 2010 write cycle (clkout asynchronous ): in multiplexed bus mode clkout (output) ad0 to ad15 (i/o) wr0, wr1 (output) astb (output) wait (input) t1 t2 tw t3 data address <25> <27> <26> <28> <21> <23> <22> <24> <6> <17> <7> <14> <20> <19> <16> <11> <18> a16 to a21 (output) remark rd is high level.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 781 of 870 sep 30, 2010 (b) read/write cycle (clkout synchronous): in multiplexed bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka <29> 0 25 ns delay time from clkout to address float t fka <30> 0 19 ns delay time from clkout to astb t dkst <31> ? 12 7 ns delay time from clkout to rd, wrm t dkrdwr <32> ? 5 14 ns data input setup time (to clkout ) t sidk <33> 15 ns data input hold time (from clkout ) t hkid <34> 5 ns data output delay time from clkout t dkod <35> 19 ns wait setup time (to clkout ) t swtk <36> 20 ns wait hold time (from clkout ) t hkwt <37> 5 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. read cycle (clkout synchronous ): in multiplexed bus mode clkout (output) ad0 to ad15 (i/o) a16 to a21 (output) astb (output) rd (output) wait (input) t1 t2 tw t3 data address hi-z <29> <31> <32> <30> <31> <32> <36> <36> <37> <37> <33> <34> remark wr0 and wr1 are high level.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 782 of 870 sep 30, 2010 write cycle (clkout synchronous ): in multiplexed bus mode clkout (output) ad0 to ad15 (i/o) astb (output) wr0, wr1 (output) wait (input) t1 t2 tw t3 data address <29> <31> <32> <32> <37> <37> <36> <36> <31> <35> a16 to a21 (output) remark rd is high level.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 783 of 870 sep 30, 2010 (2) in separate bus mode caution when operating at f xx > 20 mhz, be sure to insert address hold waits, address setup waits, and data waits. (a) read cycle (clkout asynchronous): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to rd ) t sard <38> (0.5 + t asw )t ? 27 ns address hold time (from rd ) t hard <39> it ? 3.5 note ns rd low-level width t wrdl <40> (1.5 + n + t ahw )t ? 10 ns data setup time (to rd ) t sisd <41> 23 ns data hold time (from rd ) t hisd <42> ? 3.5 ns data setup time (to address) t said <43> (2 + n + t asw + t ahw )t ? 40 ns t srdwt1 <44> (0.5 + t ahw )t ? 25 ns wait setup time (to rd ) t srdwt2 <45> (0.5 + n + t ahw )t ? 25 ns t hrdwt1 <46> (n ? 0.5 + t ahw )t ns wait hold time (from rd ) t hrdwt2 <47> (n + 0.5 + t ahw )t ns t sawt1 <48> (1 + t asw + t ahw )t ? 45 ns wait setup time (to address) t sawt2 <49> (1 + n + t asw + t ahw )t ? 45 ns t hawt1 <50> (n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <51> (1 + n + t asw + t ahw )t ns note the address may be changed during the low-level period of the rd pin. to avoid the address change, insert an idle wait. remarks 1. t asw : number of address setup wait clocks t ahw : number of address hold wait clocks 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted 4. i: number of idle states inserted after a read cycle (0 or 1) 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 784 of 870 sep 30, 2010 read cycle (clkout asynchr onous): in separate bus mode clkout (output) t1 <43> hi-z hi-z <38> <40> <47> <45> <46> <44> <48> <50> <49> <51> <42> <41> <39> tw t2 rd (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) remark wr0 and wr1 are high level.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 785 of 870 sep 30, 2010 (b) write cycle (clkout asynchronous): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to wrm ) t sawr <52> (1 + t asw + t ahw )t ? 27 ns address hold time (from wrm ) t hawr <53> 0.5t ? 6 ns wrm low-level width t wwrl <54> (0.5 + n)t ? 10 ns data output time from wrm t dosdw <55> ? 5 ns data setup time (to wrm ) t sosdw <56> (0.5 + n)t ? 20 ns data hold time (from wrm ) t hosdw <57> 0.5t ? 7 ns data setup time (to address) t saod <58> (1 + t asw + t ahw )t ? 25 ns t swrwt1 <59> 22 ns wait setup time (to wrm ) t swrwt2 <60> nt ? 22 ns t hwrwt1 <61> 0 ns wait hold time (from wrm ) t hwrwt2 <62> nt ns t sawt1 <63> (1 + t asw + t ahw )t ? 45 ns wait setup time (to address) t sawt2 <64> (1 + n + t asw + t ahw )t ? 45 ns t hawt1 <65> (n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <66> (1 + n + t asw + t ahw )t ns remarks 1. m = 0, 1 2. t asw : number of address setup wait clocks t ahw : number of address hold wait clocks 3. t = 1/f cpu (f cpu : cpu operating clock frequency) 4. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 786 of 870 sep 30, 2010 write cycle (clkout asynchr onous): in separate bus mode clkout (output) t1 <58> <52> <55> <54> <62> <60> <61><59> <63> <65> <64> <66> <57> <56> <53> tw t2 wr0, wr1 (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) hi-z hi-z remark rd is high level.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 787 of 870 sep 30, 2010 (c) read cycle (clkout synchronous): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dksa <67> 0 27 ns data input setup time (to clkout ) t sisdk <68> 20 ns data input hold time (from clkout ) t hkisd <69> 0 ns delay time from clkout to rd t dksr <70> ? 2 12 ns wait setup time (to clkout ) t swtk <71> 20 ns wait hold time (from clkout ) t hkwt <72> 0 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. read cycle (clkout synchronous, 1 wait): in separate bus mode clkout (output) t1 <70> <71> <72> <71> <72> <67> <70> <68> <69> hi-z hi-z tw t2 rd (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) <67> remark wr0 and wr1 are high level.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 788 of 870 sep 30, 2010 (d) write cycle (clkout synchronous): in separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dksa <73> 0 27 ns delay time from clkout to data output t dksd <74> 0 18 ns delay time from clkout to wrm t dksw <75> ? 2 12 ns wait setup time (to clkout ) t swtk <76> 20 ns wait hold time (from clkout ) t hkwt <77> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. write cycle (clkout synchronous ): in separate bus mode clkout (output) t1 <74> <75> <77> <76> <75> tw t2 wr0, wr1 (output) a0 to a21 (output) ad0 to ad15 (i/o) wait (input) <73> <73> <77> <76> <74> hi-z hi-z remark rd is high level.
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 789 of 870 sep 30, 2010 (3) bus hold (a) clkout asynchronous (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit hldrq high-level width t whqh <78> t + 10 ns hldak low-level width t whal <79> t ? 15 ns delay time from hldak to bus output t dhac <80> ? 3 ns delay time from hldrq to hldak t dhqha1 <81> (2n + 7.5)t + 26 ns delay time from hldrq to hldak t dhqha2 <82> 0.5t 1.5t + 26 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. bus hold (clkout asynchronous) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th ti ti hi-z astb (output) rd (output), wr0, wr1 (output) hi-z hi-z <78> <82> <79> <80> <81>
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 790 of 870 sep 30, 2010 (b) clkout synchronous (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) t shqk <83> 20 ns hldrq hold time (from clkout ) t hkhq <84> 5 ns delay time from clkout to bus float t dkf <85> 19 ns delay time from clkout to hldak t dkha <86> 19 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. bus hold (clkout synchronous) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th t2 t3 ti ti hi-z astb (output) rd (output), wr0, wr1 (output) hi-z hi-z <83> <83> <86> <86> <84> <85>
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 791 of 870 sep 30, 2010 power on/power off/reset timing (t a = ? 40 to +85 c, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit ev dd v dd t rel <87> 0 ns ev dd av ref0 , av ref1 t rea <88> 0 t rel ns v dd reset t rer <89> 500 + t reg note ns analog noise elimination (during flash erase/ writing) 500 ns reset low-level width t wrsl <90> analog noise elimination 500 ns reset v dd t fre <91> 500 ns v dd ev dd t fel <92> 0 ns av ref0 ev dd t fea <93> 0 t fel ns note depends on the on-chip regulator characteristics. v dd ev dd v i v i v i v i av ref0 reset (input) <87> <89> <91> <90> <88> <92> <93> interrupt timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit nmi high-level width t wnih analog noise elimination 500 ns nmi low-level width t wnil analog noise elimination 500 ns n = 0 to 7 (analog noise elimination) 500 ns intpn high-level width t with n = 3 (digital noise elimination) 3t smp + 20 ns n = 0 to 7 (analog noise elimination) 500 ns intpn low-level width t witl n = 3 (digital noise elimination) 3t smp + 20 ns remark t smp : noise elimination sampling clock cycle
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 792 of 870 sep 30, 2010 key return timing (t a = ? 40 to +85 c, v dd = ev dd = av ref 0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit krn high-level width t wkrh analog noise elimination 500 ns krn low-level width t wkrl analog noise elimination 500 ns remark n = 0 to 7 timer timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit ti high-level width t tih 2t + 20 ns ti low-level width t til tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tiq00 to tiq03 2t + 20 ns remark t = 1/f xx uart timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate 625 kbps asck0 cycle time 10 mhz
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 793 of 870 sep 30, 2010 csib timing (1) master mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckbn cycle time t kcy1 <94> 125 ns sckbn high-/low-level width t kh1 , t kl1 <95> t kcy1 /2 ? 8 ns sibn setup time (to sckbn ) t sik1 <96> 27 ns sibn hold time (from sckbn ) t ksi1 <97> 27 ns delay time from sckbn to sobn output t kso1 <98> 27 ns remark n = 0 to 4 (2) slave mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckbn cycle time t kcy2 <94> 125 ns sckbn high-/low-level width t kh2 , t kl2 <95> 54.5 ns sibn setup time (to sckbn ) t sik2 <96> 27 ns sibn hold time (from sckbn ) t ksi2 <97> 27 ns delay time from sckbn to sobn output t kso2 <98> 27 ns remark n = 0 to 4 sobn (output) input data output data sibn (input) sckbn (i/o) <94> <95> <95> <96> <97> <98> hi-z hi-z remark n = 0 to 4
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 794 of 870 sep 30, 2010 i 2 c bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) normal mode high-speed mode parameter symbol min. max. min. max. unit scl0n clock frequency f clk 0 100 0 400 khz bus free time (between start and stop conditions) t buf <99> 4.7 ? 1.3 ? s hold time note 1 t hd: sta <100> 4.0 ? 0.6 ? s scl0n clock low-level width t low <101> 4.7 ? 1.3 ? s scl0n clock high-level width t high <102> 4.0 ? 0.6 ? s setup time for start/restart conditions t su: sta <103> 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd: dat <104> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su: dat <105> 250 ? 100 note 4 ? ns sda0n and scl0n signal rise time t r <106> ? 1000 20 + 0.1cb note 5 300 ns sda0n and scl0n signal fall time t f <107> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su: sto <108> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <109> ? ? 0 50 ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda0n signal (at v ihmin. of scl0n signal) in order to occupy the undefined ar ea at the falling edge of scl0n. 3. if the system does not extend the scl0n signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the sc l0n signal?s low state hold time: t su : dat 250 ns ? if the system extends the scl0n signal?s low state hold time: transmit the following data bit to the sda0n line prior to the scl0n line release (t rmax. + t su:dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark n = 0 to 2
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 795 of 870 sep 30, 2010 i 2 c bus mode stop condition start condition restart condition stop condition scl0n (i/o) sda0n (i/o) <101> <107> <107> <106> <106> <104> <105> <103> <100> <99> <100> <109> <108> <102> remark n = 0 to 2 a/d converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , 3.0 v av ref0 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 bit overall error note 3.0 av ref0 3.6 v 0.6 %fsr conversion time t conv 2.6 24 s zero scale error 0.5 %fsr full scale error 0.5 %fsr non-linearity error 4.0 lsb differential linearity error 4.0 lsb analog input voltage v ian av ss av ref0 v reference voltage av ref0 3.0 3.6 v normal conversion mode 3 6.5 ma high-speed conversion mode 4 10 ma av ref0 current ai ref0 when a/d converter unused 5 a note excluding quantization error ( 0.05%fsr). caution do not set (read/write) alternate-function ports during a/d conversion; otherwise the conversion resolution may be degraded. remark lsb: least significant bit fsr: full scale range
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 796 of 870 sep 30, 2010 d/a converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , 3.0 v av ref1 3.6 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 8 bit overall error note 1 r = 2 m 1.2 %fsr settling time c = 20 pf 3 s output resistor r o output data 55h 6.42 k reference voltage av ref1 3.0 3.6 v d/a conversion operating 1 2.5 ma av ref1 current note 2 ai ref1 d/a conversion stopped 5 a notes 1. excluding quantization error ( 0.5 lsb). 2. value of 1 channel of d/a converter remark r is the output pin load resistance and c is the output pin load capacitance. lvi circuit characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit detection voltage v lvi0 2.85 2.95 3.05 v response time note t ld after v dd reaches v lvi0 (max.), or after v dd has dropped to v lvi0 (min.) 0.2 2.0 ms minimum pulse width t lw 0.2 ms reference voltage stabilization wait time t lwait after v dd reaches 2.85 v (min.) 0.1 0.2 ms note time required to detect the detection volt age and output an interrupt or reset signal. supply voltage (v dd ) time detection voltage (min.) operating voltage (min.) detection voltage (typ.) detection voltage (max.) t lwait t lw t ld t ld lvion bit = 0 1
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 797 of 870 sep 30, 2010 ram retention detection (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit detection voltage v ramh 1.9 2.0 2.1 v supply voltage rise time t ramhth v dd = 0 to 2.85 v 0.002 ms response time note t ramhd after v dd reaches 2.1 v 0.2 3.0 ms minimum pulse width t ramhw 0.2 ms note time required to detect the detection voltage and set the rams.ramf bit. supply voltage (v dd ) time detection voltage (min.) operating voltage (min.) detection voltage (typ.) detection voltage (max.) t ramhw t ramhd t ramhd t ramhth rams.ramf bit cleared by instruction
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 798 of 870 sep 30, 2010 flash memory programming characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = av ref1 , v ss = ev ss = av ss = 0 v, c l = 50 pf) (1) basic characteristics parameter symbol conditions min. typ. max. unit operating frequency f cpu 2.5 32 mhz supply voltage v dd 2.85 3.6 v used for updating programs when using flash memory programmer and renesas electronics self programming library retained for 15 years 1,000 times number of rewrites c wrt used for updating data when using rnesas electronics eeprom emulation library (usable rom size: 12 kb of 3 consecutive blocks) retained for 5 years 10,000 times programming temperature t prg ? 40 +85 c (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit flmd0, flmd1 setup time t mdset 2 3000 ms flmd0 count start time from reset t rfcf f x = 2.5 to 10 mhz 800 s flmd0 counter high-level width/ low-level width t ch /t cl 10 100 s flmd0 counter rise time/fall time t r /t f 1 s remark = oscillation stabilization time flash write mode setup timing v dd flmd1 0 v v dd reset (input) 0 v v dd flmd0 0 v t rfcf t cl t f t r t ch t mdset
v850es/jg3 chapter 29 electrical specifications r01uh0015ej0300 rev.3.00 page 799 of 870 sep 30, 2010 (3) programming characteristics parameter symbol conditions min. typ. max. unit chip erase time f xx = 32 mhz, batch erase 105 ms write time per 256 bytes f xx = 32 mhz 2.0 ms block internal verify time f xx = 32 mhz 10 ms block blank check time f xx = 32 mhz 0.5 ms flash memory information setting time f xx = 32 mhz 30 ms remark block size = 4 kbytes
v850es/jg3 chapter 30 package drawing r01uh0015ej0300 rev.3.00 page 800 of 870 sep 30, 2010 chapter 30 package drawing s y e sxb m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 (unit:mm) item dimensions d e hd he a a1 a2 a3 20.00 0.20 20.00 0.20 22.00 0.20 22.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p144gj-50-gae 3 note each lead centerline is located within 0.08mm of its true position at maximum material condition. detail of lead end 144-pin plastic lqfp (fine pitch) (20x20) 0.20 b 36 72 1 144 37 73 108 109
v850es/jg3 chapter 31 recommended soldering conditions r01uh0015ej0300 rev.3.00 page 801 of 870 sep 30, 2010 chapter 31 recommended soldering conditions the v850es/jg3 should be soldered and mounted under the following recommended conditions. for technical information, see the following website. semiconductor device mount manual (http:// www2.renesas.com /pkg/en/mount/index.html) table 31-1. surface mounting type solderi ng conditions pd70f3739gc-ueu-ax: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3740gc-ueu-ax: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3741gc-ueu-ax: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3742gc-ueu-ax: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ir60-207-3 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). remarks 1. products with -ax at the end of the part number are lead-free products. 2. for soldering methods and conditions other than those recommended above, please contact an renesas electronics sales representative.
v850es/jg3 appendix a development tools r01uh0015ej0300 rev.3.00 page 802 of 870 sep 30, 2010 appendix a development tools the following development t ools are available for the development of systems that employ the v850es/jg3. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, pr oducts supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computers, re fer to the explanation for ibm pc/at compatibles. ? windows tm unless otherwise specified, ?windows? means the following oss. ? windows 98, 2000 ? windows me ? windows xp ? windows nt tm ver. 4.0
v850es/jg3 appendix a development tools r01uh0015ej0300 rev.3.00 page 803 of 870 sep 30, 2010 figure a-1. development tool configuration flash memory write environment debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter note 2 in-circuit emulator (qb-v850essx2) note 5 ? project manager (windows only) note 1 software package conversion socket or conversion adapter target system control software embedded software ? real-time os ? network library ? file system on-chip debug emulator (qb-v850mini) note 3 (qb-mini2) note 4 flash memory write adapter flash programmer flash memory language processing software ? c compiler package ? device file notes 1. project manager pm+ is included in the c compiler package. pm+ is only used in windows. 2. the qb-v850mini, qb-mini2, and qb-v850essx2 support the usb interface only. 3. the qb-v850mini is supplied with the id850qb, usb interface cable, ocd cable, self-check board, kel adapter, and kel connector. all other products are optional. 4. the qb-mini2 is supplied with usb interface cable, 16-pin target cable, 10-pin target cable, and 78k0- ocd board (integrated debugger is not suppli ed.) all other products are optional. 5. the qb-v850essx2 is supplied with the id850qb, simple flash memo ry programmer, po wer supply unit, and usb interface adapter. a ll other products are optional.
v850es/jg3 appendix a development tools r01uh0015ej0300 rev.3.00 page 804 of 870 sep 30, 2010 a.1 software package development tools (software) commonly used with v850 microcontrollers are included this package. sp850 software package for v850 microcontrollers part number: s sp850 remark in the part number differs depending on the host machine and os used. s sp850 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this compiler converts programs written in c into object codes executable with a microcontroller. this compiler is started from project manager pm+. ca850 c compiler package part number: s ca703000 df703746 device file this file contains information peculiar to the device. this device file should be used in combination with a tool (ca850, sm850, or id850qb). the corresponding os and host machine differ depending on the tool to be used. remark in the part number differs depending on the host machine and os used. s ca703000 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) cd-rom a.3 control software pm+ project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from pm+. pm+ is included in c compiler package ca850. it can only be used in windows.
v850es/jg3 appendix a development tools r01uh0015ej0300 rev.3.00 page 805 of 870 sep 30, 2010 a.4 debugging tools (hardware) a.4.1 when using iecube qb-v850essx2 the system configuration when connec ting the qb-v850essx2 to the host machine (pc-9821 series, pc/at compatible) is shown below. even if optional prod ucts are not prepared, connection is possible. figure a-2. system configurati on (when using qb-v850essx2) (1/2) <12> mount adapter for device mounting <13> target connector for mounting on target system <8> exchange adapter exchanges pins among different microcontroller types <9> check pin adapter (s type only) enables signal monitoring <10> space adapter each adapter can adjust height by 5.6 mm. <14> target system <7> extension probe probe can be connected (s and t types) <12> mount adapter for device mounting <13> target connector for mounting on target system <11> yq connector connector for connecting to emulator <8> exchange adapter exchanges pins among different microcontroller types <10> space adapter each adapter can adjust height by 3.2 mm. <6> check pin adapter (under development) enables signal monitoring (s and t types) <5> iecube <1> s-type socket configuration optional required <4> power supply <2> cd-rom <3> usb cable simple flash programmer <14> target system t-type socket configuration system configuration accessories <1> host machine (pc-9821 series, ibm-pc/at compatibles) <2> debugger, usb driver, manuals, etc. (id850qb disk, accessory disk note 1 ) <3> usb interface cable <4> ac adapter <5> in-circuit emulator (qb-v850essx2) <6> check pin adapter (s and t types) (qb-144-ca-01 note 2 ) (optional) <7> extension probe (s and t ty pes) (qb-144-ep-01s) (optional) <8> exchange adapter note 3 (s type: qb-100gc-ea-01s, t type: qb-100gc-ea-01t) <9> check pin adapter note 4 (s type only) (qb-100-ca-01s) (optional) <10> space adapter note 4 (s type: qb-100-sa-01s, t type: qb-100gc-ys-01t) (optional) <11> yq connector note 3 (t type only) (qb-100gc-yq-01t) <12> mount adapter (s type: qb-100gc-ma -01s, t type: qb-100gc-hq-01t) (optional) <13> target connector note 3 (s type: qb-100gc-tc-01s, t type: qb-100gc-nq-01t) <14> target system
v850es/jg3 appendix a development tools r01uh0015ej0300 rev.3.00 page 806 of 870 sep 30, 2010 figure a-2. system configurat ion (when using qb-v850essx2) (2/2) notes 1. download the device file from the renesas electronics website. http://www2.renesas.com/micro/ja/ods/index.html 2. under development 3. supplied with the device depending on the ordering number. ? when qb-v850essx2-zzz is ordered the exchange adapter and the ta rget connector are not supplied. ? when qb-v850essx2-s100gc is ordered the qb-100gc-ea-01s and qb -100gc-tc-01s are supplied. ? when qb-v850essx2-t100gc is ordered the qb-100gc-ea-01t, qb-100gc-yq- 01t, and qb-100gc-nq-01t are supplied. 4. when using both <9> and <10>, the order between <9> and <10> is not cared. <5> qb-v850essx2 note in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using the v850es/jg3. it supports to the integrated debugger id850qb. this emulator should be used in combination with a power supply unit and emulation probe. use the usb interface ca ble to connect this emulator to the host machine. <3> usb interface cable cable to connect the host machine and the qb-v850essx2. <4> ac adapter 100 to 240 v can be supported by replacing the ac plug. <8> qb-100gc-ea-01s qb-100gc-ea-01t exchange adapter adapter to perform pin conversion. <9> qb-100-ca-01s check pin adapter adapter used in waveform monitoring using the oscilloscope, etc. <10> qb-100-sa-01s qb-100gc-ys-01t space adapter adapter to adjust the height. <11> qb-100gc-yq-01t yq connector conversion adapter to connect the target connector and the exchange adapter. <12> qb-100gc-ma-01s qb-100gc-hq-01t mount adapter adapter to mount the v850es/jg3 with socket. <13> qb-100gc-tc-01s qb-100gc-nq-01t target connector connector to solder on the target system. note the qb-v850essx2 is supplied with a power supply unit, usb interface cable, and simple programmer. it is also supplied with integrated debugger id850qb as control software. remark the numbers in the angle brackets correspond to the numbers in figure a-2.
v850es/jg3 appendix a development tools r01uh0015ej0300 rev.3.00 page 807 of 870 sep 30, 2010 a.4.2 when using minicube qb-v850mini (1) on-chip emulat ion using minicube the system configuration when connec ting minicube to the host machine (pc-9821 series, pc/at compatible) is shown below. figure a-3. on-chip emulation system configuration <7> <6> <1> <4> <3> <5> <2> status target po wer target system v850es/jg3 <1> host machine pc with usb ports <2> cd-rom note 1 contents such as integrated debugger id8 50qb, n-wire checker, device driver, and documents are included in cd-rom. it is supplied with minicube. <3> usb interface cable usb cable to connect the host machine and minicube. it is supplied with minicube. the cable length is approximately 2 m. <4> minicube on-chip debug emulator this on-chip debug emulator serves to debug hardware and software when developing application systems using the v850es/jg3. it supports integrated debugger id850qb. <5> ocd cable cable to connect minicube and the target system. it is supplied with minicube. the cable length is approximately 20 cm. <6> connector conversion board kel adapter this conversion board is supplied with minicube. <7> minicube connector kel connector note 2 8830e-026-170s (supplied with minicube) 8830e-026-170l (sold separately) notes 1. download the device file from the renesas electronics website. http://www2.renesas.com/micro/ja/ods/index.html 2. product of kel corporation remark the numbers in the angular brackets co rrespond to the numbers in figure a-3.
v850es/jg3 appendix a development tools r01uh0015ej0300 rev.3.00 page 808 of 870 sep 30, 2010 a.4.3 when using minicube2 qb-mini2 the system configurati on when connecting mi nicube2 to the host machine (pc-9 821 series, pc/at compatible) is shown below. figure a-4. system configuration of on-chip emulation system <6> <5> <1> <2> software <4> <3> minicube2 target system v850es/jg3 <1> host machine pc with usb ports <2> software the integrated debugger id850qb, device file, etc. download the device file from the renesas electronics website. http://www2.renesas.com/micro/ja/ods/index.html <3> usb interface cable usb cable to connect the host machine and minicube. it is supplied with minicube. the cable length is approximately 2 m. <4> minicube2 on-chip debug emulator this on-chip debug emulator serves to debug hardware and software when developing application systems using the v850es/jg3. it supports integrated debugger id850qb. <5> 16-pin target cable cable to connect minicube2 and the target system. it is supplied with minicube. the cable length is approximately 15 cm. <6> target connector (sold separat ely) use a 16-pin general-purpose connector with 2.54 mm pitch. remark the numbers in the angular brackets co rrespond to the numbers in figure a-4.
v850es/jg3 appendix a development tools r01uh0015ej0300 rev.3.00 page 809 of 870 sep 30, 2010 a.5 debugging tools (software) this simulator is used with v850 microcontrollers. sm850 is windows-based software. debugging of c source and assembler files is possible during simulation of the target system operation on the host machine. by using sm850, logic verifi cation and performance verificati on of applications can be performed independently from hardware development. therefore, development efficiency and software quality can be improved. it should be used in combination with the device file. sm850 (under development) system simulator part number: s sm703000 this debugger supports the in-circuit emulat ors for v850 microcontrollers. the id850qb is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memo ry display with the trace result. it should be used in combination with the device file. id850qb integrated debugger part number: s id703000-qb (id850qb) remark in the part number differs depending on the host machine and os used. s sm703000 s id703000-qb host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom
v850es/jg3 appendix a development tools r01uh0015ej0300 rev.3.00 page 810 of 870 sep 30, 2010 a.6 embedded software the rx850 and rx850 pro are real-time oss conforming to itron 3.0 specifications. a tool (configurator) for generating multiple information tables is supplied. rx850 pro has more functions than the rx850. rx850, rx850 pro real-time os part number: s rx703000- ??? (rx850) s rx703100- ??? (rx850 pro) rx-fs850 (file system) this is a fat file system function. it is a file system that supports the cd-rom file system function. this file system is used with the real-time os rx850 pro. caution to purchase the rx850 or rx850 pro, first fill in the purchase applicati on form and sign the license agreement. remark and ??? in the part number differ depending on the host machine and os used. s rx703000- ??? s rx703100- ??? ??? product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k 0.1 million units 001m 1 million units 010m mass-production object 10 million units s01 source program object source program for mass production host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation solaris (rel. 2.5.1) cd-rom
v850es/jg3 appendix a development tools r01uh0015ej0300 rev.3.00 page 811 of 870 sep 30, 2010 a.7 flash memory writing tools flashpro iv (part number: pg-fp4) flash programmer flash programmer dedicated to microcont rollers with on-chip flash memory. qb-mini2 (minicube2) on-chip debug em ulator with programming function. fa-100gc-8eu-a flash memory writing adapter flash memory writing adapter used connected to the flashpro iv, etc. (not wired). fa-70f3353gc-8ea-rx flash memory writing adapter flash memory writing adapter used connected to the flashpro iv, etc. (already wired). remark fa-100gc-8eu-a and fa-70f3353gc-8ea-rx are produc ts of naito densei machida mfg. co., ltd. tel: +81-42-750-4172
v850es/jg3 appendix b major differences between v850es/jg3 and v850es/jg2 r01uh0015ej0300 rev.3.00 page 812 of 870 sep 30, 2010 appendix b major differences between v850es/jg3 and v850es/jg2 differences between the v850es/jg3 and v850es/jg2 are shown below. for details, refer to each corresponding section. table b-1. major differences betw een v850es/jg3 and v850es/jg2 (1/2) major differences v850es/jg3 v850es/jg2 refer to: bv dd , bv ss pins changed to ev dd , ev ss pins provided throughout introduction: minimum instruction execution time 31.25 ns 50 ns 1.2 pin function: pin status of p10/ano0, p11/ano1 (when power is applied) hi-z undefined 2.2 internal flash memory 384/512/768/1024 kb 128/256/384/512/640 kb 3.4.4 (1) cpu function internal ram 32/40/60 kb 12/24/32/40/48 kb 3.4.4 (2) a/d converter: proportion of sampling time during conversion 8/26 clocks 4/26 clocks 13.5.2 reset function: firmware operation after releasing internal system reset none provided (refer to 22.3.4 (2) in user?s manual (u17715e) ) ? low-voltage detection interrupt (intlvi) occurrence source when supply voltage drops or rises across the detection voltage when supply voltage drops below the detection voltage 24.3 (1) low-voltage detection level 2.85 to 3.05 v (2.95 v (typ.)) 2.85 to 3.15 v (3.0 v (typ.)) 24.3 (2) low- voltage detector (lvi) rams.ramf bit set conditions ? voltage lower than detection level is detected ? set by instruction ? voltage lower than detection level is detected ? set by instruction ? reset by wdt2 and clm occurs ? reset by reset pin occurs during internal ram accessing 24.3 (3) crc function provided none chapter 25 regulator: supply clock to sub- oscillator supply voltage (v dd ) regulator output voltage 26.1 block configuration block 0 to last block: 4 kb each blocks 0 to 3: 28 kb each blocks 4 to 7: 4 kb each block 8 to last block: 64 kb each flash memory boot area 64 kb 56 kb 27.2 on-chip debug function cautions on reset related to software breakpoint none provided (refer to 27.1.6 (3) in user?s manual (u17715e) ) ?
v850es/jg3 appendix b major differences between v850es/jg3 and v850es/jg2 r01uh0015ej0300 rev.3.00 page 813 of 870 sep 30, 2010 table b-1. major differences betw een v850es/jg3 and v850es/jg2 (2/2) major differences v850es/jg3 v850es/jg2 refer to: operating condition (internal system clock frequency) f xx = 2.5 to 32 mhz f xx = 2.5 to 20 mhz internal oscillator characteristics (output frequency) 220 khz (typ.) (min. and max. values are the same as those of v850es/jg2) 200 khz (typ.) dc characteristics (supply current) additional parameters exist ? bus timing changed parameters exist ? csib timing changed parameters exist ? d/a converter (output resistance) 6.42 k 3.5 k lvi circuit characteristics (detection voltage) 2.85 to 3.05 v (2.95 v (typ.)) 2.85 to 3.15 v (3.0 v (typ.)) electrical specifications ram retention detection (response time) 3.0 ms (max.) 2.0 ms (max.) chapter 29 package drawing p100gc-50-ueu s100gf-65-jbt, s100gc-50-8ea chapter 30 recommended soldering conditions tbd provided ?
v850es/jg3 appendix c register index r01uh0015ej0300 rev.3.00 page 814 of 870 sep 30, 2010 appendix c register index (1/10) symbol name unit page ada0cr0 a/d conversion result register 0 adc 417 ada0cr0h a/d conversion result register 0h adc 417 ada0cr1 a/d conversion result register 1 adc 417 ada0cr1h a/d conversion result register 1h adc 417 ada0cr2 a/d conversion result register 2 adc 417 ada0cr2h a/d conversion result register 2h adc 417 ada0cr3 a/d conversion result register 3 adc 417 ada0cr3h a/d conversion result register 3h adc 417 ada0cr4 a/d conversion result register 4 adc 417 ada0cr4h a/d conversion result register 4h adc 417 ada0cr5 a/d conversion result register 5 adc 417 ada0cr5h a/d conversion result register 5h adc 417 ada0cr6 a/d conversion result register 6 adc 417 ada0cr6h a/d conversion result register 6h adc 417 ada0cr7 a/d conversion result register 7 adc 417 ada0cr7h a/d conversion result register 7h adc 417 ada0cr8 a/d conversion result register 8 adc 417 ada0cr8h a/d conversion result register 8h adc 417 ada0cr9 a/d conversion result register 9 adc 417 ada0cr9h a/d conversion result register 9h adc 417 ada0cr10 a/d conversion result register 10 adc 417 ada0cr10h a/d conversion result register 10h adc 417 ada0cr11 a/d conversion result register 11 adc 417 ada0cr11h a/d conversion result register 11h adc 417 ada0m0 a/d converter mode register 0 adc 420 ada0m1 a/d converter mode register 1 adc 412 ada0m2 a/d converter mode register 2 adc 415 ada0pfm power-fail compare mode register adc 419 ada0pft power-fail compare threshold value register adc 420 ada0s a/d converter channel specification register adc 416 adic interrupt control register intc 651 awc address wait control register bcu 164 bcc bus cycle control register bcu 165 bsc bus size configuration register bcu 153 cb0ctl0 csib0 control register 0 csi 488 cb0ctl1 csib0 control register 1 csi 491 cb0ctl2 csib0 control register 2 csi 492 cb0ric interrupt control register intc 651
v850es/jg3 appendix c register index r01uh0015ej0300 rev.3.00 page 815 of 870 sep 30, 2010 (2/10) symbol name unit page cb0rx csib0 receive data register csi 487 cb0rxl csib0 receive data register l csi 487 cb0str csib0 status register csi 494 cb0tic interrupt control register intc 651 cb0tx csib0 transmit data register csi 487 cb0txl csib0 transmit data register l csi 487 cb1ctl0 csib1 control register 0 csi 488 cb1ctl1 csib1 control register 1 csi 491 cb1ctl2 csib1 control register 2 csi 492 cb1ric interrupt control register intc 651 cb1rx csib1 receive data register csi 505 cb1rxl csib1 receive data register l csi 505 cb1str csib1 status register csi 512 cb1tic interrupt control register intc 651 cb1tx csib1 transmit data register csi 487 cb1txl csib1 transmit data register l csi 487 cb2ctl0 csib2 control register 0 csi 488 cb2ctl1 csib2 control register 1 csi 491 cb2ctl2 csib2 control register 2 csi 492 cb2ric interrupt control register intc 651 cb2rx csib2 receive data register csi 505 cb2rxl csib2 receive data register l csi 505 cb2str csib2 status register csi 512 cb2tic interrupt control register intc 651 cb2tx csib2 transmit data register csi 487 cb2txl csib2 transmit data register l csi 487 cb3ctl0 csib3 control register 0 csi 488 cb3ctl1 csib3 control register 1 csi 491 cb3ctl2 csib3 control register 2 csi 492 cb3ric interrupt control register intc 651 cb3rx csib3 receive data register csi 505 cb3rxl csib3 receive data register l csi 505 cb3str csib3 status register csi 512 cb3tic interrupt control register intc 651 cb3tx csib3 transmit data register csi 487 cb3txl csib3 transmit data register l csi 487 cb4ctl0 csib4 control register 0 csi 488 cb4ctl1 csib4 control register 1 csi 491 cb4ctl2 csib4 control register 2 csi 492 cb4ric interrupt control register intc 651 cb4rx csib4 receive data register csi 505 cb4rxl csib4 receive data register l csi 505 cb4str csib4 status register csi 512 cb4tic interrupt control register intc 651
v850es/jg3 appendix c register index r01uh0015ej0300 rev.3.00 page 816 of 870 sep 30, 2010 (3/10) symbol name unit page cb4tx csib4 transmit data register csi 487 cb4txl csib4 transmit data register l csi 487 ccls cpu operation clock status register cg 182 ckc clock control register cg 185 clm clock monitor mode register clm 703 crcd crc data register crc 720 crcin crc input register crc 720 ctbp callt base pointer cpu 33 ctpc callt execution status saving register cpu 32 ctpsw callt execution status saving register cpu 32 da0cs0 d/a conversion value setting register 0 dac 444 da0cs1 d/a conversion value setting register 1 dac 444 da0m d/a converter mode register dac 443 dadc0 dma addressing control register 0 dma 617 dadc1 dma addressing control register 1 dma 617 dadc2 dma addressing control register 2 dma 617 dadc3 dma addressing control register 3 dma 617 dbc0 dma transfer count register 0 dma 616 dbc1 dma transfer count register 1 dma 616 dbc2 dma transfer count register 2 dma 616 dbc3 dma transfer count register 3 dma 616 dbpc exception/debug trap status saving register cpu 33 dbpsw exception/debug trap status saving register cpu 33 dchc0 dma channel control register 0 dma 618 dchc1 dma channel control register 1 dma 618 dchc2 dma channel control register 2 dma 618 dchc3 dma channel control register 3 dma 618 dda0h dma destination address register 0h dma 615 dda0l dma destination address register 0l dma 615 dda1h dma destination address register 1h dma 615 dda1l dma destination address register 1l dma 615 dda2h dma destination address register 2h dma 615 dda2l dma destination address register 2l dma 615 dda3h dma destination address register 3h dma 615 dda3l dma destination address register 3l dma 615 dmaic0 interrupt control register intc 651 dmaic1 interrupt control register intc 651 dmaic2 interrupt control register intc 651 dmaic3 interrupt control register intc 651 dsa0h dma source address register 0h dma 632 dsa0l dma source address register 0l dma 614 dsa1h dma source address register 1h dma 614 dsa1l dma source address register 1l dma 614 dsa2h dma source address register 2h dma 614
v850es/jg3 appendix c register index r01uh0015ej0300 rev.3.00 page 817 of 870 sep 30, 2010 (4/10) symbol name unit page dsa2l dma source address register 2l dma 614 dsa3h dma source address register 3h dma 614 dsa3l dma source address register 3l dma 614 dtfr0 dma trigger factor register 0 dma 619 dtfr1 dma trigger factor register 1 dma 619 dtfr2 dma trigger factor register 2 dma 619 dtfr3 dma trigger factor register 3 dma 619 dwc0 data wait control register 0 bcu 161 ecr interrupt source register cpu 30 eipc interrupt status saving register cpu 29 eipsw interrupt status saving register cpu 29 eximc external bus interface mode control register bcu 152 fepc nmi status saving register cpu 30 fepsw nmi status saving register cpu 30 iic0 iic shift register 0 i 2 c 555 iic1 iic shift register 1 i 2 c 555 iic2 iic shift register 2 i 2 c 555 iicc0 iic control register 0 i 2 c 541 iicc1 iic control register 1 i 2 c 541 iicc2 iic control register 2 i 2 c 541 iiccl0 iic clock select register 0 i 2 c 551 iiccl1 iic clock select register 1 i 2 c 551 iiccl2 iic clock select register 2 i 2 c 551 iicf0 iic flag register 0 i 2 c 549 iicf1 iic flag register 1 i 2 c 549 iicf2 iic flag register 2 i 2 c 549 iicic0 interrupt control register intc 651 iicic1 interrupt control register intc 651 iicic2 interrupt control register intc 651 iics0 iic status register 0 i 2 c 546 iics1 iic status register 1 i 2 c 546 iics2 iic status register 2 i 2 c 546 iicx0 iic function expansion register 0 i 2 c 552 iicx1 iic function expansion register 1 i 2 c 552 iicx2 iic function expansion register 2 i 2 c 552 imr0 interrupt mask register 0 intc 653 imr0h interrupt mask register 0h intc 653 imr0l interrupt mask register 0l intc 653 imr1 interrupt mask register 1 intc 653 imr1h interrupt mask register 1h intc 653 imr1l interrupt mask register 1l intc 653 imr2 interrupt mask register 2 intc 653 imr2h interrupt mask register 2h intc 653 imr2l interrupt mask register 2l intc 653
v850es/jg3 appendix c register index r01uh0015ej0300 rev.3.00 page 818 of 870 sep 30, 2010 (5/10) symbol name unit page imr3 interrupt mask register 3 intc 653 imr3h interrupt mask register 3h intc 653 imr3l interrupt mask register 3l intc 653 intf0 external falling edge specification register 0 intc 665 intf3 external falling edge specification register 3 intc 666 intf9h external falling edge specification register 9h intc 667 intr0 external rising edge specification register 0 intc 665 intr3 external rising edge specification register 3 intc 666 intr9h external rising edge specification register 9h intc 667 ispr in-service priority register intc 655 kric interrupt control register intc 651 krm key return mode register kr 672 lockr lock register cg 186 lviic interrupt control register intc 654 lvim low-voltage detection register lvi 708 lvis low-voltage detection level select register lvi 709 nfc noise elimination control register intc 668 ocdm on-chip debug mode register dcu 749 ocks0 iic division clock select register 0 i 2 c 555 ocks1 iic division clock select register 1 i 2 c 555 osts oscillation stabilization time select register wdt 677 p0 port 0 register port 70 p1 port 1 register port 73 p3 port 3 register port 75 p3h port 3 register h port 75 p3l port 3 register l port 75 p4 port 4 register port 82 p5 port 5 register port 85 p7h port 7 register h port 88 p7l port 7 register l port 88 p9 port 9 register port 90 p9h port 9 register h port 90 p9l port 9 register l port 90 pc program counter cpu 27 pcc processor clock control register cg 178 pcm port cm register port 97 pct port ct register port 99 pdh port dh register port 101 pdl port dl register port 104 pdlh port dl register h port 104 pdll port dl register l port 104 pemu1 peripheral emulation register 1 cpu 713 pf0 port 0 function register port 712 pf3 port 3 function register port 79
v850es/jg3 appendix c register index r01uh0015ej0300 rev.3.00 page 819 of 870 sep 30, 2010 (6/10) symbol name unit page pf3h port 3 function register h port 79 pf3l port 3 function register l port 79 pf4 port 4 function register port 82 pf5 port 5 function register port 86 pf9 port 9 function register port 96 pf9h port 9 function register h port 96 pf9l port 9 function register l port 96 pfc0 port 0 function control register port 72 pfc3 port 3 function control register port 77 pfc3h port 3 function control register h port 77 pfc3l port 3 function control register l port 77 pfc4 port 4 function control register port 81 pfc5 port 5 function control register port 85 pfc9 port 9 function control register port 93 pfc9h port 9 function control register h port 93 pfc9l port 9 function control register l port 93 pfce3l port 3 function control expansion register l port 77 pfce5 port 5 function control expansion register port 85 pfce9 port 9 function control expansion register port 93 pfce9h port 9 function control expansion register h port 93 pfce9l port 9 function control expansion register l port 93 pic0 interrupt control register intc 651 pic1 interrupt control register intc 651 pic2 interrupt control register intc 651 pic3 interrupt control register intc 651 pic4 interrupt control register intc 651 pic5 interrupt control register intc 651 pic6 interrupt control register intc 651 pic7 interrupt control register intc 651 pllctl pll control register cg 184 plls pll lockup time specification register cg 187 pm0 port 0 mode register port 71 pm1 port 1 mode register port 73 pm3 port 3 mode register port 75 pm3h port 3 mode register h port 75 pm3l port 3 mode register l port 75 pm4 port 4 mode register port 80 pm5 port 5 mode register port 84 pm7h port 7 mode register h port 88 pm7l port 7 mode register l port 88 pm9 port 9 mode register port 90 pm9h port 9 mode register h port 90 pm9l port 9 mode register l port 90 pmc0 port 0 mode control register port 71
v850es/jg3 appendix c register index r01uh0015ej0300 rev.3.00 page 820 of 870 sep 30, 2010 (7/10) symbol name unit page pmc3 port 3 mode control register port 76 pmc3h port 3 mode control register h port 76 pmc3l port 3 mode control register l port 76 pmc4 port 4 mode control register port 81 pmc5 port 5 mode control register port 84 pmc9 port 9 mode control register port 91 pmc9h port 9 mode control register h port 91 pmc9l port 9 mode control register l port 91 pmccm port cm mode control register port 98 pmcct port ct mode control register port 100 pmcdh port dh mode control register port 102 pmcdl port dl mode control register port 105 pmcdlh port dl mode control register h port 105 pmcdll port dl mode control register l port 105 pmcm port cm mode register port 97 pmct port ct mode register port 99 pmdh port dh mode register port 101 pmdl port dl mode register port 104 pmdlh port dl mode register h port 104 pmdll port dl mode register l port 104 prcmd command register cpu 59 prscm0 prescaler compare register 0 wt 88 prscm1 prescaler compare register 1 csi 531 prscm2 prescaler compare register 2 csi 531 prscm3 prescaler compare register 3 csi 531 prsm0 prescaler mode register 0 wt 87 prsm1 prescaler mode register 1 csi 530 prsm2 prescaler mode register 2 csi 530 prsm3 prescaler mode register 3 csi 530 psc power save control register cg 675 psmr power save mode register cg 676 psw program status word cpu 31 r0 to r31 general-purpose registers cpu 27 rams internal ram data status register cg 709 rcm internal oscillation mode register cg 182 resf reset source flag register reset 694 rtbh0 real-time output buffer register 0h rtp 401 rtbl0 real-time output buffer register 0l rtp 401 rtpc0 real-time output port control register 0 rtp 403 rtpm0 real-time output port mode register 0 rtp 402 selcnt0 selector operation control register 0 timer 275 sva0 slave address register 0 i 2 c 556 sva1 slave address register 1 i 2 c 556 sva2 slave address register 2 i 2 c 556
v850es/jg3 appendix c register index r01uh0015ej0300 rev.3.00 page 821 of 870 sep 30, 2010 (8/10) symbol name unit page sys system status register cpu 60 tm0cmp0 tmm0 compare register 0 timer 377 tm0ctl0 tmm0 control register 0 timer 378 tm0eqic0 interrupt control register intc 651 tp0ccic0 interrupt control register intc 651 tp0ccic1 interrupt control register intc 651 tp0ccr0 tmp0 capture/compare register 0 timer 198 tp0ccr1 tmp0 capture/compare register 1 timer 200 tp0cnt tmp0 counter read buffer register timer 202 tp0ctl0 tmp0 control register 0 timer 192 tp0ctl1 tmp0 control register 1 timer 192 tp0ioc0 tmp0 i/o control register 0 timer 194 tp0ioc1 tmp0 i/o control register 1 timer 195 tp0ioc2 tmp0 i/o control register 2 timer 196 tp0opt0 tmp0 option register 0 timer 197 tp0ovic interrupt control register intc 651 tp1ccic0 interrupt control register intc 651 tp1ccic1 interrupt control register intc 651 tp1ccr0 tmp1 capture/compare register 0 timer 198 tp1ccr1 tmp1 capture/compare register 1 timer 200 tp1cnt tmp1 counter read buffer register timer 202 tp1ctl0 tmp1 control register 0 timer 192 tp1ctl1 tmp1 control register 1 timer 192 tp1ioc0 tmp1 i/o control register 0 timer 194 tp1ioc1 tmp1 i/o control register 1 timer 195 tp1ioc2 tmp1 i/o control register 2 timer 196 tp1opt0 tmp1 option register 0 timer 197 tp1ovic interrupt control register intc 651 tp2ccic0 interrupt control register intc 651 tp2ccic1 interrupt control register intc 651 tp2ccr0 tmp2 capture/compare register 0 timer 198 tp2ccr1 tmp2 capture/compare register 1 timer 200 tp2cnt tmp2 counter read buffer register timer 202 tp2ctl0 tmp2 control register 0 timer 192 tp2ctl1 tmp2 control register 1 timer 192 tp2ioc0 tmp2 i/o control register 0 timer 194 tp2ioc1 tmp2 i/o control register 1 timer 195 tp2ioc2 tmp2 i/o control register 2 timer 196 tp2opt0 tmp2 option register 0 timer 197 tp2ovic interrupt control register intc 651 tp3ccic0 interrupt control register intc 651 tp3ccic1 interrupt control register intc 651 tp3ccr0 tmp3 capture/compare register 0 timer 198 tp3ccr1 tmp3 capture/compare register 1 timer 200
v850es/jg3 appendix c register index r01uh0015ej0300 rev.3.00 page 822 of 870 sep 30, 2010 (9/10) symbol name unit page tp3cnt tmp3 counter read buffer register timer 202 tp3ctl0 tmp3 control register 0 timer 192 tp3ctl1 tmp3 control register 1 timer 192 tp3ioc0 tmp3 i/o control register 0 timer 194 tp3ioc1 tmp3 i/o control register 1 timer 195 tp3ioc2 tmp3 i/o control register 2 timer 196 tp3opt0 tmp3 option register 0 timer 197 tp3ovic interrupt control register intc 651 tp4ccic0 interrupt control register intc 651 tp4ccic1 interrupt control register intc 651 tp4ccr0 tmp4 capture/compare register 0 timer 198 tp4ccr1 tmp4 capture/compare register 1 timer 200 tp4cnt tmp4 counter read buffer register timer 202 tp4ctl0 tmp4 control register 0 timer 192 tp4ctl1 tmp4 control register 1 timer 192 tp4ioc0 tmp4 i/o control register 0 timer 194 tp4ioc1 tmp4 i/o control register 1 timer 195 tp4ioc2 tmp4 i/o control register 2 timer 196 tp4opt0 tmp4 option register 0 timer 197 tp4ovic interrupt control register intc 651 tp5ccic0 interrupt control register intc 651 tp5ccic1 interrupt control register intc 651 tp5ccr0 tmp5 capture/compare register 0 timer 198 tp5ccr1 tmp5 capture/compare register 1 timer 200 tp5cnt tmp5 counter read buffer register timer 202 tp5ctl0 tmp5 control register 0 timer 192 tp5ctl1 tmp5 control register 1 timer 192 tp5ioc0 tmp5 i/o control register 0 timer 194 tp5ioc1 tmp5 i/o control register 1 timer 195 tp5ioc2 tmp5 i/o control register 2 timer 196 tp5opt0 tmp5 option register 0 timer 197 tp5ovic interrupt control register intc 651 tq0ccic0 interrupt control register intc 651 tq0ccic1 interrupt control register intc 651 tq0ccic2 interrupt control register intc 651 tq0ccic3 interrupt control register intc 651 tq0ccr0 tmq0 capture/compare register 0 timer 287 tq0ccr1 tmq0 capture/compare register 1 timer 289 tq0ccr2 tmq0 capture/compare register 2 timer 291 tq0ccr3 tmq0 capture/compare register 3 timer 293 tq0cnt tmq0 counter read buffer register timer 295 tq0ctl0 tmq0 control register 0 timer 281 tq0ctl1 tmq0 control register 1 timer 282 tq0ioc0 tmq0 i/o control register 0 timer 283
v850es/jg3 appendix c register index r01uh0015ej0300 rev.3.00 page 823 of 870 sep 30, 2010 (10/10) symbol name unit page tq0ioc1 tmq0 i/o control register 1 timer 284 tq0ioc2 tmq0 i/o control register 2 timer 285 tq0opt0 tmq0 option register 0 timer 286 tq0ovic interrupt control register intc 651 ua0ctl0 uarta0 control register 0 uart 453 ua0ctl1 uarta0 control register 1 uart 476 ua0ctl2 uarta0 control register 2 uart 478 ua0opt0 uarta0 option control register 0 uart 455 ua0ric interrupt control register intc 651 ua0rx uarta0 receive data register uart 458 ua0str uarta0 status register uart 456 ua0tic interrupt control register intc 651 ua0tx uarta0 transmit data register uart 458 ua1ctl0 uarta1 control register 0 uart 453 ua1ctl1 uarta1 control register 1 uart 476 ua1ctl2 uarta1 control register 2 uart 478 ua1opt0 uarta1 option control register 0 uart 455 ua1ric interrupt control register intc 651 ua1rx uarta1 receive data register uart 458 ua1str uarta1 status register uart 453 ua1tic interrupt control register intc 651 ua1tx uarta1 transmit data register uart 458 ua2ctl0 uarta2 control register 0 uart 456 ua2ctl1 uarta2 control register 1 uart 476 ua2ctl2 uarta2 control register 2 uart 478 ua2opt0 uarta2 option control register 0 uart 455 ua2ric interrupt control register intc 651 ua2rx uarta2 receive data register uart 458 ua2str uarta2 status register uart 456 ua2tic interrupt control register intc 651 ua2tx uarta2 transmit data register uart 458 vswc system wait control register cpu 61 wdte watchdog timer enable register wdt 397 wdtm2 watchdog timer mode register 2 wdt 396, 556 wtic interrupt control register intc 651 wtiic interrupt control register intc 651 wtm watch timer operation mode register wt 389
v850es/jg3 appendix d instruction set list r01uh0015ej0300 rev.3.00 page 824 of 870 sep 30, 2010 appendix d instruction set list d.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the remainders of division resu lts and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the conditions code sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list
v850es/jg3 appendix d instruction set list r01uh0015ej0300 rev.3.00 page 825 of 870 sep 30, 2010 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword half word (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols used in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency).
v850es/jg3 appendix d instruction set list r01uh0015ej0300 rev.3.00 page 826 of 870 sep 30, 2010 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition code (cccc) condition formula explanation 0 0 0 0 ov = 1 overflow 1 0 0 0 ov = 0 no overflow 0 0 0 1 cy = 1 carry lower (less than) 1 0 0 1 cy = 0 no carry not lower (greater than or equal) 0 0 1 0 z = 1 zero 1 0 1 0 z = 0 not zero 0 0 1 1 (cy or z) = 1 not higher (less than or equal) 1 0 1 1 (cy or z) = 0 higher (greater than) 0 1 0 0 s = 1 negative 1 1 0 0 s = 0 positive 0 1 0 1 ? always (unconditional) 1 1 0 1 sat = 1 saturated 0 1 1 0 (s xor ov) = 1 less than signed 1 1 1 0 (s xor ov) = 0 greater than or equal signed 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed 1 1 1 1 ((s xor ov) or z) = 0 greater than signed
v850es/jg3 appendix d instruction set list r01uh0015ej0300 rev.3.00 page 827 of 870 sep 30, 2010 d.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 r r r r r 0 1 0 010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 11 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 11 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 11 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 44 4 bit#3,disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 r r r r r 1 1 1 111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 11 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 11 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 r r r r r 0 1 0 011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 3 3 3 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 3 3 3 r r r r r
v850es/jg3 appendix d instruction set list r01uh0015ej0300 rev.3.00 page 828 of 870 sep 30, 2010 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (restored pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 33 3 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 22 2 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 11 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 11 note 11
v850es/jg3 appendix d instruction set list r01uh0015ej0300 rev.3.00 page 829 of 870 sep 30, 2010 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 11 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 11 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 11 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 r r r r r 0 1 0 000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 14 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 14 5 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 11 2 mulh imm5,reg2 r r r r r 0 1 0 111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 11 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 11 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 14 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 14 5 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3
v850es/jg3 appendix d instruction set list r01uh0015ej0300 rev.3.00 page 830 of 870 sep 30, 2010 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) sp sp+4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend (imm5) ep sp/imm n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 3 3 3 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 11 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 11 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 11 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 11 1
v850es/jg3 appendix d instruction set list r01uh0015ej0300 rev.3.00 page 831 of 870 sep 30, 2010 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 11 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 11 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 11 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 11 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 11 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 11 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 11 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 11 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 11 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 11 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 11 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], halfword) 11 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 11 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1
v850es/jg3 appendix d instruction set list r01uh0015ej0300 rev.3.00 page 832 of 870 sep 30, 2010 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,halfword)) logically shift left by 1 55 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 11 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 11 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 33 3 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (accord ing to the number of wait st ates. also, if there are no wait states, n is the total number of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states).
v850es/jg3 appendix d instruction set list r01uh0015ej0300 rev.3.00 page 833 of 870 sep 30, 2010 notes 12. in this instruction, for convenience of mnemonic descrip tion, the source register is made reg2, but the reg1 field is used in the opcode. theref ore, the meaning of register specif ication in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8.
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 834 of 870 sep 30, 2010 appendix e list of cautions this appendix lists cautions described in this document. ?classification (hard/soft)? in table is as follows. hard: cautions for microcontroller internal/external hardware soft: cautions for software such as register settings or programs (1/36) chapter classification function details of function cautions page flmd0 connect these pins to v ss in the normal mode. p. 5 chapter 1 hard introduction regc connect the regc pin to v ss via a 4.7 f (recommended value) capacitor. p. 5 soft p05 incorporates a pull-down resistor. it can be disconnected by clearing the ocdm.ocdm0 bit to 0. p. 11 hard ddo in the on-chip debug mode, high-level output is forcibly set. p. 15 kr0 to kr7 pull this pin up externally. p. 16 soft nmi the nmi pin alternately functions as the p02 pin. it functions as the p02 pin after reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1. the initial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge using intf0 and intr0 registers. p. 16 chapter 2 hard pin functions when power is turned on when the power is turned on, the following pin may output an undefined level temporarily, even during reset. ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin p. 24 eipc register, eipsw register, fepc register, fepsw register because only one set of these registers is available, the contents of these registers must be saved by program if multiple interrupts are enabled. p. 28 eipc, fepc, ctpc registers even if eipc or fepc, or bit 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti instruction after interrupt servicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). p. 28 program space because the 4 kb area of addresses 03fff000h to 03ffffffh is an on-chip peripheral i/o area, instructions cannot be fetched from this area. therefore, do not execute an operation in which the result of a branch address calculation affects this area. p. 36 when a register is accessed in word uni ts, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. p. 43 if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read, and data is written to the lower 8 bits. p. 43 on-chip peripheral i/o area addresses not defined as registers ar e reserved for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. p. 43 chapter 3 soft cpu functions internal ram area if a branch instruction is at the upper limit of the internal ram area, a prefetch operation (invalid fetch) straddling t he on-chip peripheral i/o area does not occur. p. 44
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 835 of 870 sep 30, 2010 (2/36) chapter classification function details of function cautions page five nop instructions or more must be inserted immediately after setting the idle1 mode, idle2 mode, or stop mode (by setting the psc.stp bit to 1). p. 58 when a store instruction is executed to store data in the command register, interrupts are not acknowledged. this is because it is assumed that steps <3> and <4> above are performed by successive store instructions. if another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, c ausing malfunction. p. 58 setting data to special registers although dummy data is written to the prcmd register, use the same general- purpose register used to set t he special register (<4> in example) to write data to the prcmd register (<3> in exam ple). the same applies when a general- purpose register is used for addressing. p. 58 if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcmd register, the prerr bit is cleared to 0 (the write access takes precedence). p. 60 sys register if data is written to the prcmd register, which is not a special register, immediately after a write access to the p rcmd register, the prerr bit is set to 1. p. 60 registers to be set first be sure to set the following regist ers first when using the v850es/jg3. ? system wait control register (vswc) ? on-chip debug mode register (ocdm) ? watchdog timer mode register 2 (wdtm2) p. 61 vswc register three clocks are required to access an on-chip peripheral i/o register (without a wait cycle). the v850es/jg3 requires wait cycles according to the operating frequency. set the following value to the vswc register in accordance with the frequency used. p. 61 chapter 3 soft cpu functions accessing specific on-chip peripheral i/o registers accessing the above registers is prohibit ed in the following statuses. if a wait cycle is generated, it can only be cleared by a reset. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 62 hard basic port configuration ports 0, 3 to 5, and 9 are 5 v tolerant. p. 70 soft pfn register the pfnm bit of the pfn register is valid only when the pmnm bit of the pmn register is 0 (when the output mode is s pecified) in port mode (pmcnm bit = 0). when the pmnm bit is 1 (when the input m ode is specified), the set value of the pfn register is invalid. p. 68 hard, soft the drst pin is used for on-chip debugging. if on-chip debugging is not used, fix the p05/intp2/drst pin to low level between when the reset signal of the reset pin is released and when the ocdm.ocdm0 bit is cleared (0). for details, see 4.6.3 cautions on on-chip debug pins . p. 70 hard port 0 the p02 to p06 pins have hysteresis c haracteristics in the input mode of the alternate function, but do not have hyster esis characteristics in the port mode. p. 70 pmc0 register the p05/intp2/drst pin becomes the drst pin regardless of the value of the pmc05 bit when the ocdm.ocdm0 bit = 1. p. 71 pf0 register when an output pin is pulled up at ev dd or higher, be sure to set the pf0n bit to 1. p. 72 p1 register do not read or write the p1 register during d/a conversion (see 14.4.3 cautions ). p. 73 chapter 4 soft port functions pm1 register when using p1n as al ternate functions (anon pin output), set the pm1n bit to 1. p. 73
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 836 of 870 sep 30, 2010 (3/36) chapter classification function details of function cautions page soft pm1 register when using one of the p10 and p11 pins as an i/o port and the other as a d/a output pin, do so in an application where the port i/o level does not change during d/a output. p. 73 hard port 3 the p31 to p35, p38, and p39 pins hav e hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. p. 74 p3 register to read/write bits 8 to 15 of the p3 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the p3h register. p. 75 pm3 register to read/write bits 8 to 15 of the pm 3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm3h register. p. 75 be sure to set bits 15 to 10, 7, and 6 to ?0?. p. 76 pmc3 register to read/write bits 8 to 15 of the pmc3 regi ster in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc3h register. p. 76 pfc3 register to read/write bits 8 to 15 of the pf c3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc3h register. p. 77 pfce3l register be sure to set bits 7 to 3, 1, and 0 to ?0?. p. 77 pfc31/rxda0 input/intp7 input the intp7 pin and rxda0 pin are alternat e-function pins. when using the pin as the rxda0 pin, disable edge detection fo r the intp7 alternate-function pin. (clear the intf3.intf31 bit and the intr3 .intr31 bit to 0.) when using the pin as the intp7 pin, stop uarta0 recepti on. (clear the ua0ctl0.ua0rxe bit to 0.) p. 78 when an output pin is pulled up at ev dd or higher, be sure to set the pf3n bit to 1. p. 79 soft pf3 register to read/write bits 8 to 15 of the pf3 register in 8-bit or 1-bit uni ts, specify them as bits 0 to 7 of the pf3h register. p. 79 hard port 4 the p40 to p42 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. p. 80 soft pf4 register when an output pin is pulled up at ev dd or higher, be sure to set the pf4n bit to 1. p. 82 hard, soft the ddi, ddo, dck, and dms pins are used for on-chip debugging. if on-chip debugging is not used, fix the p05/intp2/drst pin to low level between when the reset signal of the reset pin is released and when the ocdm.ocdm0 bit is cleared (0). for details, see 4.6.3 cautions on on-chip debug pins . p. 83 when the power is turned on, the p53 pi n may output undefined level temporarily even during reset. p. 83 hard port 5 the p50 to p55 pins have hysteresis c haracteristics in the input mode of the alternate function, but do not have hyster esis characteristics in the port mode. p. 83 port 5 alternate function specifications the krn pin and tiq0m pin are alternate- function pins. when using the pin as the tiq0m pin, disable krn pin key retu rn detection, which is the alternate function. (clear the krm.krmn bit to 0. ) also, when using the pin as the krn pin, disable tiq0m pin edge detection, which is the alternate function (n = 0 to 3, m = 0 to 3). p. 86 pf5 register when an output pin is pulled up at ev dd or higher, be sure to set the pf5n bit to 1. p. 86 p7h register, p7l register do not read/write the p7h and p7l r egisters during a/d conversion (see 13.6 (4) alternate i/o ). p. 88 chapter 4 soft port functions pm7h register, pm7l register when using the p7n pin as its alternate functi on (anin pin), set the pm7n bit to 1. p. 88
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 837 of 870 sep 30, 2010 (4/36) chapter classification function details of function cautions page hard port 9 the p90 to p97, p99, p910, and p912 to p915 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. p. 89 p9 register to read/write bits 8 to 15 of the p9 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the p9h register. p. 90 pm9 register to read/write bits 8 to 15 of the pm 9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm9h register. p. 90 to read/write bits 8 to 15 of the pmc9 regi ster in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc9h register. p. 91 pmc9 register when using the a0 to a15 pins as the alte rnate functions of the p90 to p915 pins, set all 16 bits of the pmc9 register to ffffh at once. p. 92 pfc9 register, pfce9 register when performing separate address bus output (a0 to a15), set the pmc9 register to ffffh for all 16 bits at once after clearing the pfc9 or pfce9 register to 0000h. p. 93 pfc9 register to read/write bits 8 to 15 of the pf c9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc9h register. p. 93 pfce9 register to read/write bits 8 to 15 of the pfce9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfce9h register. p. 93 specification of port 9 alternate function the rxda1 and kr7 pins must not be used at the same time. when using the rxda1 pin, do not use the kr7 pin. when using the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear the pfce91 bit to 0). p. 95 when an output pin is pulled up at ev dd or higher, be sure to set the pf9n bit to 1. p. 96 pf9 register to read/write bits 8 to 15 of the pf9 register in 8-bit or 1-bit uni ts, specify them as bits 0 to 7 of the pf9h register. p. 96 pdl register to read/write bits 8 to 15 of the pdl register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pdlh register. p. 104 pmdl register to read/write bits 8 to 15 of the pm dl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmdlh register. p. 104 when the smsel bit of the eximc register = 1 (separate mode) and the bs30 to bs00 bits of the bsc register = 0 (8-bit bus width), do not specify the ad8 to ad15 pins. p. 105 pmcdl register to read/write bits 8 to 15 of the pmcdl r egister in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcdlh register. p. 105 the intp7 pin and rxda0 pin are alternat e-function pins. when using the pin as the rxda0 pin, disable edge detection for t he alternate-function intp7 pin (clear the intf3.intf31 bit and intr3.intr31 bit to 0). when using the pin as the intp7 pin, stop the uarta0 recepti on operation (clear the ua0ctl0.ua0rxe bit to 0). p. 137 when using one of the p10 and p11 pins as an i/o port and the other as a d/a output pin (ano0, ano1), do so in an application where the port i/o level does not change during d/a output. p. 137 when setting pins a0 to a15 as the alternat e function, set all 16 bits of the pmc9 register to ffffh at once. p. 140, 141 chapter 4 soft port functions using port pins as alternate- function pins the rxda1 and kr7 pins must not be used at the same time. when using the rxda1 pin, do not use the kr7 pin. when using the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear the pfce91 bit to 0). p. 140
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 838 of 870 sep 30, 2010 (5/36) chapter classification function details of function cautions page to switch from the port mode to alter nate-function mode in the following order. <1> set the pfn register note : n-ch open-drain setting <2> set the pfcn and pfcen registers: alternate-function selection <3> set the corresponding bit of the pmcn register to 1: switch to alternate- function mode if the pmcn register is set first, note with caution that, at that moment or depending on the change of the pin states in accordance with the setting of the pfn, pfcn, and pfcen registers, unexpected operations may occur. p. 144 cautions on switching from port mode to alternate- function mode regardless of the port mode/alternate-func tion mode, the pn register is read and written as follows. ? pn register read: read the port output latch value (when pmn.pmnm bit = 0), or read the pin states (pmn.pmnm bit = 1). ? pn register write: write to the port output latch p. 144 cautions on alternate- function mode (input) the input signal to the alternate-function block is low level when the pmcn.pmcnm bit is 0 due to the and output of the pmcn register set value and the pin level. thus, depending on the por t setting and alternatefunction operation enable timing, unexpected operations may occur. therefore, switch between the port mode and alternate-function mode in the following sequence. ? to switch from port mode to alternate-function mode (input) set the pins to the alternate-functi on mode using the pmcn register and then enable the alternatefunction operation. ? to switch from alternate-function mode (input) to port mode stop the alternate-function operation and then switch the pins to the port mode. p. 145 pfn.pfnm bit in port mode in port mode, the pfn.pfnm bit is valid only in the output mode (pmn.pmnm bit = 0). in the input mode (pmnm bit = 1), the value of the pfnm bit is not reflected in the buffer. p. 146 soft cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be wri tten in addition to the targeted bit. therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. p. 147 hard, soft the following action must be taken if on-chip debugging is not used. ? clear the ocdm0 bit of the ocdm register (special register) (0) at this time, fix the p05/intp2/drst pin to low level from when reset by the reset pin is released until the above action is taken. if a high level is input to the drst pin before the above action is taken, it may cause a malfunction (cpu deadlock). handle the p05 pin with the utmost care. p. 148 cautions on on- chip debug pins after reset by the wdt2res signal, clock monitor (clm), or low-voltage detector (lvi), the p05/intp2/drst pin is not initialized to function as an on-chip debug pin (drst). the ocdm register holds the current value. p. 148 cautions on p05/intp2/ drst pin the p05/intp2/drst pin has an internal pull-down resistor (30 k typ.). after a reset by the reset pin, a pull-down resistor is connected. the pull-down resistor is disconnected when the o cdm0 bit is cleared (0). p. 148 cautions on p53 pin when power is turned on when the power is turned on, the following pin may output an undefined level temporarily, even during reset. ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin p. 148 chapter 4 hard port functions hysteresis characteristics in port mode, the following port pins do not have hysteresis characteristics. p02 to p06 p31 to p35, p38, p39 p40 to p42 p50 to p55 p90 to p97, p99, p910, p912 to p915 p. 148
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 839 of 870 sep 30, 2010 (6/36) chapter classification function details of function cautions page pin status when internal rom when a write access is performed to the internal rom area, address, data, and control signals are activated in the same way as access to the external memory area. p. 150 eximc register set the eximc register from the internal rom or internal ram area before making an external access. after setting the eximc register, be sure to insert a nop instruction. p. 152 write to the bsc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the bsc register are complete. p. 153 bsc register be sure to set bits 14, 12, 10, and 8 to ?1?, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to ?0?. p. 153 the internal rom and internal ram areas are not subject to programmable wait, and are always accessed without a wait state. the on-chip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. p. 161 write to the dwc0 register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the dwc0 register are complete. p. 161 when the v850es/jg3 is used in separate bus mode and operated at f xx > 20 mhz, be sure to insert one or more waits. p. 161 dwc0 register be sure to clear bits 15, 11, 7, and 3 to ?0?. p. 161 address setup wait and address hold wait cycles are not inserted when the internal rom area, internal ram area, and on-chip peripheral i/o areas are accessed. p. 164 write to the awc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the awc register are complete. p. 164 when the v850es/jg3 is operated at f xx > 20 mhz, be sure to insert the address hold wait and the address setup wait. p. 164 awc register be sure to set bits 15 to 8 to ?1?. p. 164 the internal rom, internal ram, and on-ch ip peripheral i/o ar eas are not subject to idle state insertion. p. 165 write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the bcc register are complete. p. 165 chapter 5 soft bus control functions bcc register be sure to set bits 15, 13, 11, and 9 to ?1?, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to ?0?. p. 165 do not change the cpu clock (by using t he ck3 to ck0 bits) while clkout is being output. p. 179 use a bit manipulation instruction to m anipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. p. 179 when stopping the main clock, stop the pll. also stop the operations of the on- chip peripheral functions operating with the main clock. p. 180 if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied, then change to the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 p. 180 chapter 6 soft clock generation function pcc register enable operation of the on-chip peripheral functions operating with the main clock only after the oscillation of the main clock stabilizes. if their operations are enabled before the lapse of the oscillation stabilization time, a malfunction may occur. p. 181
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 840 of 870 sep 30, 2010 (7/36) chapter classification function details of function cautions page the internal oscillator cannot be stopped while the cpu is operating on the internal oscillation clock (ccls.cclsf bit = 1). do not set the rstop bit to 1. p. 182 rcm register the internal oscillator oscillates if the ccls.cclsf bit is set to 1 (when wdt overflow occurs during oscillation stabilization) even when the rstop bit is set to 1. at this time, the rstop bit remains being set to 1. p. 182 when the pllon bit is cleared to 0, the selpll bit is automatically cleared to 0 (clockthrough mode). p. 184 pllctl register the selpll bit can be set to 1 only when the pll clock frequency is stabilized. if not (unlocked), ?0? is written to the selpll bit if data is written to it. p. 184 the pll mode cannot be used at f x = 5.0 to 10.0 mhz. p. 185 before changing the multiplication fact or between 4 and 8 by using the ckc register, set the clock-through mode and stop the pll. p. 185 ckc register be sure to set bits 3 and 1 to ?1? and clear bits 7 to 4 and 2 to ?0?. p. 185 lockr register the lock register does not reflect the lock status of the pll in real time. p. 186 set so that the lockup time is 800 s or longer. p. 187 chapter 6 soft clock generation function plls register do not change the plls register setting during the lockup period. p. 187 set the tpncks2 to tpncks0 bits when the tpnce bit = 0. when the value of the tpnce bit is changed from 0 to 1, t he tpncks2 to tpncks0 bits can be set simultaneously. p. 192 tpnctl0 register be sure to clear bits 3 to 6 to ?0?. p. 192 the tpnest bit is valid only in the exte rnal trigger pulse output mode or one-shot pulse output mode. in any other mode, writing 1 to this bit is ignored. p. 193 external event count input is selected in the external event count mode regardless of the value of the tpneee bit. p. 193 set the tpneee and tpnmd2 to tpnmd0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) the operation is not guaranteed when rewriting is performed with the tpnce bit = 1. if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. p. 193 tpnctl1 register be sure to clear bits 3, 4, and 7 to ?0?. p. 193 rewrite the tpnol1, tpnoe1, tp nol0, and tpnoe0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. p. 194 tpnioc0 register even if the tpnolm bit is manipulated when the tpnce and tpnoem bits are 0, the topnm pin output level varies (m = 0, 1). p. 194 rewrite the tpnis3 to tpnis0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. p. 195 tpnioc1 register the tpnis3 to tpnis0 bits are valid only in the freerunning timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible. p. 195 rewrite the tpnees1, tpnees0, tpnets1, and tpnets0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. p. 196 chapter 7 soft 16-bit timer/ event counter p (tmp) tpnioc2 register the tpnees1 and tpnees0 bits are valid only when the tpnctl1.tpneee bit = 1 or when the external event count mode (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 bits = 001) has been set. p. 196
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 841 of 870 sep 30, 2010 (8/36) chapter classification function details of function cautions page tpnioc2 register the tpnets1 and tpnets0 bits are valid only when the external trigger pulse output mode (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 bits = 010) or the one- shot pulse output mode (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 = 011) is set. p. 196 rewrite the tpnccs1 and tpnccs0 bits when the tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. p. 197 tpnopt0 register be sure to clear bits 1 to 3, 6, and 7 to ?0?. p. 197 tpnccr0 register accessing the tpnccr0 register is prohi bited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 198 tpnccr1 register accessing the tpnccr1 register is prohi bited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 200 tpncnt register accessing the tpncnt register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 202 to use the external event count mode, s pecify that the valid edge of the tipn0 pin capture trigger input is not detected (by clearing the tpnioc1.tpnis1 and tpnioc1.tpnis0 bits to ?00?). p. 203 operation when using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tpnctl1.tpneee bit to 0). p. 203 interval timer mode (tpnmd2 to tpnmd0 bits = 000) this bit can be set to 1 only when the interrupt request signals (inttpncc0 and inttpncc1) are masked by the interrupt mask flags (tpnccmk0 and tpnccmk1) and timer output (topn1) is performed at the same time. however, set the tpnccr0 and tpnccr1 registers to the same value (see 7.5.1 (2) (d) operation of tpnccr1 register ). p. 205 notes on rewriting tpnccr0 register to change the value of the tpnccr0 regist er to a smaller value, stop counting once and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. p. 210 register setting for operation in external event count mode when an external clock is used as the count clock, the external clock can be input only from the tipn0 pin. at this time, set the tpnioc1.tpnis1 and tpnioc1.tpnis0 bits to 00 (capture tr igger input (tipn0 pin): no edge detection). p. 216 in the external event count mode, do not set the tpnccr0 register to 0000h. p. 218 external event count mode (tpnmd2 to tpnmd0 bits = 001) in the external event count mode, use of the timer output is disabled. if performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 bits = 000, tpnctl1.tpneee bit = 1). p. 218 chapter 7 soft 16-bit timer/ event counter p (tmp) notes on rewriting the tpnccr0 register to change the value of the tpnccr0 regist er to a smaller value, stop counting once and then change the set value. if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. p. 219
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 842 of 870 sep 30, 2010 (9/36) chapter classification function details of function cautions page tpnioc0, tpnoe0, tpnol0 bits clear this bit to 0 when the topn0 pin is not used in the external trigger pulse output mode. p. 224 note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccrm register after wr iting the tpnccr1 register after the inttpncc0 signal is detected. p. 228 tpnioc0.tpnoe0, tpnol0 bits clear this bit to 0 when the topn0 pin is not used in the one-shot pulse output mode. p. 236 register setting for operation in one-shot pulse output mode one-shot pulses are not output even in the one-shot pulse output mode, if the value set in the tpnccr1 register is greater than that set in the tpnccr0 register. p. 237 note on rewriting tpnccrm register to change the set value of the tpnccrm register to a smaller value, stop counting once, and then change the set value. if the value of the tpnccrm register is rewritten to a smaller value during counting, the 16-bit counter may overflow. p. 239 tpnioc0.tpnoe0, tpnol0 bits clear this bit to 0 when the topn0 pin is not used in the pwm output mode. p. 243 when using the selector function, be sure to set the port/timer alternate function pins for tmp to be connected to the capture trigger input. p. 274 selector function disable the peripheral i/os to be connected (tmp/uarta) before setting the selector function. p. 274 when setting the isel3 or isel4 bit to ?1?, be sure to set the corresponding alternate-function pin to the capture trigger input. p. 275 selcnt0 register be sure to clear bits 7 to 5, and 2 to 0 to ?0?. p. 275 chapter 7 soft 16-bit timer/ event counter p (tmp) capture operation when the capture operation is used and a sl ow clock is selected as the count clock, ffffh, not 0000h, may be captured in the tpnccr0 and tpnccr1 registers if the capture trigger is input i mmediately after the tpnce bit is set to 1. p. 276 set the tq0cks2 to tq0cks0 bits when the tq0ce bit = 0. when the value of the tq0ce bit is changed from 0 to 1, t he tq0cks2 to tq0cks0 bits can be set simultaneously. p. 281 tq0ctl0 register be sure to clear bits 3 to 6 to ?0?. p. 281 the tq0est bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. in any other mode, writing 1 to this bit is ignored. p. 282 external event count input is selected in the external event count mode regardless of the value of the tq0eee bit. p. 282 set the tq0eee and tq0md2 to tq0md0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when t he tq0ce bit = 1.) the operation is not guaranteed when rewriting is performed with the tq0ce bit = 1. if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. p. 282 tq0ctl1 register be sure to clear bits 3, 4, and 7 to ?0?. p. 282 rewrite the tq0olm and tq0oem bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0c e bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. p. 283 chapter 8 soft 16-bit timer/ event counter q (tmq) tq0ioc0 register even if the tq0olm bit is manipulated when the tq0ce and tq0oem bits are 0, the toq0m pin output level varies. p. 283
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 843 of 870 sep 30, 2010 (10/36) chapter classification function details of function cautions page rewrite the tq0is7 to tq0is0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0c e bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. p. 284 tq0ioc1 register the tq0is7 to tq0is0 bits are valid only in the freerunning timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible. p. 284 rewrite the tq0ees1, tq0ees0, tq0ets1, and tq0ets0 bits when the tq0ctl0.tq0ce bit = 0. (the same val ue can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. p. 285 the tq0ees1 and tq0ees0 bits are va lid only when the tq0ctl1.tq0eee bit = 1 or when the external event count mode (tq0ctl1.tq0md2 to tq0ctl1.tq0md0 bits = 001) has been set. p. 285 tq0ioc2 register the tq0ets1 and tq0ets0 bits are valid only when the external trigger pulse output mode (tq0ctl1.tq0md2 to tq0c tl1.tq0md0 bits = 010) or the one- shot pulse output mode (tq0ctl1.tq0md2 to tq0ctl1.tq0md0 = 011) is set. p. 285 rewrite the tq0ccs3 to tq0ccs0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0c e bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. p. 286 tq0opt0 register be sure to clear bits 1 to 3 to ?0?. p. 286 tq0ccr0 register accessing the tq0ccr0 register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 287 tq0ccr1 register accessing the tq0ccr1 register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 289 tq0ccr2 register accessing the tq0ccr2 register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 291 tq0ccr3 register accessing the tq0ccr3 register is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 293 tq0cnt register accessing the tq0cnt register is prohibit ed in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 295 chapter 8 soft 16-bit timer/ event counter q (tmq) external event count mode to use the external event count mode, specify that the valid edge of the tiq00 pin capture trigger input is not detec ted (by clearing the tq0ioc1.tq0is1 and tq0ioc1.tq0is0 bits to ?00?). p. 296
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 844 of 870 sep 30, 2010 (11/36) chapter classification function details of function cautions page external trigger pulse output mode, one-shot pulse output mode, pulse width measurement mode when using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tq0ctl1.tq0eee bit to 0). p. 296 tq0ctl1.tq0eee bit this bit can be set to 1 only when the interrupt request signals (inttq0cc0 and inttq0cck) are masked by the inte rrupt mask flags (tq0ccmk0 to tq0ccmkk) and the timer output (toq0k) is performed at the same time. however, the tq0ccr0 and tq0ccrk regist ers must be set to the same value (see 8.5.1 (2) (d) operation of tq0ccr1 to tq0ccr3 registers ) (k = 1 to 3). p. 298 notes on rewriting tq0ccr0 register to change the value of the tq0ccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tq0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. pp. 302, 311 register setting for operation in external event count mode when an external clock is used as the c ount clock, the external clock can be input only from the tiq00 pin. at this time, set the tq0ioc1.tq0is1 and tq0ioc1.tq0is0 bits to 00 (captur e trigger input (tiq00 pin): no edge detection). p. 308 in the external event count mode, do not set the tq0ccr0 register to 0000h. p. 310 external event count mode (tq0md2 to tq0md0 bits = 001) in the external event count mode, us e of the timer output is disabled. if performing timer output using external event count input, set the interval timer mode, and select the operation enabled by t he external event count input for the count clock (tq0ctl1.tq0md2 to tq0ctl1.tq0md0 bits = 000, tq0ctl1.tq0eee bit = 1). p. 310 tq0ioc0.tq0oe0, tq0ol0 bits clear this bit to 0 when the toq00 pin is not used in the external trigger pulse output mode. p. 318 note on changing pulse width during operation to change the pwm waveform while t he counter is operating, write the tq0ccr1 register last. rewrite the tq0ccrk register after wr iting the tq0ccr1 register after the inttq0cc0 signal is detected. p. 322 tq0ioc0.tq0oe0, tq0ol0 bits clear this bit to 0 when the toq00 pin is not used in the one-shot pulse output mode. p. 331 register setting for operation in one-shot pulse output mode one-shot pulses are not output even in the one-shot pulse output mode, if the value set in the tq0ccrk register is greater than that set in the tq0ccr0 register. p. 332 note on rewriting tq0ccrm register to change the set value of the tq0ccrm register to a smaller value, stop counting once, and then change the set value. if the value of the tq0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. p. 335 tq0ic0.tq0oe0, tq0ol0 bits clear this bit to 0 when the toq00 pi n is not used in the pwm output mode. p. 340 chapter 8 soft 16-bit timer/ event counter q (tmq) capture operation when the capture operation is used and a sl ow clock is selected as the count clock, ffffh, not 0000h, may be captured in the tq0ccr0, tq0ccr1, tq0ccr2, and tq0ccr3 registers if the c apture trigger is input immediately after the tq0ce bit is set to 1. p. 375
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 845 of 870 sep 30, 2010 (12/36) chapter classification function details of function cautions page set the tm0cks2 to tm0cks0 bits when tm0ce bit = 0. when changing the value of tm0ce from 0 to 1, it is not possible to set the value of the tm0cks2 to tm0cks0 bits simultaneously. p. 378 tm0ctl0 register be sure to clear bits 3 to 6 to ?0?. p. 378 pp. operation in interval timer mode do not set the tm0cmp0 register to ffffh. 379, 382 count start it takes the 16-bit counter up to the following time to start counting after the tm0ctl0.tm0ce bit is set to 1, depending on the count clock selected. p. 383 chapter 9 soft 16-bit interval timer m (tmm) tm0cmp0, tm0ctl0 registers rewriting the tm0cmp0 and tm0ctl0 regi sters is prohibited while tmm0 is operating. if these registers are rewritten while t he tm0ce bit is 1, the operation cannot be guaranteed. if they are rewritten by mistake, clear the tm0ctl0.tm0ce bit to 0, and re-set the registers. p. 383 do not change the values of the bgcs00 and bgcs01 bits during watch timer operation. p. 387 set the prsm0 register before setting the bgce0 bit to 1. p. 387 prsm0 register set the prsm0 and prscm0 registers according to the main clock frequency that is used so as to obtain an f brg frequency of 32.768 khz. p. 387 do not rewrite the prscm0 register during watch timer operation. p. 388 set the prscm0 register before setting the prsm0.bgce0 bit to 1. p. 388 prscm0 register set the prsm0 and prscm0 registers according to the main clock frequency that is used so as to obtain an f brg frequency of 32.768 khz. p. 388 wtm register rewrite the wtm2 to wtm7 bits while both the wtm0 and wtm1 bits are 0. p. 390 soft some time is required before the firs t watch timer interrupt request signal (intwt) is generated after operation is enabled (wtm.wtm1 and wtm.wtm0 bits = 1). p. 393 chapter 10 hard watch timer functions cautions it takes 0.515625 seconds (max.) for t he first intwt signal to be generated (2 9 1/32768 = 0.015625 seconds longer (max.)). the intwt signal is then generated every 0.5 seconds. p. 393 watchdog timer 2 automatically starts in the reset mode following reset release. when watchdog timer 2 is not used, eit her stop its operation before reset is executed via this function, or clear wa tchdog timer 2 once and stop it within the next interval time. also, write to the wdtm2 register for verification purposes only once, even if the default settings (reset mode, interval time: f r /2 19 ) do not need to be changed. p. 394 default-start watchdog timer for the non-maskable interrupt servici ng due to a non-maskable interrupt request signal (intwdt2), see 19.2.2 (2) from intwdt2 signal . p. 394 accessing the wdtm2 register is prohibit ed in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 396 for details of the wdcs20 to wdcs24 bits, see table 11-2 watchdog timer 2 clock selection . p. 396 chapter 11 soft watchdog timer 2 function wdtm2 register although watchdog timer 2 can be stopped just by stopping the operation of the internal oscillator, clear the wdtm2 register to 00h to securely stop the timer (to avoid selection of the main clock or subclock due to an erroneous write operation). p. 396
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 846 of 870 sep 30, 2010 (13/36) chapter classification function details of function cautions page if the wdtm2 register is rewritten twice a fter reset, an overflow signal is forcibly generated and the counter is reset. p. 396 to intentionally generate an overflow si gnal, write data to the wdtm2 register only twice, or write a value other than ?ach? to the wdte register only once. however, when watchdog timer 2 is set to stop operation, an overflow signal is not generated even if data is written to the wdtm2 register only twice, or a value other than ?ach? is written to the wdte register only once. p. 396 wdtm2 register to stop the operation of watchdog timer 2, set the rcm.rstop bit to 1 (to stop the internal oscillator) and write 00h in the wdtm2 register. if the rcm.rstop bit cannot be set to 1, set the wdcs23 bit to 1 (2 n /f xx is selected and the clock can be stopped in the idle1, idlw2, s ub-idle, and subclock operation modes). p. 396 when a value other than ?ach? is writt en to the wdte register, an overflow signal is forcibly output. p. 397 when a 1-bit memory manipulation instruct ion is executed for the wdte register, an overflow signal is forcibly output. p. 397 to intentionally generate an overflow signal , write a value other than ?ach? to the wdte register only once, or write dat a to the wdtm2 register only twice. however, when the watchdog timer 2 is se t to stop operation, an overflow signal is not generated even if data is written to the wdtm2 register only twice, or a value other than ?ach? is written to the wdte register only once. p. 397 chapter 11 soft watchdog timer 2 function wdte register the read value of the wdte register is ?9ah? (which differs from written value ?ach?). p. 397 when writing to bits 6 and 7 of the rtbh0 register, always write 0. p. 401 accessing the rtbl0 and rtbh0 registers is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 401 rtbl0, rtbh0 registers after setting the real-time output port, set output data to the rtbl0 and rtbh0 registers by the time a realti me output trigger is generated. p. 401 by enabling the real-time output operati on (rtpc0.rtpoe0 bit = 1), the bits enabled to real-time output among the rtp 00 to rtp05 signals perform realtime output, and the bits set to port mode output 0. p. 402 if real-time output is disabled (rtpoe0 bit = 0), the real-time output pins (rtp00 to rtp05) all output 0, regardless of the rtpm0 register setting. p. 402 rtpm0 register in order to use this register as the r eal-time output pins (rtp00 to rtp05), set these pins as real-time output port pi ns using the pmc and pfc registers. p. 402 rtpc0 register set the rtpeg0, byte0, and extr0 bits only when rtpoe0 bit = 0. p. 403 real-time output operation prevent the following c onflicts by software. ? conflict between real-time output dis able/enable switching (rtpoe0 bit) and selected real-time output trigger. ? conflict between writing to the rtbh0 and rtbl0 registers in the real-time output enabled status and the selected real-time output trigger. p. 405 initialization before performing initialization, disable real-time output (rtpoe0 bit = 0). p. 405 chapter 12 soft real-time output function (rto) rtbh0, rtbl0 registers once real-time output has been disabled (rtpoe0 bit = 0), be sure to initialize the rtbh0 and rtbl0 registers before enabling real-time output again (rtpoe0 bit = 0 1). p. 405
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 847 of 870 sep 30, 2010 (14/36) chapter classification function details of function cautions page hard ani0 to ani11 pins make sure that the voltages input to the ani0 to ani11 pins do not exceed the rated values. in particular if a voltage of av ref0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. p. 409 accessing the ada0m0 register is prohibit ed in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 411 a write operation to bit 0 is ignored. p. 411 changing the ada0m1.ada0fr2 to ada0m1.ada0fr0 bits is prohibited while a/d conversion is enabled (ada0ce bit = 1). p. 411 when writing data to the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft register in the following modes, stop the a/d conversion by clearing the ada0ce bit to 0. after the data is written to the register, enable the a/d conversion again by setting the ada0ce bit to 1. ? normal conversion mode ? one-shot select mode/one-shot sc an mode in high-speed conversion mode if the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written in the other modes during a/d conversion (ada0ef bit = 1), the following will be performed according to the mode. ? in software trigger mode a/d conversion is stopped and started again from the beginning. ? in hardware trigger mode a/d conversion is stopped, and the trigger standby status is set. p. 411 to select the external trigger mode/timer trigger mode (ada0tmd bit = 1), set the highspeed conversion mode (ada0m1.ada0hs1 bit = 1). do not input a trigger during stabilization time that is inserted once after the a/d conversion operation is enabled (ada0ce bit = 1). p. 411 ada0m0 register when not using the a/d converter, stop the operation by setting the ada0ce bit to 0 to reduce the power consumption. p. 411 changing the ada0m1 register is prohi bited while a/d conversion is enabled (ada0m0.ada0ce bit = 1). p. 412 to select the external trigger mode/ti mer trigger mode (ada0m0.ada0tmd bit = 1), set the high-speed conversion mode (ada0h s1 bit = 1). do not input a trigger during stabilization time that is inserted once after the a/d conversion operation is enabled (ada0ce bit = 1). p. 412 ada0m1 register be sure to clear bits 6 to 4 to ?0?. p. 412 set as 2.6 s conversion time 10.4 s. p. 413 chapter 13 soft a/d converter conversion time selection in normal conversion mode (ada0hs1 bit = 0) during a/d conversion, if the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written or trigger is input, reconversion is carried out. however, if the stabilization time end timing conflicts with the writing to these registers, or if the stabilization time end timing conflicts with the trigger input, the stabilization time of 64 clocks is reinserted. if a conflict occurs again with the reinserted stabilization time end timing, the stabilization time is reinserted. therefore do not set the trigger input interval and control register write interval to 64 clocks or below. p. 413
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 848 of 870 sep 30, 2010 (15/36) chapter classification function details of function cautions page set as 2.6 s conversion time 10.4 s. p. 414 conversion time selection in high-speed conversion mode (ada0hs1 bit = 1) in the high-speed conversion mode, rewrit ing of the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers and tri gger input are prohibited during the stabilization time. p. 414 when writing data to the ada0m2 register in the following modes, stop the a/d conversion by clearing the ad0m0.ada0ce bi t to 0. after the data is written to the register, enable the a/d conversion agai n by setting the ada0ce bit to 1. ? normal conversion mode ? one-shot select mode/one-shot sc an mode in high-speed conversion mode p. 415 ada0m2 register be sure to clear bits 7 to 2 to ?0?. p. 415 when writing data to the ada0s register in the following modes, stop the a/d conversion by clearing the ad0m0.ada0ce bi t to 0. after the data is written to the register, enable the a/d conversion agai n by setting the ada0ce bit to 1. ? normal conversion mode ? one-shot select mode/one-shot sc an mode in high-speed conversion mode p. 416 ada0s register be sure to clear bits 7 to 4 to ?0?. p. 416 accessing the ada0crn and ada0crnh registers is prohibited in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 417 ada0crn, ada0crnh registers a write operation to the ada0m0 and ada0 s registers may cause the contents of the ada0crn register to become undefi ned. after the conversion, read the conversion result before writing to the ada0m0 and ada0s registers. correct conversion results may not be read if a sequence other than the above is used. p. 417 in the select mode, the 8-bit data set to the ada0pft register is compared with the value of the ada0crnh register specified by the ada0s register. if the result matches the condition specif ied by the ada0pfc bit, t he conversion result is stored in the ada0crn register and the intad signal is generated. if it does not match, however, the interrupt signal is not generated. p. 419 in the scan mode, the 8-bit data set to the ada0pft register is compared with the contents of the ada0cr0h register. if the result matches the condition specified by the ada0pfc bit, the conversion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, however, the intad signal is not generated. regardless of the comparison result, the scan operation is continued and the conversion result is st ored in the ada0crn register until the scan operation is completed. however, the intad signal is not generated after the scan operation has been completed. p. 419 ada0pfm register when writing data to the ada0pfm register in the following modes, stop the a/d conversion by clearing the ad0m0.ada0ce bi t to 0. after the data is written to the register, enable the a/d conversion agai n by setting the ada0ce bit to 1. ? normal conversion mode ? one-shot select mode/one-shot sc an mode in high-speed conversion mode p. 419 chapter 13 soft a/d converter ada0pft register when writing data to the ada0pft register in the following modes, stop the a/d conversion by clearing the ad0m0.ada0ce bi t to 0. after the data is written to the register, enable the a/d conversion agai n by setting the ada0ce bit to 1. ? normal conversion mode ? one-shot select mode/one-shot sc an mode in high-speed conversion mode p. 420
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 849 of 870 sep 30, 2010 (16/36) chapter classification function details of function cautions page external trigger mode to select the external trigger mode, set the high-speed conversion mode. do not input a trigger during stabilization time that is inserted once after the a/d conversion operation is enabled (ada0m0.ada0ce bit = 1). p. 423 timer trigger mode to select the timer trigger mode, se t the high-speed conversion mode. do not input a trigger during stabilization time that is inserted once after the a/d conversion operation is enabled (ada0m0.ada0ce bit = 1). p. 424 when a/d converter is not used when the a/d converter is not used, t he power consumpti on can be reduced by clearing the ada0m0.ada0ce bit to 0. p. 434 input range of ani0 to ani11 pins input the voltage within the specified range to the ani0 to ani11 pins. if a voltage equal to or higher than av ref0 or equal to or lower than av ss (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undef ined, and the conversion value of the other channels may also be affected. p. 434 countermeasures against noise to maintain the 10-bit resolution, the ani0 to ani11 pins must be effectively protected from noise. the influence of noise increases as the output impedance of the analog input source becomes higher. to lower the noise, connecting an external capacitor as shown in figure 13-12 is recommended. p. 434 alternate i/o the analog input pins (ani0 to an i11) function alternately as port pins. when selecting one of the ani0 to ani11 pi ns to execute a/d conversion, do not execute an instruction to read an input port or write to an output port during conversion as the conver sion resolution may drop. also the conversion resolution may drop at the pins set as output port pins during a/d conversion if the output current fluct uates due to the effect of the external circuit connected to the port pins. if a digital pulse is applied to a pin adjac ent to the pin whose input signal is being converted, the a/d conversion value ma y not be as expected due to the influence of coupling noise. therefore, do not apply a pulse to a pin adjacent to the pin undergoing a/d conversion. p. 434 soft interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the ada0s register are changed. if the analog input pin is changed during a/d conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ada0s register is rewritten. if the adif flag is read immediately after the ada0s register is rewritten, the adif flag may be set even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d conversion is stopped, clear the adif flag before resuming conversion. p. 435 chapter 13 hard a/d converter av ref0 pin (a) the av ref0 pin is used as the power supply pin of the a/d converter and also supplies power to the alternate-function ports. in an application where a backup power supply is used, be sure to supply the same voltage as v dd to the av ref0 pin as shown in figure 13-15. (b) the av ref0 pin is also used as the referenc e voltage pin of the a/d converter. if the source supplying power to the av ref0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the current that flows during conversion (especially, immediately after the conversion oper ation enable bit ada0ce has been set to 1). as a result, the conversion accu racy may drop. to avoid this, it is recommended to connect a capacitor across the av ref0 and av ss pins to suppress the reference voltage fluct uation as shown in figure 13-15. (c) if the source supplying power to the av ref0 pin has a high dc resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the a/d conversion current. p. 436
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 850 of 870 sep 30, 2010 (17/36) chapter classification function details of function cautions page reading ada0crn register when the ada0m0 to ada0m2, ada0s, ada0pfm, or ada0pft register is written, the contents of the ada0crn register may be undefined. read the conversion result after completion of conversion and before writing to the ada0m0 to ada0m2, ada0s, ada0pfm, or ada0pft register. also, when an external/timer trigger is acknowledged, t he contents of the ada0crn register may be undefined. read the conversion result after completion of conversion and before the next external/timer trigger is acknowledged. the correct conversion result may not be read at a timing different from the above. p. 436 standby mode because the a/d conv erter stops operating in the stop mode, conversion results are invalid, so power consumption can be reduced. operations are resumed after the stop mode is released, but the a/d conversion results after the stop mode is released are invalid. when using the a/d converter after the stop mode is released, before setting the stop mode or releasing the stop mode, clear the ada0m0.ada0ce bit to 0 then set the ada0ce bit to 1 after releasing the stop mode. in the idle1, idle2, or subclock operat ion mode, operation continues. to lower the power consumption, therefore, clear the ada0m0.ada0ce bit to 0. in the idle1 and idle2 modes, since the analog input voltage value cannot be retained, the a/d conversion results after the idle1 and idle2 modes are released are invalid. the results of conversions before the idle1 and idle2 modes were set are valid. p. 436 high-speed conversion mode in the high-speed conversion mode, rewrit ing of the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers and trigger input during the stabilization time are prohibited. p. 437 a/d conversion time a/d conversion time is the total time of stabilization time, conversion time, wait time, and trigger response time (for details of these times, refer to table 13-2 conversion time selection in normal conversion mode (ada0hs1 bit = 0) and table 13-3 conversion time selection in high-speed conversion mode (ada0hs1 bit = 1) ). during a/d conversion in the normal conv ersion mode, if the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written or a trigger is input, reconversion is carried out. however, if the stabilization time end timing conflicts with the writing to these registers, or if the stabilization time end timing conflicts with the trigger input, the stabilization time of 64 clocks is reinserted. if a conflict occurs again with the reinserted stabilization time end timing, the stabilization time is reinserted. therefore do not set the trigger input interv al and control register write interval to 64 clocks or below. p. 437 soft variation of a/d conversion results the results of the a/d conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noi se. to reduce the variation, take counteractive measures wi th the program such as averaging the a/d conversion results. p. 437 chapter 13 hard a/d converter a/d conversion result hysteresis characteristics the successive comparison type a/d conv erter holds the analog input voltage in the internal sample & hold capacitor and then performs a/d conversion. after the a/d conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur. ? when the same channel is used for a/d conversions, if the voltage is higher or lower than the previous a/d conversion, then hysteresis characteristics may appear where the conversion result is a ffected by the previous value. thus, even if the conversion is performed at the same potential, the result may vary. ? when switching the analog input channel , hysteresis characteristics may appear where the conversion result is a ffected by the previous channel value. this is because one a/d converter is used for the a/ d conversions. thus, even if the conversion is performed at the same potential, the result may vary. p. 437
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 851 of 870 sep 30, 2010 (18/36) chapter classification function details of function cautions page dac0 and dac1 share the av ref1 pin. p. 442 d/a converter dac0 and dac1 share the av ss pin. the av ss pin is also shared by the a/d converter. p. 442 hard da0m register the output trigger in the real-t ime output mode (da0mdn bit = 1) is as follows. ? when n = 0: inttp2cc0 signal (see chapter 7 16-bit timer/event counter p (tmp) ) ? when n = 1: inttp3cc0 signal (see chapter 7 16-bit timer/event counter p (tmp) ) p. 443 da0cs0, da0cs1 registers in the real-time output mode (da0m.da0mdn bit = 1), set the da0csn register before the inttp2cc0/inttp3cc0 signals are generated. d/a conversion starts when the inttp2cc0/inttp3cc0 signals are generated. p. 444 do not change the set value of the da0csn register while the trigger signal is being issued in the real-time output mode. p. 446 before changing the operation mode, be sure to clear the da0m.da0cen bit to 0. p. 446 soft when using one of the p10/an00 and p11/an01 pins as an i/o port and the other as a d/a output pin, do so in an applic ation where the port i/o level does not change during d/a output. p. 446 make sure that av ref0 = v dd = av ref1 = 3.0 to 3.6 v. if this range is exceeded, the operation is not guaranteed. p. 446 apply power to av ref1 at the same timing as av ref0 . p. 446 hard no current can be output from the anon pin (n = 0, 1) because the output impedance of the d/a converter is high. when connecting a resistor of 2 m or less, insert a jfet input operational amplifier between the resistor and the anon pin. p. 446 chapter 14 soft d/a converter cautions because the d/a converte r stops operation in the stop mode, the ano0 and ano1 pins go into a highimpedance stat e, and the power consumption can be reduced. in the idle1, idle2, or subclock operation mode, however, the operation continues. to lower the power consumpti on, therefore, clear the da0m.da0cen bit to 0. p. 446 csib4 and uarta0 mode switching the transmit/receive operation of csib4 and uarta0 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. p. 447 uarta2 and i 2 c00 mode switching the transmit/receive operation of uarta2 and i 2 c00 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. p. 448 uarta1 and i 2 c02 mode switching the transmit/receive operation of uarta1 and i 2 c02 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. p. 449 uanopt0 register do not set the uansrt and uanstt bits (to 1) during sbf reception (uansrf bit = 1). p. 455 if sbf is transmitted during a data recept ion, a framing error occurs. p. 465 sbf reception do not set the sbf reception trigger bit (uansrt) and sbf transmission trigger bit (uanstt) to 1 during an sbf reception (uansrf = 1). p. 465 continuous transmission when initializing transmissions during the execution of continuous transmissions, make sure that the uanstr.uantsf bit is 0, then perform the initialization. transmit data that is initialized when the uantsf bit is 1 cannot be guaranteed. p. 466 chapter 15 soft asynchro- nous serial interface a (uarta) uart reception be sure to read the uanrx register even when a reception error occurs. if the uanrx register is not read, an overrun e rror occurs during reception of the next data, and reception errors continue occurring indefinitely. p. 470
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 852 of 870 sep 30, 2010 (19/36) chapter classification function details of function cautions page the operation during reception is perform ed assuming that there is only one stop bit. a second stop bit is ignored. p. 470 when reception is completed, read the uanrx register after the reception complete interrupt request signal (intuanr) has been generated, and clear the uanpwr or uanrxe bit to 0. if the uanpwr or uanrxe bit is cleared to 0 before the intuanr signal is generated, the read value of the uanrx register cannot be guaranteed. p. 470 uart reception if receive completion processing (intua nr signal generation) of uartan and the uanpwr bit = 0 or uanrxe bit = 0 conflict, the intuanr signal may be generated in spite of these being no data stored in the uanrx register. to complete reception without waiti ng intuanr signal generation, be sure to clear (0) the interrupt request flag (uanrif) of the uanric register, after setting (1) the interrupt mask flag (uanrmk) of the interrupt control register (uanric) and then set (1) the uanpwr bit = 0 or uanrxe bit = 0. p. 470 when an intuanr signal is generated, the uanstr register must be read to check for errors. p. 471 reception errors if a receive error interrupt occurs duri ng continuous reception, read the contents of the uanstr register must be read before the next reception is completed, then perform error processing. p. 472 lin function when using the lin function, fix the uanps1 and uanps0 bits of the uanctl0 register to 00. p. 473 uanctl1 register clear the uanctl0.uanpwr bit to 0 befor e rewriting the uanctl1 register. p. 476 uanctl2 register clear the uanctl0.uanpwr bit to 0 or clear the uantxe and uanrxe bits to 00 before rewriting the uanctl2 register. p. 477 the baud rate error during transmission must be within the error tolerance on the receiving side. p. 478 baud rate error the baud rate error during reception must satisfy the range indicated in (5) allowable baud rate range during reception. p. 478 allowable baud rate range during reception the baud rate error during reception must be set within the allowable error range using the following equation. p. 480 when the clock supply to uartan is stopped when the clock supply to uartan is stopped (for example, in idle1, idle2, or stop mode), the operation stops with eac h register retaining the value it had immediately before the cl ock supply was stopped. the txdan pin output also holds and outputs the value it had imm ediately before the clock supply was stopped. however, the operation is not guaranteed after the clock supply is resumed. therefore, after the clock s upply is resumed, the circuits should be initialized by setting the uanctl0.uanpwr, uanctl0.uanrxen, and uanctl0.uantxen bits to 000. p. 483 rxda1 pin kr7 pin the rxda1 and kr7 pins must not be used at the same time. to use the rxda1 pin, do not use the kr7 pin. to use the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear pfce91 bit to 0). p. 483 chapter 15 soft asynchro- nous serial interface a (uarta) performing the transfer of transmit data and receive data using dma transfer in uartan, the interrupt caused by a communication error does not occur. when performing the transfer of transmit data and receive data using dma transfer, error processing cannot be performed even if errors (parity, overrun, framing) occur during transfer. either read the ua nstr register after dma transfer has been completed to make sure that there are no errors, or read the uanstr register during communicati on to check for errors. p. 483
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 853 of 870 sep 30, 2010 (20/36) chapter classification function details of function cautions page start up uartan start up the uartan in the following sequence. <1> set the uanctl0.uanpwr bit to 1. <2> set the ports. <3> set the uanctl0.uantxe bit to 1, uanctl0.uanrxe bit to 1. p. 483 stop uartan stop the uartan in the following sequence. <1> set the uanctl0.uantxe bit to 0, uanctl0.uanrxe bit to 0. <2> set the ports and set the uanctl0.uanpwr bit to 0 (it is not a problem if port setting is not changed). p. 483 transmit mode in transmit mode (uanctl0.uanp wr bit = 1 and uanctl0.uantxe bit = 1), do not overwrite the same value to t he uantx register by software because transmission starts by writ ing to this register. to transmit the same value continuously, overwrite the same value. p. 483 chapter 15 soft asynchro- nous serial interface a (uarta) continuous transmission in continuous transmission, the communicati on rate from the stop bit to the next start bit is extended 2 base clocks more than usual. however, the reception side initializes the timing by detecting the star t bit, so the reception result is not affected. p. 483 csib4 and uarta0 mode switching the transmit/receive operation of csib4 and uarta0 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. p. 484 csib0 and i 2 c01 mode switching the transmit/receive operation of csib0 and i 2 c01 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. p. 485 to forcibly suspend transmission/reception, clear the cbnpwr bit to 0 instead of the cbnrxe and cbntxe bits. at this time, the clock output is stopped. p. 488 cbnctl0 register be sure to clear bits 3 and 2 to ?0?. p. 490 the cbnctl1 register can be rewritt en only when the cbnctl0.cbnpwr bit = 0. p. 491 cbnctl1 register set the communication clock (f cclk ) to 8 mhz or lower. p. 491 cbnctl2 register the cbnctl2 register can be rewritten only when the cbnctl0.cbnpwr bit = 0 or when both the cbntxe and cbnrxe bits = 0. p. 492 continuous transfer mode (master mode, transmission mode) in continuous transmission mode, the re ception completion interrupt request signal (intcbnr) is not generated. p. 509 continuous transfer mode (slave mode, transmission mode) in continuous transmission mode, the re ception completion interrupt request signal (intcbnr) is not generated. p. 518 clock timing in single transfer mode, writing to the cbntx register with the cbntsf bit set to 1 is ignored. this has no influence on the operation during transfer. for example, if the next data is written to the cbntx register when dma is started by generating the intcbnr signal, the wri tten data is not transferred because the cbntsf bit is set to 1. use the continuous transfer mode, not the single transfer mode, for such applications. p. 527 do not rewrite the prsmm register during operation. p. 530 prsm1 to prsm3 registers set the prsmm register before setting the bgcem bit to 1. p. 530 do not rewrite the prscmm register during operation. p. 531 chapter 16 soft 3-wire variable- length serial i/o (csib) prscm1 to prscm3 registers set the prscmm register before setting the prsmm.bgcem bit to 1. p. 531
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 854 of 870 sep 30, 2010 (21/36) chapter classification function details of function cautions page baud rage generation set f brgm to 8 mhz or lower. p. 531 when transferring transmit data and receive data using dma transfer when transferring transmit data and receiv e data using dma transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. check that the no overrun error has occurred by reading the cbnstr.cbnove bit after dma transfer has been completed. p. 532 cbnctl0 register cbnctl1 register cbnctl2 register in regards to registers that are forb idden from being rewritten during operations (cbnctl0.cbnpwr bit is 1), if rewrit ing has been carried out by mistake during operations, set the cbnctl0.cbnpwr bi t to 0 once, then initialize csibn. registers to which rewriting during oper ation are prohibited are shown below. ? cbnctl0 register: cbntxe, cbnrxe, cbndir, cbntms bits ? cbnctl1 register: cbnckp, cbndap, cbncks2 to cbncks0 bits ? cbnctl2 register: cbncl3 to cbncl0 bits p. 532 chapter 16 soft 3-wire variable- length serial i/o (csib) communication types 2, 4 in communication type 2 and 4 (cbnctl1.cbndap bit = 1), the cbnstr.cbntsf bit is cleared half a sckbn clock after occurrence of a reception complete interrupt (intcbnr). in the single transfer mode, writing the next transmit data is ignored during communication (cbntsf bit = 1), and the nex t communication is not started. also if reception-only communication (cbn ctl0.cbntxe bit = 0, cbnctl0.cbnrxe bit = 1) is set, the next communication is not started even if the receive data is read during communication (cbntsf bit = 1). therefore, when using the single transfe r mode with communication type 2 or 4 (cbndap bit = 1), pay particular attention to the following. ? to start the next transmission, confirm that cbntsf bit = 0 and then write the transmit data to the cbntx register. ? to perform the next reception conti nuously when reception-only communication (cbntxe bit = 0, cbnrxe bit = 1) is set, confirm that cbntsf bit = 0 and then read the cbnrx register. or, use the continuous transfer mode inst ead of the single transfer mode. use of the continuous transfer mode is re commend especially for using dma. p. 532 i 2 c bus to use the i 2 c bus function, use the p38/sda00, p39/scl00, p40/sda01, p41/scl01, p90/sda02, and p91/scl02 pins as the serial transmit/receive data i/o pins (sda00 to sda02) and serial clock i/o pins (scl00 to scl02), respectively, and set them to n-ch open-drain output. p. 533 uarta2 and i 2 c00 mode switching the transmit/receive operation of uarta2 and i 2 c00 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. p. 533 csib0 and i 2 c01 mode switching the transmit/receive operation of csib0 and i 2 c01 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. p. 534 uarta1 and i 2 c02 mode switching the transmit/receive operation of uarta1 and i 2 c02 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. p. 535 chapter 17 soft i 2 c bus iicc0 to iicc2 registers if the i 2 cn operation is enabled (iicen bit = 1) when the scl0n line is high level and the sda0n line is low level, the star t condition is detected immediately. to avoid this, after enabling the i 2 cn operation, immediately set the lreln bit to 1 with a bit manipulation instruction. p. 542
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 855 of 870 sep 30, 2010 (22/36) chapter classification function details of f unction cautions page set the sptn bit to 1 only in master mode. however, when the iicrsvn bit is 0, the sptn bit must be set to 1 and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see 17.15 cautions . p. 545 iicc0 to iicc2 registers when the trcn bit = 1, the wreln bit is set to 1 during the ninth clock and the wait state is canceled, after which t he trcn bit is cleared to 0 and the sda0n line is set to high impedance. p. 545 accessing the iicsn register is prohibit ed in the following statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 546 iics0 to iics2 registers the trcn bit is cleared to 0 and sda0n line becomes high impedance when the wreln bit is set to 1 and the wait state is canceled to 0 at the ninth clock by trcn bit = 1. p. 547 write the stcenn bit only when operation is stopped (iicen bit = 0). p. 550 when the stcenn bit = 1, the bus released status (iicbsyn bit = 0) is recognized regardless of the actual bus status immediately after the i 2 cn bus operation is enabled. therefore, to issue t he first start condition (sttn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. p. 550 iicf0 to iicf2 registers write the iicrsvn bit only when operation is stopped (iicen bit = 0). p. 550 iiccl0 to iiccl2 registers be sure to clear bits 7 and 6 to ?0?. p. 551 since the selection clock is f xx regardless of the value set to the ocks0 register, clear the ocks0 register to 00h (i 2 c division clock stopped status). p. 553 i 2 c0n transfer clock setting method since the selection clock is f xx regardless of the value set to the ocks1 register, clear the ocks1 register to 00h (i 2 c division clock stopped status). p. 554 start condition when the iiccn.iicen bit of the v850es/jg3 is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. be sure to set the iiccn.iicen bit to 1 when the scl0n and sda0n lines are high level. p. 558 when the iiccn.wtimn bit = 1, an intiicn signal occurs at the falling edge of the ninth clock. when the wtimn bit = 0 and the extension code?s slave address is received, an intiicn signal occurs at the falling edge of the eighth clock (n = 0 to 2). p. 590 status during arbitration and interrupt request signal generation timing when there is a possibility that arbitration will occur, set the spien bit to 1 for master device operation (n = 0 to 2). p. 590 when iicfn.stcenn bit = 0 immediately after the i 2 c0n operation is enabled, the bus communication status (iicfn.iicbsyn bit = 1) is recognized regar dless of the actual bus status. to execute master communication in the status where a stop condition has not been detected, generate a stop conditi on and then release the bus before starting the master communication. use the following sequence for generating a stop condition. <1> set the iiccln register. <2> set the iiccn.iicen bit. <3> set the iiccn.sptn bit. p. 596 chapter 17 soft i 2 c bus when iicfn.stcenn bit = 1 immediately after i 2 c0n operation is enabled, the bus released status (iicbsyn bit = 0) is recognized regardless of the actual bus status. to generate the first start condition (iiccn.sttn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. p. 596
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 856 of 870 sep 30, 2010 (23/36) chapter classification function details of function cautions page when communication among other devices are in progress when the iiccn.iicen bit of the v850es/jg3 is set to 1 while communications among other devices are in progress, the start condition may be detected depending on the status of the communication line. be sure to set the iiccn.iicen bit to 1 when the scl0n and sda0n lines are high level. p. 596 operation enable determine the operation clock frequency by the iiccln, iicxn, and ocksm registers before enabling the operation (iiccn.iicen bit = 1). to change the operation clock frequency, clear the iiccn.iicen bit to 0 once. p. 596 iiccn.sttn, sptn bits after the iiccn.sttn and iiccn.sptn bits have been set to 1, they must not be re-set without being cleared to 0 first. p. 596 transmission reservation if transmission has been reserved, set the iiccn.spien bit to 1 so that an interrupt request is generated by the det ection of a stop condition. after an interrupt request has been generated, the wait state will be released by writing communication data to i 2 cn, then transferring will begin. if an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait state because an interrupt request was not generated. however, it is not necessary to set the spien bit to 1 for the software to detect the iicsn.mstsn bit. p. 596 master operation in single master system release the i 2 c0n bus (scl0n, sda0n pins = high level) in conformity with the specifications of the product in communication. for example, when the eeprom outputs a low level to the sda0n pin, set the scl0n pin to the output port and output clock pulses from that output port until when the sda0n pin is constantly high level. p. 598 confirm that the bus release status (ii ccln.cldn bit = 1, iiccln.dadn bit = 1) has been maintained for a certain period (1 frame, for example). when the sda0n pin is constantly low level, det ermine whether to release the i 2 c0n bus (scl0n, sda0n pins = high level) by referring to the specifications of the product in communication. p. 599 conform the transmission and reception form ats to the specifications of the product in communication. p. 601 when using the v850es/jg3 as the master in the multimaster system, read the iicsn.mstsn bit for each intiicn interrupt occurrence to confirm the arbitration result. p. 601 master operation in multimaster system when using the v850es/jg3 as the slave in the multimaster system, confirm the status using the iicsn and iicfn register s for each intiicn interrupt occurrence to determine the next processing. p. 601 pp. slave wait cancellation to cancel slave wait, write ffh to iicn or set wreln. 606 to 608 pp. chapter 17 soft i 2 c bus master wait cancellation to cancel master wait, write ffh to iicn or set wreln. 609 to 611 be sure to clear bits 14 to 10 of the dsanh register to 0. p. 614 chapter 18 soft dma function (dma controller) dsa0 to dsa3 registers set the dsanh and dsanl registers at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initializati on by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer p. 614
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 857 of 870 sep 30, 2010 (24/36) chapter classification function details of function cautions page when the value of the dsan register is read, two 16-bit registers, dsanh and dsanl, are read. if reading and updating conflict, the value being updated may be read (see 18.13 cautions ). p. 614 dsa0 to dsa3 registers following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. p. 614 be sure to clear bits 14 to 10 of the ddanh register to 0. p. 615 set the ddanh and ddanl registers at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initializati on by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer p. 615 when the value of the ddan register is read, two 16-bit registers, ddanh and ddanl, are read. if reading and updating conflict, a value being updated may be read (see 18.13 cautions ). p. 615 dda0 to dda3 registers following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. p. 615 set the dbcn register at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initializati on by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer p. 616 dbc0 to dbc3 registers following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. p. 616 be sure to clear bits 15, 13 to 8, and 3 to 0 of the dadcn register to ?0?. p. 617 set the dadcn register at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initializati on by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer p. 617 the ds0 bit specifies the size of t he transfer data, and does not control bus sizing. if 8-bit data (ds0 bit = 0) is set, therefore, the lower data bus is not always used. p. 617 if the transfer data size is set to 16 bits (ds0 bit = 1), transfer cannot be started from an odd address. transfer is always star ted from an address with the first bit of the lower address aligned to 0. p. 617 chapter 18 soft dma function (dma controller) dadc0 to dadc3 registers if dma transfer is executed on an on-chip per ipheral i/o register (as the transfer source or destination), be sure to specify the same transfer size as the register size. for example, to execute dma transfe r on an 8-bit register, be sure to specify 8-bit transfer. p. 617
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 858 of 870 sep 30, 2010 (25/36) chapter classification function details of function cautions page the tcn bit is read-only. p. 618 the initn and stgn bits are write-only. p. 618 be sure to clear bits 6 to 3 of the dchcn register to 0. p. 618 dchc0 to dchc3 registers when dma transfer is completed (when a terminal count is generated), the enn bit is cleared to 0 and then the tcn bit is set to 1. if the dchcn register is read while its bits are being updated, a value indicating ?transfer not completed and transfer is disabled? (tcn bit = 0 and enn bit = 0) may be read. p. 618 do not set the dfn bit to 1 by software. wr ite 0 to this bit to clear a dma transfer request if an interrupt that is specified as the cause of starting dma transfer occurs while dma transfer is disabled. p. 619 set the ifcn5 to ifcn0 bits at the fo llowing timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initializati on by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer p. 619 an interrupt request that is generated in the standby mode (idel1, idle2, stop, or sub-idle mode) does not start the dma transfer cycle (nor is the dfn bit set to 1). p. 619 dtfr0 to dtfr3 registers if a dma start factor is selected by the ifc n5 to ifcn0 bits, the dfn bit is set to 1 when an interrupt occurs from the select ed on-chip peripheral i/o, regardless of whether the dma transfer is enabled or dis abled. if dma is enabled in this status, dma transfer is immediately started. p. 619 relationship between transfer targets the operation is not guaranteed for comb inations of transfer destination and source marked with ? ? in table 18-2. p. 621 two start factors (software trigger and hardware trigger) cannot be used for one dma channel. if two start factors ar e simultaneously generated for one dma channel, only one of them is valid. the start factor that is valid cannot be identified. p. 624 a new transfer request that is generated after the preceding dma transfer request was generated or in the preceding dma transfer cycle is ignored (cleared). p. 624 request by on- chip peripheral i/o the transfer request interval of the same dma channel varies depending on the setting of bus wait in the dma transfer cycle, the start status of the other channels, or the external bus hold request. in particular, as described in caution 2, a new transfer request that is generat ed for the same channel before the dma transfer cycle or during the dma transfer cycl e is ignored. therefore, the transfer request intervals for the same dma channel must be sufficiently separated by the system. when the software trigger is used, completion of the dma transfer cycle that was generated before can be check ed by updating the dbcn register. p. 624 chapter 18 soft dma function (dma controller) caution for vswc register when using the dmac, be sure to set an appropriate value, in accordance with the operating frequency, to the vswc register. when the default value (77h) of the vswc r egister is used, or if an inappropriate value is set to the vswc register, the operation is not correctly performed (for details of the vswc register, see 3.4.8 (1) (a) system wait control register (vswc)) . p. 630
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 859 of 870 sep 30, 2010 (26/36) chapter classification function details of function cautions page caution for dma transfer executed on internal ram when executing the following instructions located in the internal ram, do not execute a dma transfer that transfers data to/from the internal ram (transfer source/destination), because the cpu ma y not operate correctly afterward. ? bit manipulation instruction located in internal ram (set1, clr1, or not1) ? data access instruction to misali gned address located in internal ram conversely, when executing a dma transfer to transfer data to/from the internal ram (transfer source/destination), do not execute the above two instructions. p. 630 caution for reading dchcn.tcn bit the tcn bit is cleared to 0 when it is read, but it is not automatically cleared even if it is read at a specific timing. to accurately clear the tcn bit, add the following processing. (a) when waiting for completion of dma transfer by polling tcn bit confirm that the tcn bit has been set to 1 (after tcn bit = 1 is read), and then read the tcn bit three more times. (b) when reading tcn bit in interrupt servicing routine execute reading the tcn bit three times. p. 630 even if the initn bit is set to 1 when t he channel executing dma transfer is to be initialized, the channel may not be initializ ed. to accurately initialize the channel, execute either of the following two procedures. (a) temporarily stop transfer of all dma channels initialize the channel executing dma tr ansfer using the procedure in <1> to <7> below. note, however, that tcn bit is cleared to 0 when step <5> is executed. make sure that the other processing programs do not expect that the tcn bit is 1. <1> disable interrupts (di). <2> read the dchcn.enn bit of dma channels other than the one to be forcibly terminated, and transfer the value to a general-purpose register. <3> clear the enn bit of the dma c hannels used (including the channel to be forcibly terminated) to 0. to clear the enn bit of the last dma channel, execute the clear instruction twice. if the target of dma transfer (transfer source/destination) is the internal ram, execute the instruction three times. example: execute instructions in t he following order if channels 0, 1, and 2 are used (if the target of trans fer is not the internal ram). ? clear dchc0.e00 bit to 0. ? clear dchc1.e11 bit to 0. ? clear dchc2.e22 bit to 0. ? clear dchc2.e22 bit to 0 again. <4> set the initn bit of the channel to be forcibly terminated to 1. <5> read the tcn bit of each channel not to be forcibly terminated. if both the tcn bit and the enn bit read in <2> are 1 (logical product (and) is 1), clear the saved enn bit to 0. <6> after the operation in <5>, write the enn bit value to the dchcn register. <7> enable interrupts (ei). p. 631 be sure to execute step <5> above to prevent illegal setting of the enn bit of the channels whose dma transfer has been normally completed between <2> and <3>. p. 631 chapter 18 soft dma function (dma controller) dma transfer initialization procedure (setting dchcn.initn bit to 1) (b) repeatedly execute setting initn bit until transfer is forcibly terminated correctly <1> suppress a request from the dma request source of the channel to be forcibly terminated (stop operation of the on-chip peripheral i/o). <2> check that the dma transfer r equest of the channel to be forcibly terminated is not held pending, by using the dtfrn.dfn bit. if a dma transfer request is held pending, wait until execution of the pending request is completed. <3> when it has been confirmed that the dma request of the channel to be forcibly terminated is not held pending, clear the enn bit to 0. p. 632
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 860 of 870 sep 30, 2010 (27/36) chapter classification function details of function cautions page dma transfer initialization procedure (setting dchcn.initn bit to 1) <4> again, clear the enn bit of the channel to be forcibly terminated. if the target of transfer for the channel to be forcibly terminated (transfer source/destination) is the internal ram, execute this operation once more. <5> copy the initial number of trans fers of the channel to be forcibly terminated to a general-purpose register. <6> set the initn bit of the channel to be forcibly terminated to 1. <7> read the value of the dbcn register of the channel to be forcibly terminated, and compare it with the value copied in <5>. if the two values do not match, repeat operations <6> and <7>. p. 632 procedure of temporarily stopping dma transfer (clearing enn bit) stop and resume the dma transfer under execution using the following procedure. <1> suppress a transfer request from the dma request source (stop the operation of the on-chip peripheral i/o). <2> check the dma transfer request is not held pending, by using the dfn bit (check if the dfn bit = 0). if a request is pending, wait until ex ecution of the pending dma transfer request is completed. <3> if it has been confirmed that no dm a transfer request is held pending, clear the enn bit to 0 (this operation stops dma transfer). <4> set the enn bit to 1 to resume dma transfer. <5> resume the operation of the dma request source that has been stopped (start the operation of the onchip peripheral i/o). p. 632 memory boundary the operation is not guaranteed if the address of the transfer source or destination exceeds the area of the dma ta rget (external memory, internal ram, or on-chip peripheral i/o ) during dma transfer. p. 632 transferring misaligned data dma transfer of misaligned data with a 16-bit bus width is not supported. if an odd address is specified as the trans fer source or destination, the least significant bit of the address is forcibly assumed to be 0. p. 632 bus arbitration for cpu because the dma controller has a higher priority bus mastership than the cpu, a cpu access that takes place during dm a transfer is held pending until the dma transfer cycle is completed and the bus is released to the cpu. however, the cpu can access the exter nal memory, on-chip peripheral i/o, and internal ram to/from which dma transfer is not being executed. ? the cpu can access the internal ra m when dma transfer is being executed between the external memory and on-chip peripheral i/o. ? the cpu can access the internal ram and on-chip peripheral i/o when dma transfer is being executed between the ex ternal memory and external memory. p. 633 registers/bits that must not be rewritten during dma operation set the following registers at the following timing when a dma operation is not under execution. [registers] ? dsanh, dsanl, ddanh, ddanl, dbcn, and dadcn registers ? dtfrn.ifcn5 to dtfrn.ifcn0 bits [timing of setting] ? period from after reset to start of the first dma transfer ? time after channel initialization to start of dma transfer ? period from after completion of dma transfer (tcn bit = 1) to start of the next dma transfer p. 633 chapter 18 soft dma function (dma controller) dsanh register ddanh register dadcn register dchcn register be sure to set the following register bits to 0. ? bits 14 to 10 of dsanh register ? bits 14 to 10 of ddanh register ? bits 15, 13 to 8, and 3 to 0 of dadcn register ? bits 6 to 3 of dchcn register p. 633
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 861 of 870 sep 30, 2010 (28/36) chapter classification function details of function cautions page dma start factor do not start two or more dma channels with the same start factor. if two or more channels are started with the same fact or, dma for which a channel has already been set may be started or a dma channel with a lower priority may be acknowledged earlier than a dma channel wi th a higher priority. the operation cannot be guaranteed. p. 633 chapter 18 soft dma function (dma controller) read values of dsan and ddan registers values in the middle of updating may be read from the dsan and ddan registers during dma transfer (n = 0 to 3). for example, if the dsanh register and then the dsanl register are read when the dma transfer source address (dsan register) is 0000ffffh and the count direction is incremental (dadcn.sad1 and dadcn.sad0 bits = 00), the value of the dsan register differs as follo ws, depending on whether dma transfer is executed immediately after the dsanh register is read. (a) if dma transfer does not occur while dsan register is read <1> read value of dsanh register: dsanh = 0000h <2> read value of dsanl register: dsanl = ffffh (b) if dma transfer occurs while dsan register is read <1> read value of dsanh register: dsanh = 0000h <2> occurrence of dma transfer <3> incrementing dsan register: dsan = 00100000h <4> read value of dsanl register: dsanl = 0000h p. 634 for the non-maskable interrupt servicing executed by the non-maskable interrupt request signal (intwdt2), see 19.2.2 (2) from intwdt2 signal . p. 639 non-maskable interrupts when the ep and np bits are changed by the ldsr instruction during non- maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 0 and the np bit back to 1 using the ldsr in struction immediately before the reti instruction. p. 642 maskable interrupt when the ep and np bits are changed by t he ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 0 and the np bit back to 0 using the ldsr instruction i mmediately before the reti instruction. p. 646 multiple interrupt to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing t he ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. pp. 648 to 650 disable interrupts (di) or mask the interrupt to read the xxicn.xxifn bit. if the xxifn bit is read while interrupts are enabled (ei) or while the interrupt is unmasked, the correct value may not be read when acknowledging an interrupt and reading the bit conflict. p. 651 interrupt control register the flag xxlfn is reset automatically by the hardware if an interrupt request signal is acknowledged. p. 651 the device file defines the xxicn.xxmkn bit as a reserved word. if a bit is manipulated using the name of xxmkn, the contents of the xxicn register, instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten). p. 653 to read bits 8 to 15 of the imr0 to imr3 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of imr0h to imr3h registers. p. 653 chapter 19 soft interrupt/ exception processing function imr0 to imr3 registers set bits 7 to 15 of the imr3 register to 1. if the setting of these bits is changed, the operation is not guaranteed. p. 653
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 862 of 870 sep 30, 2010 (29/36) chapter classification function details of function cautions page ispr register if an interrupt is acknowledged wh ile the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after the bits of the register have been set by acknowledging the interrupt may be read. to accurately read the value of the ispr register bef ore an interrupt is acknowledged, read the register while interrupts are disabled (di). p. 655 restoration from software exception processing when the ep and np bits are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 1 and the np bit back to 0 using the ldsr instruction immediately before the reti instruction. p. 658 illegal opcode definition since it is possible to assign this instruct ion to an illegal opcode in the future, it is recommended that it not be used. p. 660 restoration from exception trap dbpc and dbpsw can be accessed only during the interval between the execution of an illegal opcode and the dbret instruction. p. 661 restoration from debug trap dbpc and dbpsw can be accessed only during the interval between the execution of the dbtrap instruction and the dbret instruction. p. 663 when the function is changed from the ex ternal interrupt function (alternate function) to the port function, an edge ma y be detected. therefore, clear the intf0n and intr0n bits to 00, and then set the port mode. p. 665 intf0, intr0 registers be sure to clear the intf0n and intr0n bits to 00 when these registers are not used as the nmi or intp0 to intp3 pins. p. 665 when the function is changed from the ex ternal interrupt function (alternate function) to the port function, an edge ma y be detected. therefore, clear the intf31 and intr31 bits to 00, and then set the port mode. p. 666 the intp7 pin and rxda0 pin are alternat e-function pins. when using the pin as the rxda0 pin, disable edge detection for t he intp7 alternate-function pin (clear the intf3.intf31 bit and the inrt3.intr31 bit to 0). when using the pin as the intp7 pin, stop uarta0 reception (c lear the ua0ctl0.ua0rxe bit to 0). p. 686 intf3, intr3 registers be sure to clear the intf31 and intr31 bits to 00 when these registers are not used as intp7 pin. p. 666 when the function is changed from the ex ternal interrupt function (alternate function) to the port function, an edge ma y be detected. therefore, clear the intf9n and intr9n bits to 0, and then set the port mode. p. 667 intf9h, intr9h registers be sure to clear the intf9n and intr9n bits to 00 when these registers are not used as intp4 to intp6 pins. p. 667 nfc register after the sampling clock has been changed, it takes 3 sampling clocks to initialize the digital noise eliminator. therefore, if an intp3 valid edge is input within these 3 sampling clocks after the sampling clock has been changed, an interrupt request signal may be generated. therefore, be careful about the following points when using the interrupt and dma functions. ? when using the interrupt function, after the 3 sampling clocks have elapsed, enable interrupts after the interrupt request flag (pic3.pif3 bit) has been cleared. ? when using the dma function (started by intp3), enable dma after 3 sampling clocks have elapsed. p. 668 chapter 19 soft interrupt/ exception processing function nmi pin the nmi pin and p02 pin are an alter nate-function pin, and function as a normal port pin after being reset. to enable the nm i pin, validate the nmi pin with the pmc0 register. the initial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge using the intf0 and intr0 registers. p. 670
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 863 of 870 sep 30, 2010 (30/36) chapter classification function details of function cautions page rewrite the krm register after once clearing the krm register to 00h. p. 672 krm register if the krm register is changed, an in terrupt request signal (intkr) may be generated. to prevent this, change the krm r egister after disabling interrupts (di) or masking, then clear the interrupt request flag (kric.krif bit) to 0, and enable interrupts (ei) or clear the mask. p. 672 kr0 to kr7 pins if a low level is input to any of the kr0 to kr7 pins, the intkr signal is not generated even if the falling edge of another pin is input. p. 672 rxda1 pin kr7 pin the rxda1 and kr7 pins must not be used at the same time. to use the rxda1 pin, do not use the kr7 pin. to use the kr7 pin, do not use the rxda1 pin (it is recommended to set the pfc91 bit to 1 and clear pfce91 bit to 0). p. 672 chapter 20 soft key interrupt function use the key interrupt function to use the key interrupt function, be sure to set the port pin to the key return pin and then enable the operation with the krm register. to switch from the key return pin to the port pin, disable the operation with the krm register and then set the port pin. p. 672 before setting the idle1, idle2, stop, or sub-idle mode, set the psmr.psm1 and psmr.psm0 bits and then set the stp bit. p. 675 settings of the nmi1m, nmi0m, and intm bits are invalid when halt mode is released. p. 675 psc register if the nmi1m, nmi0m, or intm bit is set to 1 at the same time the stp bit is set to 1, the setting of nmi1m, nmi0m, or intm bit becomes invalid. if there is an unmasked interrupt request signal being held pending when the idle1/idle2/stop mode is set, set the bit corresponding to the interrupt request signal (nmi1m, nmi0m, or intm) to 1, and then set the stp bit to 1. p. 675 be sure to clear bits 2 to 7 to ?0?. p. 676 psmr register the psm0 and psm1 bits are valid only when the psc.stp bit is 1. p. 676 the wait time following release of the stop mode does not include the time until the clock oscillation starts (?a? in the figure below) following release of the stop mode, regardless of whether the stop mode is released by reset or the occurrence of an interrupt request signal. p. 677 be sure to clear bits 3 to 7 to ?0?. p. 677 osts register the oscillation stabilization time following reset release is 2 16 /f x (because the initial value of the osts register = 06h). p. 677 insert five or more nop instruct ions after the halt instruction. p. 678 halt mode if the halt instruction is executed while an unmasked interrupt request signal is being held pending, the status shifts to halt mode, but the halt mode is then released immediately by the pending interrupt request. p. 678 insert five or more nop instructions afte r the instruction that stores data in the psc register to set the idle1 mode. p. 680 idle1 mode if the idle1 mode is set while an unmasked interrupt request signal is being held pending, the idle1 mode is released immediately by the pending interrupt request. p. 680 releasing idle1 mode an interrupt request signal that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and idle1 mode is not released. p. 680 insert five or more nop instructions afte r the instruction that stores data in the psc register to set the idle2 mode. p. 682 chapter 21 soft standby function idle2 mode if the idle2 mode is set while an unmasked interrupt request signal is being held pending, the idle2 mode is released immediately by the pending interrupt request. p. 682
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 864 of 870 sep 30, 2010 (31/36) chapter classification function details of function cautions page releasing idle2 mode the interrupt request signal that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and idle2 mode is not released. p. 682 insert five or more nop instructions afte r the instruction that stores data in the psc register to set the stop mode. p. 685 stop mode if the stop mode is set while an unmasked interrupt request signal is being held pending, the stop mode is released i mmediately by the pending interrupt request. p. 685 releasing stop mode the interrupt request that is disabl ed by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes inva lid and stop mode is not released. p. 685 when manipulating the ck3 bit, do not change the set values of the pcc.ck2 to pcc.ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details of the pcc register, see 6.3 (1) processor clock control register (pcc) . p. 689 subclock operation mode if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied and set the subclock operation mode. internal system clock (f clk ) > subclock (f xt = 32.768 khz) 4 p. 689 when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details of the pcc register, see 6.3 (1) processor clock control register (pcc) . p. 689 be sure to stop the pll (pllctl.pllon bit = 0) before stopping the main clock. p. 690 releasing subclock operation mode when the cpu is operating on the subclock and main clock oscillation is stopped, accessing a register in which a wait occurs is disabled. if a wait is generated, it can be released only by reset (see 3.4.8 (2) ). p. 690 following the store instruction to the psc register to set the sub-idle mode, insert the five or more nop instructions. p. 691 sub-idle mode if the sub-idle mode is set while an unm asked interrupt request signal is being held pending, the sub-idle mode is then released immediately by the pending interrupt request. p. 691 the interrupt request signal that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becom es invalid and sub-idle mode is not released. p. 691 releasing sub- idle mode when the sub-idle mode is released, 12 cycles of the subclock (about 366 s) elapse from when the interrupt request signal that releases the sub-idle mode is generated to when the mode is released. p. 691 be sure to stop the pll (pllctl.pllon bit = 0) before stopping the main clock. p. 692 chapter 21 soft standby function operating status in sub- idle mode to realize low power consumption, stop the a/d and d/a converters before shifting to the sub-idle mode. p. 692 emergency operation mode in emergency operation mode, do not acce ss on-chip peripheral i/o registers other than registers used for interrupts, por t function, wdt2, or timer m, each of which can operate with the internal oscillation clock. in addition, operation of csib0 to csib4 and uarta0 using the externally input clock is also prohibited in this mode. p. 693 reset function an lvi circuit internal reset does not reset the lvi circuit. p. 693 soft resf register only ?0? can be written to each bit of this register. if writ ing ?0? conflicts with setting the flag (occurrence of reset) , setting the flag takes precedence. p. 694 p. 695 chapter 22 hard reset function hardware status on reset pin input when the power is turned on, the following pin may output an undefined level temporarily, even during reset. ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 865 of 870 sep 30, 2010 (32/36) chapter classification function details of function cautions page chapter 22 hard, soft reset function hardware status on reset pin input the ocdm register is initialized by t he reset pin input. therefore, note with caution that, if a high level is input to the p05/drst pin after a reset release before the ocdm.ocdm0 bit is cleared, the on-chip debug mode is entered. for details, see chapter 4 port functions . p. 695 once the clme bit has been set to 1, it cannot be cleared to 0 by any means other than reset. p. 703 clm register when a reset by the clock monitor occurs, the clme bit is cleared to 0 and the resf.clmrf bit is set to 1. p. 703 the internal oscillator can be stopped by setting the rcm.rstop bit to 1. p. 704 the clock monitor is stopped while the internal oscillator is stopped. p. 704 chapter 23 soft clock monitor internal oscillator the internal oscillator cannot be stopped by software. p. 704 when the lvion and lvimd bits to 1, the low-voltage detector cannot be stopped until the reset request due to other than the low-voltage detection is generated. p. 708 when the lvion bit is set to 1, the compar ator in the lvi circuit starts operating. wait 0.2 ms or longer by software before checking the voltage at the lvif bit after the lvion bit is set. p. 708 lvim register be sure to clear bits 6 to 2 to ?0?. p. 708 this register cannot be written until a reset request due to something other than low-voltage detection is generated after the lvim.lvion and lvim.lvimd bits are set to 1. p. 709 lvis register be sure to clear bits 7 to 1 to ?0?. p. 709 to use for internal reset signal if the lvimd bit is set to 1, the contents of the lvim and lvis registers cannot be changed until a reset request other than lvi is generated. p. 710 to use for interrupt when the intlvi signal is generated, conf irm, using the lvim/lvif bit, whether the intlvi signal is generated due to a supply voltage drop or rise across the detected voltage. p. 711 chapter 24 soft low- voltage detector (lvi) pemu1 register this bit is not automatically cleared. p. 713 chapter 25 hard crc function crcd register accessing the crcd register is prohi bited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-chip peripheral i/o registers . ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock p. 715 chapter 26 hard regulator regulator use the regulator with a setting of v dd = ev dd = av ref0 = av ref1 . p. 719 pp. flmd1 pin connect the flmd1 pin to the flas h programmer or connect to a gnd via a pull- down resistor on the board. 727 to 729 wire these pins as shown in figure 27- 6, or connect then to gnd via pull-down resistor on board. p. 729 pg-fp4 clock cannot be supplied via the clk pin of the flash programmer. create an oscillator on board and supply the clock. p. 729 pp. be sure to connect the regc pin to gnd via a 4.7 f (recommended value) capacitor. 730, 731 pp. chapter 27 hard flash memory fa-144gj-uen-a a clock cannot be supplied from the clk pin of the flash programmer. create an oscillator on the board and supply the clock from that oscillator. 730, 731
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 866 of 870 sep 30, 2010 (33/36) chapter classification function details of function cautions page wire the flmd1 pin as shown below, or connect it to gnd on board via a pull- down resistor. p. 733 supply a clock by creating an oscillator on the flash writing adapter (enclosed by the broken lines). p. 733 fa-144gj-uen-a do not input a high level to the drst pin. p. 733 selection of communication mode when uarta0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the flmd0 pulse. p. 735 flmd1 pin if the v dd signal is input to the flmd1 pi n from another device during on-board writing and immediately after reset, isolate this signal. p. 737 chapter 27 hard flash memory flmd0 pin make sure that the flmd0 pin is at 0 v when reset is released. p. 744 when using the ddi, ddo, dck, and dms pins not as on-chip debug pins but as port pins after external reset, any of the following actions must be taken. ? input a low level to the p05/intp2/drst pin. ? set the ocdm0 bit. in this case, take the following actions. <1> clear the ocdm0 bit to 0. <2> fix the p05/intp2/drst pin to low level until <1> is completed. p. 750 hard, soft ocdm register the drst pin has an on-chip pull-down resi stor. this resistor is disconnected when the ocdm0 flag is cleared to 0. p. 750 if a reset signal is input (from the target system or a reset signal from an internal reset source) during run (program ex ecution), the break function may malfunction. p. 751 even if the reset signal is masked by the mask function, the i/o buffer (port pin) may be reset if a reset signal is input from a pin. p. 751 soft pin reset during a break is masked and t he cpu and peripheral i/o are not reset. if pin reset or internal reset is generated as soon as the flash me mory is rewritten by dmm or read by the ram monitor f unction while the user program is being executed, the cpu and peripheral i/o may not be correctly reset. p. 751 cautions (duc) in the on-chip debug mode, the ddo pin is forcibly set to the high-level output. p. 751 hard do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewr itten during debugging and the number of rewrites of the flash memory cannot be guaranteed. moreover, do not embed the debug moni tor program into mass-produced products. p. 760 forced breaks cannot be executed if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial inte rface, which is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby re lease by a maskable interrupt is prohibited ? mode for communication between minicube2 and the target device is uarta0, and the main clock has been stopped p. 760 chapter 28 soft on-chip debug function cautions (other than duc) the pseudo rrm function and dmm function do not operate if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial inte rface, which is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby re lease by a maskable interrupt is prohibited ? mode for communication between minicube2 and the target device is uarta0, and the main clock has been stopped ? mode for communication between minicube2 and the target device is uarta0, and a clock different from t he one specified in the debugger is used for communication p. 761
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 867 of 870 sep 30, 2010 (34/36) chapter classification function details of function cautions page the standby mode is released by the pseudo rrm function and dmm function if one of the following conditions is satisfied. ? mode for communication between minicube2 and the target device is csib0 or csib3 ? mode for communication between minicube2 and the target device is uarta0, and the main clock has been supplied. p. 761 peripheral i/o registers that requires a specific sequenc e cannot be written with the dmm function. p. 761 cautions (other than duc) if a space where the debug monitor program is allocated is rewritten by flash self programming, the debugger can no longer operate normally. p. 761 chapter 28 soft on-chip debug function security id after the flash memory is eras ed, 1 is written to the entire area. p. 762 be sure not to exceed the absolute maxi mum ratings (max. value) of each supply voltage. p. 765 do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open- collector pins, however, can be directly connected to each other. direct connection of the output pins bet ween an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. p. 766 absolute maximum ratings product quality may suffer if the absol ute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under c onditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. p. 766 the oscillation frequency shown above indicates only oscillator characteristics. use the v850es/jg3 so that the inter nal operation conditions do not exceed the ratings shown in ac characteristics and dc char acteristics. p. 768 time required to set up the flash memory. secure the setup time using the osts register. p. 768 hard when using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to av oid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a gr ound pattern through which a high current flows. ? do not fetch signals from the oscillator. p. 768 soft when the main clock is stopped and the devic e is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. p. 768 main clock oscillator characteristics for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. p. 768 chapter 29 hard electrical specifica- tions subclock oscillator characteristics the oscillation frequency shown above indicates only oscillator characteristics. use the v850es/jg3 so that the inter nal operation conditions do not exceed the ratings shown in ac characteristics and dc char acteristics. p. 770
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 868 of 870 sep 30, 2010 (35/36) chapter classification function details of function cautions page when using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a gr ound pattern through which a high current flows. ? do not fetch signals from the oscillator. p. 770 the subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillator. particular care is therefore required wi th the wiring method when the subclock is used. p. 770 subclock oscillator characteristics for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. p. 770 data retention characteristics shifting to stop mode and restoring from stop mode must be performed within the rated operating range. p. 775 hard ac characteristics if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. p. 776 bus timing (multiplexed bus mode) when operating at f xx > 20 mhz, be sure to insert address hold waits and address setup waits. p. 778 when operating at f xx > 20 mhz, be sure to insert address hold waits, address setup waits, and data waits. p. 783 bus timing (separate bus mode) the address may be changed during the low-level period of the rd pin. to avoid the address change, insert an address wait. p. 783 at the start condition, the first clock pul se is generated after the hold time. p. 794 the system requires a minimum of 300 ns hold time internally for the sda0n signal (at v ihmin . of scl0n signal) in order to occupy the undefined area at the falling edge of scl0n. p. 794 if the system does not extend the scl0n signal low hold time (t low ), only the maximum data hold time (t hd:dat ) needs to be satisfied. p. 794 i 2 c bus mode the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl0n signal?s low state hold time: t su:dat 250 ns ? if the system extends the scl0n signal?s low state hold time: transmit the following data bit to the sda0n line prior to the scl0n line release (t rmax . + t su:dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). p. 794 chapter 29 soft electrical specifica- tions a/d converter do not set (read/write) alternate- function ports during a/d conversion; otherwise the conversion resolution may be degraded. p. 795
v850es/jg3 appendix e list of cautions r01uh0015ej0300 rev.3.00 page 869 of 870 sep 30, 2010 (36/36) chapter classification function details of function cautions page chapter 29 soft electrical specifica- tions programming characteristics when writing initially to shipped products , it is counted as one rewrite for both ?erase to write? and ?write only?. example (p: write, e: erase) shipped product ?? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites p. 799 appendix a soft develop- ment tool rx850, rx850 pro to purchase the rx850 or rx850 pro, first fill in the purchase application form and sign the license agreement. p. 810 appendix d soft instruction set list instruction set do not specify the same regist er for general-purpose registers reg1 and reg3. p. 832
v850es/jg3 appendix f revision history r01uh0015ej0300 rev.3.00 page 870 of 870 sep 30, 2010 appendix f revision history f.1 major revisions in this edition page description p. 474 modification of caution in 15.6.10 receive data noise filter p. 474 modification of figure 15-15. timing of rxdan signal judged as noise p. 798 modification of flash memory programming characteristics p. 799 addition of remark to chapter 29 (3) programming characteristics f.2 revision history of previous editions a history of the revisions up to this edition is shown below. ?applied to:? indicates the chapters to which the revision was applied. edition description applied to: ? change of under development state of all products development completed pd70f3739gc-ueu-ax, 70f3740gc-ueu-ax, 70f3741gc-ueu-ax, 70f3742gc-ueu-ax throughout modification of figure 7-18 register setting for operation in external trigger pulse output mode modification of figure 7-22 register setting for operation in one-shot pulse output mode modification of figure 7-36 register setting in pulse width measurement mode chapter 7 16-bit timer/event counter p (tmp) modification of figure 8-18 register setting for operation in external trigger pulse output mode modification of figure 8-22 register setting for operation in one-shot pulse output mode modification of figure 8-36 register setting in pulse width measurement mode chapter 8 16-bit timer/event counter q (tmq) modification of table 13-2 conversion time selection in normal conversion mode (ada0hs1 bit = 0) modification of table 13-3 conversion time selection in high-speed conversion mode (ada0hs1 bit = 1) modification of figure 13-3 conversion operation timing (continuous conversion) chapter 13 a/d converter modification of figure 15-4 block diagram of asynchronous serial interface an chapter 15 asynchronous serial interface a (uarta) modification of 18.13 (4) (a) temporarily stop transfer of all dma channels modification of 18.13 (8) bus arbitration for cpu chapter 18 dma function (dma controller) modification of table 27-2 basic functions modification of table 27-3 security functions modification of table 27-4 security setting modification of figure 27-7 procedure for manipulating flash memory modification of table 27-7 flash memory control commands modification of figure 27-17 standard self programming flow modification of table 27-10 flash function list modification of table 27-11 internal resources used chapter 27 flash memory addition of chapter 29 (i) kyocera kinseki corporation: crystal resonator (t a = ? 10 to +70 c) addition of chapter 29 (ii) murata mfg. co. ltd.: ceramic resonator (t a = ? 20 to +80 c) chapter 29 electrical specifications addition of chapter 31 recommended soldering conditions chapter 31 recommended soldering conditions 2nd addition of appendix f revision history appendix f revision history
v850es/jg3 user?s manual: hardware publication date: rev.3.00 sep 30, 2010 published by: renesas electronics corporation
http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 7f, no. 363 fu shing north road taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2010 renesas electronics corporation. all rights reserved. colophon 1.0
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